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MT4C4001JECN-10/883C [AUSTIN]

1 MEG x 4 DRAM Fast Page Mode DRAM; 1 MEG ×4 DRAM的快速页面模式的DRAM
MT4C4001JECN-10/883C
型号： MT4C4001JECN-10/883C
厂家： AUSTIN SEMICONDUCTOR    AUSTIN SEMICONDUCTOR
描述：

1 MEG x 4 DRAM Fast Page Mode DRAM
1 MEG ×4 DRAM的快速页面模式的DRAM

内存集成电路 动态存储器 CD
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DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
1 MEG x 4 DRAM  
PIN ASSIGNMENT  
(Top View)  
Fast Page Mode DRAM  
20-Pin DIP (C, CN)  
20-Pin SOJ (ECJ),  
AVAILABLE AS MILITARY  
20 Vss  
20-Pin LCC (ECN), &  
20-Pin GullWing (ECG)  
DQ1  
DQ2  
WE\  
RAS\  
A9  
A0  
A1  
A2  
A3  
1
2
3
4
5
6
7
8
9
19 DQ4  
18 DQ3  
17 CAS\  
16 OE\  
15 A8  
14 A7  
13 A6  
12 A5  
11 A4  
SPECIFICATIONS  
• SMD 5962-90847  
• MIL-STD-883  
1
26  
25  
24  
23  
22  
DQ1  
DQ2  
WE\  
RAS\  
A9  
Vss  
2
3
4
5
DQ4  
DQ3  
CAS\  
OE\  
FEATURES  
• Industry standard x4 pinout, timing, functions, and  
packages  
9
18  
17  
16  
15  
14  
A8  
A7  
A6  
A5  
A4  
A0  
A1  
A2  
A3  
Vcc  
10  
11  
12  
13  
• High-performance, CMOS silicon-gate process  
• Single +5V±10% power supply  
• Low-power, 2.5mW standby; 300mW active, typical  
• All inputs, outputs, and clocks are fully TTL and CMOS  
compatible  
• 1,024-cycle refresh distributed across 16ms  
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\  
(CBR), and HIDDEN  
Vcc 10  
20-Pin DIP (CZ)  
OE\  
1
3
5
7
9
2
4
6
8
CAS\  
DQ4  
DQ1  
WE\  
DQ3  
Vss  
DQ2  
RAS\  
• FAST PAGE MODE access cycle  
• CBR with WE\ a HIGH (JEDEC test mode capable via  
WCBR)  
10 A9  
12 A1  
14 A3  
16 A4  
18 A6  
20 A8  
A0 11  
A2 13  
Vcc 15  
A5 17  
A7 19  
OPTIONS  
• Timing  
MARKING  
70ns access  
80ns access  
100ns access  
120ns access  
-7  
-8  
-10  
-12  
GENERAL DESCRIPTION  
The MT4C4001J is a randomly accessed solid-state  
memory containing 4,194,304 bits organized in a x4  
configuration. During READ or WRITE cycles each bit is  
uniquely addressed through the 20 address bits which are  
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the  
first 10 bits and CAS\ the later 10 bits. A READ or WRITE  
cycle is selected with the WE\ input. A logic HIGH on WE\  
dictates READ mode while a logic LOW on WE\ dictates  
WRITE mode. During a WRITE cycle, data-in (D) is latched  
by the falling edge of WE\ or CAS\, whichever occurs last. If  
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)  
remain open (High-Z) until the next CAS\ cycle. If WE\ goes  
LOW after data reaches the output pin(s), Qs are activated and  
retain the selected cell data as long as CAS\ remains low  
(regardless of WE\ or RAS\). This LATE WE\ pulse results in  
a READ-WRITE cycle. The four data inputs and four data  
outputs are routed through four pins using common I/O and  
pin direction is controlled by WE\ and OE\. FAST-PAGE-  
MODE operations allow faster data operations (READ,  
WRITE, or READ-MODIFY-WRITE) within a row address  
(A0-A9) defined page boundary. The FAST PAGE MODE  
(continued)  
• Packages  
Ceramic DIP (300 mil)  
Ceramic DIP (400 mil)  
Ceramic LCC*  
Ceramic ZIP  
Ceramic SOJ  
CN  
C
ECN  
CZ  
ECJ  
ECG  
No. 103  
No. 104  
No. 202  
No. 400  
No. 504  
No. 600  
Ceramic Gull Wing  
*NOTE: If solder-dip and lead-attach is desired on LCC  
packages, lead-attach must be done prior to the solder-  
dip operation.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
1
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
GENERAL DESCRIPTION (cont.)  
cycle is always initiated with a row address strobe-in by RAS\  
followed by a column address strobed-in by CAS\. CAS\ may  
be toggled-in by holding RAS\ LOW and strobing-in different  
column addresses, thus executing faster memory cycles.  
Returning RAS\ HIGH terminates the FAST PAGE MODE  
operation.  
Returning RAS\ and CAS\ HIGH terminates a memory cycle  
and decreases chip current to a reduced standby level. Also,  
the chip is preconditioned for the next cycle during the RAS\  
HIGH time. Memory cell data is retained in its corrected  
stated by maintaining power and executing any RAS\ cycle  
(READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or  
HIDDEN REFRESH) so that all 1,024 combinations of RAS\  
addresses (A0-A9) are executed at least every 16ms,  
regardless of sequence. The CBR REFRESH cycle will  
invoke the internal refresh counter for automatic RAS\  
addressing.  
FUNCTIONAL BLOCK DIAGRAM  
FAST PAGE MODE  
4
DATA IN  
BUFFER  
WE\  
CAS\  
DQ1  
DQ2  
DQ3  
DQ4  
*EARLY-WRITE  
DETECTION CIRCUIT  
4
DATA OUT  
BUFFER  
4
NO. 2 CLOCK  
GENERATOR  
OE\  
COLUMN  
ADDRESS  
BUFFER  
10  
COLUMN  
DECODER  
Vcc  
Vss  
10  
4
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
A9  
1024  
SENSE AMPLIFIERS  
I/O GATING  
REFRESH  
CONTROLLER  
1024 x 4  
REFRESH  
COUNTER  
10  
MEMORY  
ARRAY  
1024  
ROW ADDRESS  
BUFFERS (10)  
10  
10  
NO. 1 CLOCK  
GENERATOR  
RAS\  
NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE)  
CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
2
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
TRUTHTABLE  
ADDRESSES  
DATA IN/OUT  
tR  
tC  
DQ1-DQ4  
High-Z  
FUNCTION  
RAS\  
H
L
CAS\  
H X  
L
WE\  
X
H
OE\  
X
Standby  
READ  
X
X
L
X
ROW  
ROW  
ROW  
ROW  
n/a  
ROW  
n/a  
ROW  
n/a  
ROW  
ROW  
ROW  
X
COL  
COL  
COL  
COL  
COL  
COL  
COL  
COL  
COL  
n/a  
Data Out  
Data In  
Data Out/Data In  
Data Out  
EARLY-WRITE  
READ-WRITE  
FAST-PAGE-MODE  
READ  
FAST-PAGE-MODE  
EARLY-WRITE  
FAST-PAGE-MODE  
READ-WRITE  
L
L
L
L
L
L
L
L
L
L
L
L
H L  
H
H
L
L H  
L
1st Cycle  
2nd Cycle  
1st Cycle  
2nd Cycle  
1st Cycle  
2nd Cycle  
H L  
H L  
H L  
H L  
H L  
H L  
H
L
X
X
Data Out  
Data In  
Data In  
L
H L  
H L  
X
L H  
L H  
X
Data Out/Data In  
Data Out/Data In  
High-Z  
RAS\-ONLY REFRESH  
READ  
WRITE  
L H L  
L H L  
H L  
L
L
L
H
L
H
L
X
X
COL  
COL  
X
Data Out  
Data In  
High-Z  
HIDDEN REFRESH  
CAS\-BEFORE-RAS\ REFRESH  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
3
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
ABSOLUTE MAXIMUM RATINGS*  
*Stresses greater than those listed under "Absolute Maximum  
Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V Ratings" may cause permanent damage to the device. This is  
Storage Temperature.......................................-65oC to +150oC a stress rating only and functional operation of the device at  
Power Dissipation.................................................................1W these or any other conditions above those indicated in the  
Short Circuit Output Current...........................................50mA operation section of this specification is not implied.  
Lead Temperature (soldering 5 seconds).....................+270oC Exposure to absolute maximum rating conditions for extended  
periods may affect reliability.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS  
(NOTES: 1, 3, 4, 6, 7) (-55°C < TA < 125°C; VCC = 5V ±10%)  
PARAMETER/CONDITION  
Supply Voltage  
SYM  
MIN  
MAX  
UNITS  
NOTES  
4.5  
5.5  
V
VCC  
Input High (Logic 1) Voltage, All Inputs  
Input Low (Logic 0) Voltage, All Inputs  
2.4  
V
V
VIH  
VIL  
V
CC+0.5  
-0.5  
0.8  
INPUT LEAKAGE CURRENT  
-5  
5
5
µA  
µA  
Any Input 0V < VIN < 5.5V Vcc = 5.5V  
(All other pints not under test = 0V)  
OUTPUT LEAKAGE CURRENT  
II  
-5  
IOZ  
(Q is Disabled, 0V < VOUT < 5.5V) Vcc = 5.5V  
OUTPUT LEVELS  
2.4  
V
V
VOH  
VOL  
Output High Voltage (IOUT = -5mA)  
0.4  
Output Low Voltage (IOUT = 4.2mA)  
MAX  
-10  
PARAMETER/CONDITION  
STANDBY CURRENT (TTL)  
(RAS\ = CAS\ = VIH)  
SYM  
ICC1  
-7  
-8  
-12 UNITS NOTES  
4
4
4
2
4
2
mA  
mA  
STANDBY CURRENT (CMOS)  
2
2
ICC2  
(RAS\ = CAS\ = VCC -0.2V; all other inputs = VCC -0.2V)  
OPERATING CURRENT: Random READ/WRITE  
Average Power-Supply Current  
85  
75  
65  
45  
65  
65  
70  
40  
70  
70  
mA  
mA  
mA  
mA  
3, 4  
3, 4  
3
ICC3  
ICC4  
ICC5  
ICC6  
(RAS\, CAS\, Address Cycling: tRC = tRC(MIN))  
OPERATING CURRENT: FAST PAGE MODE  
Average Power-Supply Current  
60  
85  
85  
50  
75  
75  
(RAS\ = VIL, CAS\, Address Cycling: tPC = tPC (MIN))  
REFRESH CURRENT: RAS\-ONLY  
Average Power-Supply Current  
(RAS\ Cycling, CAS\ = VIH: tRC = tRC (MIN))  
REFRESH CURRENT: CAS\-BEFORE-RAS\  
Average Power-Supply Current  
3, 5  
(RAS\, CAS\, Address Cycling: tRC = tRC (MIN))  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
4
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
CAPACITANCE  
PARAMETER  
SYM  
MIN  
MAX  
UNITS  
NOTES  
Input Capacitance: A0-A10  
7
pF  
2
CI1  
Input Capacitance: RAS\, CAS\, WE\, OE\  
Input/Output Capacitance: DQ  
7
8
pF  
pF  
2
2
CI2  
CIO  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS  
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%)  
-7  
-8  
-10  
-12  
PARAMETER  
Random READ or WRITE cycle time  
READ-WRITE cycle time  
SYM  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS NOTES  
t
130  
150  
190  
220  
ns  
RC  
t
180  
40  
200  
45  
240  
55  
255  
70  
ns  
ns  
ns  
RWC  
t
FAST-PAGE-MODE READ or WRITE cycle time  
FAST-PAGE-MODE READ-WRITE cycle time  
Access time from RAS\  
PC  
t
90  
90  
110  
140  
PRWC  
t
t
70  
20  
80  
20  
90  
25  
45  
45  
120  
30  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
14  
15  
RAC  
CAC  
Access time from CAS\  
t
35  
40  
60  
Access time from column address  
Access time from CAS\ precharge  
RAS\ pulse width  
AA  
t
t
35  
40  
60  
CPA  
RAS  
70  
70  
20  
50  
20  
70  
10  
10  
20  
5
10,000  
80  
80  
20  
60  
20  
80  
10  
10  
20  
5
10,000  
100  
100  
25  
70  
25  
100  
12  
12  
25  
5
10,000  
120  
120  
30  
90  
30  
120  
15  
15  
25  
10  
0
100,000  
100,000  
t
100,000  
10,000  
100,000  
10,000  
100,000  
RAS\ pulse width (FAST PAGE MODE)  
RAS\ hold time  
RASP  
t
RSH  
t
RAS\ precharge time  
RP  
t
10,000  
CAS\ pulse width  
CAS  
CSH  
CPN  
t
t
CAS\ hold time  
16  
17  
CAS\ precharge time  
t
CAS\ precharge time (FAST PAGE MODE)  
RAS\ to CAS\ delay time  
CP  
t
50  
35  
60  
40  
75  
90  
60  
RCD  
t
CAS\ to RAS\ precharge time  
Row address setup time  
CRP  
t
0
0
0
ASR  
RAH  
RAD  
t
t
10  
15  
0
10  
15  
0
15  
20  
0
15  
20  
0
Row address hold time  
50  
18  
RAS\ to column address delay time  
Column address setup time  
t
ASC  
t
15  
50  
35  
0
15  
60  
40  
0
20  
70  
50  
0
25  
85  
60  
0
Column address hold time  
CAH  
t
Column address hold time (referenced to RAS\)  
Column address to RAS\ lead time  
Read command setup time  
AR  
t
RAL  
RCS  
RCH  
RRH  
t
t
t
0
0
0
0
19  
19  
Read command hold time (referenced to CAS\)  
Read command hold time (referenced to RAS\)  
CAS\ to output in Low-Z  
0
0
0
0
t
0
0
0
0
CLZ  
OFF  
t
0
20  
0
20  
0
20  
0
20  
20  
Output buffer turn-off delay  
t
0
0
0
0
21, 27  
WE\ command setup time  
WCS  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
5
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS  
(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C < TC < 125°C; VCC = 5V ±10%)  
-7  
-8  
-10  
-12  
PARAMETER  
Write command hold time  
SYM  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
UNITS NOTES  
15  
15  
20  
25  
ns  
t
WCH  
WCR  
50  
15  
20  
20  
0
60  
15  
20  
20  
0
70  
20  
25  
25  
0
80  
25  
30  
30  
0
ns  
ns  
ns  
ns  
t
Write command hold time (referenced to RAS\)  
Write command pulse width  
t
WP  
t
t
RWL  
CWL  
Write command to RAS\ lead time  
Write commend to CAS\ lead time  
Data-in setup time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
22  
22  
t
DS  
DH  
12  
50  
95  
60  
45  
3
15  
60  
105  
65  
45  
3
18  
70  
130  
80  
55  
3
25  
90  
140  
90  
60  
3
t
Data-in hold time  
t
DHR  
Data-in hold time (referenced to RAS\)  
RAS\ to WE\ delay time  
21  
21  
21  
t
RWD  
t
AWD  
CWD  
Column address to WE\ delay time  
CAS\ to WE\ delay time  
t
50  
16  
50  
16  
50  
16  
50  
16  
t
T
Transition time (rise or fall)  
t
REF  
RPC  
CSR  
CHR  
Refresh period (1,024 cycles)  
0
0
0
0
t
t
RAS\ to CAS\ precharge time  
5
10  
15  
10  
10  
10  
10  
0
10  
20  
10  
10  
10  
10  
0
10  
25  
10  
10  
10  
10  
0
5
CAS\ setup time (CAS\-BEFORE-RAS\ REFRESH)  
CAS\ hold time (CAS\-BEFORE-RAS\ REFRESH)  
WE\ hold time (CAS\-BEFORE-RAS\ REFRESH)  
WE\ setup time (CAS\-BEFORE-RAS\ REFRESH)  
WE\ hold time (WCBR test cycle)  
WE\ setup time (WCBR test cycle)  
OE\ setup prior to RAS during HIDDEN REFRESH cycle  
Output disable  
10  
10  
10  
10  
10  
0
5
t
25, 28  
25, 28  
25, 28  
25, 28  
t
WRH  
t
t
WRP  
WTH  
t
WTS  
t
ORD  
15  
15  
20  
20  
25  
25  
25  
25  
27  
23  
26  
t
OD  
t
OE  
OEH  
Output enable  
20  
20  
25  
25  
t
OE\ hold time from WE\ during READ-MODIFY-WRITE cycle  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
6
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
NOTES:  
point only; if tRAD is greater than the specified tRAD (MAX)  
limit, then access time is controlled exclusively by tAA  
1. All voltages referenced to Vss.  
2. This parameter is sampled, not 100% tested. Capacitance  
is measured with Vcc=5V, f=1 MHz at less than 50mVrms,  
TA = 25°C ±3°C, Vbias = 2.4V applied to each input and  
output individually with remaining inputs and outputs open.  
3. Icc is dependent on cycle rates.  
4. Icc is dependent on output loading and cycle rates.  
Specified values are obtained with minimum cycle time and  
the output open.  
5. Enables on-chip refresh and address counters.  
6. The minimum specifications are used only to indicate cycle  
time at which proper operation over the full temperature range  
.
19. Either tRCH or tRRH must be satisfied for a READ cycle.  
20. tOFF (MAX) defines the time at which the output achieves  
the open circuit conditions and is not referenced to VOH or  
VOL  
21. tWCS, tRWD, tAWD, and tCWD are not restrictive operating  
parameters. tWCS applies to EARLY-WRITE cycles. tRWD  
AWD, and tCWD apply to READ-MODIFY-WRITE cycles.  
.
,
t
If tWCS > tWCS (MIN), the cycle is an EARLY-WRITE cycles  
and the data output will remain an open circuit throughout the  
entire cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and  
(-55°C < TA < 125°C) is assured.  
7. An initial pause of 100µs is required after power-up  
followed by eight RAS\ refresh cycles (RAS\-ONLY or CBR  
with WE\ HIGH) before proper device operation is assured.  
The eight RAS\ cycle wake-up should be repeated any time  
the 16ms refresh requirement is exceeded.  
tCWD > tCWD (MIN), the cycle is a READ-MODIFY-WRITE  
and the data output will contain data read from the selected  
cell. If neither of the above conditions is met, the state of the  
data out is indeterminate. OE\ held HIGH and WE\ taken LOW  
after CAS\ goes LOW results in a LATE-WRITE (OE\  
8. AC characteristics assume tT = 5ns.  
controlled) cycle. tWCS, tRWD, tCWD, and tAWD are not  
applicable in a LATE-WRITE cycle.  
22. These parameters are referenced to CAS\ leading edge in  
EARLY-WRITE cycle and WE\ leading edge in LATE-WRITE  
cycles and WE\ leading edge in LATE-WRITE or  
READ-MODIFY-WRITE cycle.  
9. VIH (MIN) and VIL (MAX) are reference levels for  
measuring timing of input signals. Transition times are  
measured between VIH and VIL (or between VIL and VIH).  
10. In addition to meeting the transition rate specification, all  
input signals must transit between VIH and VIL (or between  
VIL and VIH) in a monotonic manner.  
23. If OE\ is tied permanently LOW, LATE-WRITE or  
READ-MODIFY-WRITE operations are not possible.  
24. A HIDDEN REFRESH may also be performed after a  
WRITE cycle. In this case, WE\=LOW and OE\=HIGH.  
11. If CAS\ = VIH, data outputs (DQs) are High-Z.  
12. If CAS\ = VIL, data outputs (DQs) may contain data from  
the last valid READ cycle.  
25. tWTS and tWTH are setup and hold specifications for the  
WE\ pin being held LOW to enable the JEDEC test mode (with  
CBR timing constraints). These two parameters are the  
13. Measured with a load equivalent to two TTL gates and  
100pF.  
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than  
the maximum recommended value shown in this table, tRAC  
will increase by the amount that tRCD exceeds the value shown.  
inverts of tWRP and tWRH in the CBR REFRESH cycle.  
26. LATE-WRITE and READ-MODIFY-WRITE cycles must  
have both tOD and tOEH met (OE\ HIGH during WRITE cycle)  
in order to ensure that the output buffers will be open during  
the WRITE cycle. The DQs will provide the previously read  
data if CAS\ remains LOW and OE\ is taken back LOW after  
15. Assumes that tRCD > tRCD (MAX)  
16. If CAS\ is LOW at the falling edge of RAS\, DQs will be  
maintained from the previous cycle. To initiate a new cycle  
and clear the data out buffer, CAS\ must be pulsed HIGH for  
tOEH is met. If CAS\ goes HIGH prior to OE\ going back LOW,  
the DQs will remain open.  
tCPN  
.
17. Operation within the tRCD (MAX) limit ensures that tRAC  
(MAX) can be met. tRCD (MAX) is specified as a reference  
point only; if tRCD is greater than the specified tRCD (MAX)  
27. The DQs open during READ cycles once tOD or tOFF  
occur. If CAS\ goes HIGH first, OE\ becomes a “don’t care.”  
If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a “don’t  
care;” and the DQs will provide the previously read data if  
OE\ is taken back LOW (while CAS\ remains LOW).  
28. JEDEC test mode only.  
limit, then access time is controlled exclusively by tCAC  
.
18. Operation within the tRAD (MAX) limit ensures that tRCD  
(MAX) can be met. tRAD (MAX) is specified as a reference  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
7
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
READ CYCLE  
EARLY-WRITE CYCLE  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
8
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
READ-WRITE CYCLE  
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)  
FAST-PAGE-MODE READ CYCLE  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
9
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
FAST-PAGE-MODE EARLY-WRITE CYCLE  
FAST-PAGE-MODE READ-WRITE CYCLE  
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)  
*tPC = LATE-WRITE cycle  
tPRWC = FAST READ-MODIFY-WRITE cycle  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
10  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
RAS\-ONLY REFRESH CYCLE  
(ADDR = A0-A9;WE\ = Don’t Care)  
CAS\-BEFORE-RAS\ REFRESH CYCLE  
(A0-A9, and OE\ = DON’T CARE)  
HIDDEN REFRESH CYCLE24  
(WE\ = HIGH, OE\ = LOW)  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
11  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
4 MEG POWER-UP AND REFRESH  
POWER-UP  
The 4 Meg JEDEC test mode constraint may introduce  
another problem. The 1 Meg POWER-UP cycle requires a  
100µs delay followed by any eight RAS\ cycles. The 4 Meg  
POWER-UP is more restrictive in that eight RAS\-ONLY or  
CBR REFRESH (WE\ held HIGH) cycles must be used. The  
restriction is needed since the 4 Meg may power-up in the  
JEDEC specified test mode and must exit out of the test mode.  
The only way to exit the 4 Meg JEDEC test mode is with  
either a RAS\-ONLY or a CBR REFRESH cycle  
(WE\ held HIGH).  
CONSTRAINTS  
The EIA/JEDEC 4 Meg DRAM introduces two potential  
incompatibilities compared to the previous generation  
1 Meg DRAM. The incompatibilities involve refresh and  
power-up. Understanding these incompatibilities and  
providing for them will offer the designer and system user  
greater compatibility between the 1 Meg and 4 Meg.  
REFRESH  
The most commonly used refresh mode of the 1 Meg is  
the CBR (CAS\-BEFORE-RAS\) REFRESH cycle. The CBR  
for the 1 Meg specifies the WE\ pin as a “don’t care.” The 4  
Meg, on the other hand, specifies the CBR REFRESH mode  
with the WE\ pin held at a voltage HIGH level.  
A CBR cycle with WE\ LOW will put the 4 Meg into the  
JEDEC specified test mode (WCBR).  
SUMMARY  
1. The 1 Meg CBR REFRESH allows the WE\ pin to be “don’t  
care” while the 4 Meg CBR requires WE\ to be HIGH.  
2. The eight RAS\ wake-up cycles on the 1 Meg may be any  
valid RAS\ cycle while the 4 Meg may only use RAS\-ONLY  
or CBR REFRESH cycles (WE\ held HIGH).  
COMPARISON OF 4 MEGTEST MODE AND WCBRTO 1 MEG CBR  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
12  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITIONS*  
ASI Case #103 (Package Designator CN)  
SMD 5962-90847, Case Outline R  
D
A
Q
L
E
e
b
S1  
b2  
Pin 1  
R
eA  
c
SMD Specifications  
SYMBOL  
MIN  
---  
0.014  
0.045  
0.008  
---  
MAX  
0.200  
0.026  
0.065  
0.018  
1.060  
0.310  
A
b
b2  
c
D
E
0.220  
eA  
e
0.300 BSC  
0.100 BSC  
Q
L
S1  
R
0.015  
0.125  
0.005  
90°  
0.070  
0.200  
---  
105°  
NOTE: These dimensions are per the SMD. ASI's package dimensional limits  
may differ, but they will be within the SMD limits.  
* All measurements are in inches.  
MT4C4001J  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 1.5 10/02  
13  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITIONS*  
ASI Case #104 (Package Designator C)  
SMD 5962-90847, Case Outline U  
D
D1  
A
Q
L
E
e
b
S1  
b2  
Pin 1  
eA  
c
SMD Specifications  
SYMBOL  
MIN  
---  
MAX  
0.175  
0.021  
0.065  
0.014  
1.030  
0.910  
0.410  
0.420  
A
b
b2  
c
D
D1  
E
0.015  
0.045  
0.008  
0.980  
0.890  
0.380  
0.385  
eA  
e
0.100 BSC  
Q
L
S1  
0.015  
0.125  
---  
0.060  
0.200  
0.070  
NOTE: These dimensions are per the SMD. ASI's package dimensional limits  
may differ, but they will be within the SMD limits.  
* All measurements are in inches.  
MT4C4001J  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 1.5 10/02  
14  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITIONS*  
ASI Case #400 (Package Designator CZ)  
SMD 5962-90847, Case Outline N  
SMD SPECIFICATIONS  
SYMBOL  
MIN  
MAX  
0.405  
0.023  
0.045  
0.015  
0.055  
0.115  
1.065  
0.130  
0.200  
0.050  
A
b
b2  
c
0.355  
0.016  
0.035  
0.008  
0.045  
0.085  
1.035  
0.100  
0.125  
0.015  
e
eA  
D
E
L
L1  
NOTE: These dimensions are per the SMD. ASI's package dimensional limits  
may differ, but they will be within the SMD limits.  
* All measurements are in inches.  
MT4C4001J  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 1.5 10/02  
15  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
ASI Case #202 (Package Designator ECN)  
SMD 5962-90847, Case Outline T  
L1  
S
e
E1  
E
b
R
L
D
A
A1  
SMD SPECIFICATIONS  
SYMBOL  
MIN  
MAX  
A
A1  
b
D
E
0.060  
0.080  
0.035 TYP  
0.050 TYP  
0.022  
0.343  
0.665  
0.590  
0.028  
0.357  
0.685  
0.610  
E1  
e
L
L1  
R
0.045  
0.080  
0.006  
0.025  
0.055  
0.100  
0.010  
0.050  
S
NOTE: These dimensions are per the SMD. ASI's package dimensional limits  
may differ, but they will be within the SMD limits.  
* All measurements are in inches.  
MT4C4001J  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
Rev. 1.5 10/02  
16  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITION*  
ASI Case #504 (Package Designator ECJ)  
A
b1  
b2  
e
L
D
D1  
E1  
b
A1  
E
ASI SPECIFICATIONS  
SYMBOL  
MIN  
MAX  
0.140  
0.078  
0.028  
A
A1  
b
0.120  
0.066  
0.022  
b1  
b2  
D
D1  
E
E1  
e
L
0.050 TYP  
0.090  
0.665  
0.592  
0.345  
0.345  
0.045  
0.057  
0.11  
0.685  
0.608  
0.355  
0.360  
0.055  
0.063  
*All measurements are in inches.  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
17  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITION*  
ASI Case #600 (Package Designator ECG)  
ASI PACKAGE SPECIFICATIONS  
SYMBOL  
MIN  
MAX  
0.140  
0.078  
0.028  
A
A1  
b
0.120  
0.066  
0.022  
b1  
b2  
D
D1  
E
E1  
E2  
e
0.050 TYP  
0.090  
0.665  
0.592  
0.345  
0.482  
0.442  
0.045  
0.110  
0.685  
0.608  
0.355  
0.498  
0.458  
0.055  
e1  
L
0.014 Dia. TYP  
0.057  
0.063  
*All measurements are in inches.  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
18  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
ORDERING INFORMATION  
EXAMPLE: MT4C4001JCN-8/883C  
EXAMPLE: MT4C4001JC-12/883C  
Device  
Number  
MT4C4001J  
MT4C4001J  
MT4C4001J  
MT4C4001J  
Package  
Type  
CN  
Device  
Number  
MT4C4001J  
MT4C4001J  
MT4C4001J  
MT4C4001J  
Package  
Type  
C
Speed ns Process  
Speed ns Process  
-7  
/*  
/*  
/*  
/*  
-7  
-8  
/*  
/*  
/*  
/*  
CN  
CN  
CN  
-8  
C
C
C
-10  
-12  
-10  
-12  
EXAMPLE: MT4C4001JCZ-7/883C  
EXAMPLE: MT4C4001JECN-10/XT  
Device  
Number  
MT4C4001J  
MT4C4001J  
MT4C4001J  
MT4C4001J  
Package  
Type  
CZ  
Device  
Number  
MT4C4001J  
MT4C4001J  
MT4C4001J  
MT4C4001J  
Package  
Type  
ECN  
ECN  
ECN  
Speed ns Process  
Speed ns Process  
-7  
/*  
/*  
/*  
/*  
-7  
/*  
/*  
/*  
/*  
CZ  
CZ  
CZ  
-8  
-8  
-10  
-12  
-10  
-12  
ECN  
EXAMPLE: MT4C4001JECJ-7/IT  
EXAMPLE: MT4C4001JECG-12/IT  
Device  
Number  
MT4C4001J  
MT4C4001J  
MT4C4001J  
MT4C4001J  
Package  
Type  
ECJ  
Device  
Number  
MT4C4001J  
MT4C4001J  
MT4C4001J  
MT4C4001J  
Package  
Type  
ECG  
ECG  
ECG  
Speed ns Process  
Speed ns Process  
-7  
/*  
/*  
/*  
/*  
-7  
/*  
/*  
/*  
/*  
ECJ  
ECJ  
ECJ  
-8  
-8  
-10  
-12  
-10  
-12  
ECG  
*AVAILABLE PROCESSES  
IT = Industrial Temperature Range  
XT = Extended Temperature Range  
883C = Full Military Processing  
-40oC to +85oC  
-55oC to +125oC  
-55oC to +125oC  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
19  
DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
ASI TO DSCC PART NUMBER  
CROSS REFERENCE*  
ASI Package Designator CZ  
ASI Package Designator C  
ASI Part #  
SMD Part #  
ASI Part #  
SMD Part #  
MT4C4001JCZ-8/883C  
MT4C4001JCZ-10/883C  
MT4C4001JCZ-12/883C  
5962-9084703MNA  
5962-9084702MNA  
5962-9084701MNA  
MT4C4001JC-8/883C  
MT4C4001JC-10/883C  
MT4C4001JC-12/883C  
5962-9084703MUA  
5962-9084702MUA  
5962-9084701MUA  
ASI Package Designator CN  
ASI Package Designator ECN  
ASI Part #  
SMD Part #  
ASI Part #  
SMD Part #  
MT4C4001JCN-8/883C  
MT4C4001JCN-10/883C  
MT4C4001JCN-12/883C  
5962-9084703MRA  
5962-9084702MRA  
5962-9084701MRA  
MT4C4001JECN-8/883C  
MT4C4001JECN-10/883C  
MT4C4001JECN-12/883C  
5962-9084703MTA  
5962-9084702MTA  
5962-9084701MTA  
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
20  

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