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MT5C2561EC-45L/IT [AUSTIN]

MT5C2561 SRAM MEMORY ARRAY; MT5C2561 SRAM存储器阵列
MT5C2561EC-45L/IT
型号： MT5C2561EC-45L/IT
厂家： AUSTIN SEMICONDUCTOR    AUSTIN SEMICONDUCTOR
描述：

MT5C2561 SRAM MEMORY ARRAY
MT5C2561 SRAM存储器阵列

存储 静态存储器
文件： 总11页 (文件大小：122K)
中文：  中文翻译
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SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
256K x 1 SRAM  
PIN ASSIGNMENT  
SRAM MEMORY ARRAY  
(Top View)  
AVAILABLE AS MILITARY  
SPECIFICATIONS  
• SMD 5962-88725  
• SMD 5962-88544  
• MIL-STD-883  
24-Pin DIP (C)  
(300 MIL)  
A6  
A7  
A8  
1
2
3
4
5
6
7
8
9
10  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Vcc  
A5  
A4  
A3  
A2  
FEATURES  
A9  
• High Speed: 35, 45, 55, and 70  
• Battery Backup: 2V data retention  
• Low power standby  
• High-performance, low-power, CMOS double-metal  
process  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE\  
• All inputs and outputs are TTL compatible  
A10  
A11  
A14  
A15  
A0  
A1  
A17  
A16  
A13  
A12  
D
Q
WE\ 11  
Vss 12  
CE\  
28-Pin LCC (EC)  
OPTIONS  
• Timing  
MARKING  
3
2 1 28 27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
35ns access  
45ns access  
55ns access  
70ns access  
-35  
-45  
-55*  
-70*  
NC  
A4  
NC  
A9  
A10  
A11  
A14  
A15  
A0 10  
Q 11  
NC 12  
4
5
6
7
8
9
A3  
A2  
A1  
A17  
A16  
A13  
NC  
• Package(s)  
13 14 15 16 17  
Ceramic DIP (300 mil)  
CeramicLCC  
C
EC  
No. 106  
No. 204  
• Operating Temperature Ranges  
Industrial (-40oC to +85oC)  
IT  
XT  
GENERAL DESCRIPTION  
Military (-55oC to +125oC)  
The Austin Semiconductor SRAM family employs  
high-speed, low-power CMOS and are fabricated using double-  
layer metal, double-layer polysilicon technology.  
• 2V data retention/low power  
L
For flexibility in high-speed memory applications,  
Austin Semiconductor offers chip enable (CE\) on all organiza-  
tions. This enhancement can place the outputs in High-Z for  
additional flexibility in system design. The x1 configuration  
features separate data input and output.  
*Electrical characteristics identical to those provided for the 45ns  
access devices.  
Writing to these devices is accomplished when write  
enable (WE\) and CE\ inputs are both LOW. Reading is accom-  
plished when WE\ remains HIGH and CE\ goes LOW. The  
device offers a reduced power standby mode when disabled.  
This allows system designs to achieve low standby power re-  
quirements.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
These devices operate from a single +5V power sup-  
ply and all inputs and outputs are fully TTL compatible.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
1
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
FUNCTIONAL BLOCK DIAGRAM  
VCC  
GND  
A13  
A14  
A15  
A16  
A17  
A0  
D
Q
262,144-BIT  
MEMORY ARRAY  
A1  
CE\  
A2  
A3  
A4  
WE\  
POWER  
DOWN  
COLUMN DECODER  
A5 A6 A7 A8 A9 A10 A11 A12  
TRUTHTABLE  
MODE  
CE\ WE\  
DQ  
POWER  
STANDBY  
READ  
WRITE  
H
L
L
X
H
L
HIGH-Z STANDBY  
Q
ACTIVE  
ACTIVE  
HIGH-Z  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
2
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
*Stresses greater than those listed under "Absolute Maximum  
Voltage on Any Pin Relative to Vss..................................-0.5V to +7V Ratings" may cause permanent damage to the device. This is  
ABSOLUTE MAXIMUM RATINGS*  
Voltage on Vcc Supply Relative to Vss.............................-0.5V to +7V  
Voltage Applied to Q.........................................................-0.5V to +6V  
Storage Temperature......................................................-65oC to +150oC  
Power Dissipation..............................................................................1W  
Short Circuit Output Current.........................................................50mA  
Lead Temperature (soldering 10 seconds)....................................+260oC  
Junction Temperature..................................................................+175oC  
a stress rating only and functional operation of the device at  
these or any other conditions above those indicated in the  
operation section of this specification is not implied. Exposure  
to absolute maximum rating conditions for extended periods  
may affect reliability.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS  
(-55oC < TC < 125oC; VCC = 5V +10%)  
DESCRIPTION  
CONDITIONS  
MIN  
MAX  
UNITS  
NOTES  
SYM  
2.2  
V
1
VIH  
VCC+0.5  
Input High (Logic 1) Voltage  
-0.5  
-10  
0.8  
10  
V
1, 2  
VIL  
ILI  
Input Low (Logic 0) Voltage  
Input Leakage Current  
µA  
0V<VIN<VCC  
Output(s) disabled  
0V<VOUT<VCC  
Output Leakage Current  
-10  
2.4  
10  
µA  
ILO  
Output High Voltage  
Output Low Voltage  
V
V
1
1
IOH = -4.0mA  
VOH  
VOL  
0.4  
I
OL = 8.0mA  
MAX  
PARAMETER  
CONDITIONS  
SYM  
-35  
-45 UNITS NOTES  
Power Supply  
Current: Operating  
120  
120  
100  
25  
mA  
mA  
mA  
3
3
ICCSP  
CE\ < VIL; VCC = MAX  
f = MAX = 1/tRC (MIN)  
Output Open  
100  
25  
ICCLP  
CE\ > VIH; All Other Inputs  
< VIL or > VIH, VCC = MAX  
f = 0 Hz  
Power Supply  
Current: Standby  
ISBT1  
CE\ > VCC -0.2V; VCC = MAX  
VIL < VSS +0.2V  
VIH > VCC -0.2V; f = 0 Hz  
ISBCSP  
20  
3
20  
3
mA  
mA  
ISBCLP  
"L" Version Only  
CAPACITANCE  
PARAMETER  
CONDITIONS  
SYM  
MAX  
UNITS  
NOTES  
TA = 25oC, f = 1MHz  
Vcc = 5V  
Input Capacitance  
CI  
10  
12  
pF  
4
Output Capacitance  
CO  
pF  
4
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
3
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS  
(Note 5) (-55oC < TC < 125oC;VCC = 5V +10%)  
-35  
-45  
DESCRIPTION  
MIN  
MAX  
MIN  
MAX  
UNITS NOTES  
SYMBOL  
READ CYCLE  
tRC  
tAA  
tACE  
tOH  
READ cycle time  
35  
45  
ns  
ns  
ns  
ns  
Address access time  
35  
35  
45  
45  
Chip Enable access time  
Output hold from address change  
3
3
3
3
tLZCE  
tHZCE  
tPU  
ns  
ns  
ns  
ns  
7
6, 7  
4
Chip Enable to output in Low-Z  
Chip disable to output in High-Z  
Chip Enable to power-up time  
Chip disable to power-down time  
WRITE CYCLE  
20  
35  
20  
45  
0
0
tPD  
4
tWC  
tCW  
tAW  
WRITE cycle time  
35  
30  
30  
0
45  
40  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable to end of write  
Address valid to end of write  
Address setup time  
tAS  
tAH  
Address hold from end of write  
WRITE pulse width  
5
5
tWP  
30  
20  
0
40  
20  
0
tDS  
Data setup time  
tDH  
Data hold time  
tLZWE  
tHZWE  
Write disable to output in Low-Z  
Write Enable to output in High-Z  
0
0
7
0
15  
0
20  
6, 7  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
4
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
ACTEST CONDITIONS  
Input pulse levels ...................................... Vss to 3.0V  
Input rise and fall times ......................................... 5ns  
Input timing reference levels ................................ 1.5V  
Output reference levels ....................................... 1.5V  
Output load ................................. See Figures 1 and 2  
167Ω  
167Ω  
Q
Q
VTH =1.73V  
VTH =1.73V  
5pF  
30pF  
Fig. 2 Output Load  
Equivalent  
Fig. 1 Output Load  
Equivalent  
allowing for actual tester RC time constant.  
NOTES  
7. At any given temperature and voltage condition, tHZCE is  
less than tLZCE, and tHZWE is less than tLZWE and tHZOE is  
1. All voltages referenced to VSS (GND).  
2. -3V for pulse width < 20ns  
3. ICC is dependent on output loading and cycle rates.  
The specified value applies with the outputs  
less than tLZOE  
.
8. WE\ is HIGH for READ cycle.  
9. Device is continuously selected. Chip enable is held in  
its active state.  
10. Address valid prior to, or coincident with, latest  
occurring chip enable.  
11. tRC = Read Cycle Time.  
12. Chip enable (CE\) and write enable (WE\) can initiate and  
terminate a WRITE cycle.  
unloaded, and f =  
1
Hz.  
tRC (MIN)  
4. This parameter is guaranteed but not tested.  
5. Test conditions as specified with the output loading  
as shown in Fig. 1 unless otherwise noted.  
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE are  
specified with CL = 5pF as in Fig. 2. Transition is  
measured ±200mV typical from steady state voltage,  
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)  
DESCRIPTION  
CONDITIONS  
SYM  
MIN  
MAX UNITS NOTES  
VCC for Retention Data  
2
---  
V
VDR  
CE\ > (VCC - 0.2V)  
µA  
Data Retention Current  
VCC = 2V ICCDR  
900  
VIN > (VCC - 0.2V)  
or < 0.2V  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
0
---  
ns  
ns  
4
Operation Recovery Time  
4, 11  
tRC  
LOWVcc DATA RETENTIONWAVEFORM  
DATA RETENTION MODE  
VCC  
4.5V  
4.5V  
VDR > 2V  
tCDR  
tR  
VIH  
VIL  
VDR  
CE\  
DON’T CARE  
UNDEFINED  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
5
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
READ CYCLE NO. 1 8, 9  
t
RC
VALID  
ADDRESS  
Q  
t
AA
tOH  
PREVIOUS DATA VALID  
DATA VALID  
READ CYCLE NO. 2 7, 8, 10  
tR  
C
CE\  
tLZCE  
tHZCE  
t
E  
ACE  
DATA VALID  
Q  
Icc  
t
PU  
tP  
D
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
6
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
WRITE CYCLE NO. 1 12  
(Chip Enabled Controlled)  
tWC  
ADDRESS  
tA  
W
tAH  
tAS  
tCW  
CE\  
t
WP  
WE\  
tDH  
t
DS  
DATA VAILD  
D
Q
HIGH Z  
7, 12  
WRITE CYCLE NO. 2  
(Write Enabled Controlled)  
tW  
C
ADDRESS  
tAW  
tAW  
tAH  
tCW  
CE\  
tAS  
t
WP  
WE\  
tDS  
tDH  
tDH  
D
Q
DATA VALID  
tHZWE  
tLZWE  
HIGH-Z  
DON’T CARE  
UNDEFINED  
NOTE: Output enable (OE\) is inactive (HIGH).  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
7
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITIONS*  
ASI Case #106 (Package Designator C)  
SMD #5962-88544 & #5962-88725, Case Outline L  
D
A
Q
L
Pin 1  
b
e
S1  
b2  
E
NOTE  
c
0o to 15o  
eA  
SMD SPECIFICATIONS  
SYMBOL  
MIN  
---  
0.014  
0.045  
0.008  
---  
MAX  
0.200  
0.026  
0.065  
0.018  
1.280  
0.310  
A
b
b2  
c
D
E
0.220  
eA  
e
0.300 BSC  
0.100 BSC  
L
Q
S1  
0.125  
0.015  
0.005  
0.200  
0.060  
---  
NOTE: These dimensions are per the SMD. ASI's package dimensional limits  
may differ, but they will be within the SMD limits.  
*All measurements are in inches.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
8
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
MECHANICAL DEFINITIONS*  
ASI Case #204 (Package Designator EC)  
SMD# 5962-88544, Case Outline X  
D1  
B2  
D2  
L2  
e
E3  
E
E1  
E2  
h x 45o  
D
L
hx45o  
B1  
D3  
A
A1  
SMD SPECIFICATIONS  
SYMBOL  
MIN  
MAX  
0.120  
0.088  
0.028  
A
A1  
B1  
B2  
D
0.060  
0.050  
0.022  
0.072 REF  
0.342  
0.358  
D1  
D2  
D3  
E
0.200 BSC  
0.100 BSC  
---  
0.540  
0.358  
0.560  
E1  
E2  
E3  
e
0.400 BSC  
0.200 BSC  
---  
0.558  
0.050 BSC  
0.040 REF  
h
L
L2  
0.045  
0.075  
0.055  
0.095  
NOTE: These dimensions are per the SMD. ASI's package dimensional limits  
may differ, but they will be within the SMD limits.  
*All measurements are in inches.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
9
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
ORDERING INFORMATION  
EXAMPLE: MT5C2561EC-70/XT  
EXAMPLE: MT5C2561C-45L/IT  
Device  
Number  
Package Speed  
Device  
Number  
Package Speed  
Options** Process  
Options** Process  
Type  
ns  
Type  
ns  
MT5C2561  
MT5C2561  
MT5C2561  
MT5C2561  
C
-35  
L
L
L
L
/*  
/*  
/*  
/*  
MT5C2561  
MT5C2561  
MT5C2561  
MT5C2561  
EC  
-35  
L
L
L
L
/*  
/*  
/*  
/*  
C
C
C
-45  
-55  
-70  
EC  
EC  
EC  
-45  
-55  
-70  
*AVAILABLE PROCESSES  
IT = Industrial Temperature Range  
XT = Extended Temperature Range  
883C = Full Military Processing  
-40oC to +85oC  
-55oC to +125oC  
-55oC to +125oC  
** OPTIONS  
L = 2V Data Retention/Low Power  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
10  
SRAM  
MT5C2561  
Austin Semiconductor, Inc.  
ASI TO DSCC PART NUMBER  
CROSS REFERENCE*  
ASI Package Designator C  
ASI Package Designator EC  
ASI Part #  
SMD Part #  
5962-8872501LX  
5962-8872502LX  
5962-8872503LX  
5962-8872504LX  
ASI Part #  
SMD Part #  
5962-8872501XX  
5962-8872502XX  
5962-8872503XX  
5962-8872504XX  
MT5C2561C-35/883C  
MT5C2561C-45/883C  
MT5C2561C-55/883C  
MT5C2561C-70/883C  
MT5C2561EC-35/883C  
MT5C2561EC-45/883C  
MT5C2561EC-55/883C  
MT5C2561EC-70/883C  
MT5C2561C-35L883C  
MT5C2561C-45L883C  
MT5C2561C-55L883C  
MT5C2561C-70L883C  
5962-8854401LX  
5962-8854402LX  
5962-8854403LX  
5962-8854404LX  
MT5C2561EC-35L883C  
MT5C2561EC-45L883C  
MT5C2561EC-55L883C  
MT5C2561EC-70L883C  
5962-8854401XX  
5962-8854402XX  
5962-8854403XX  
5962-8854404XX  
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C2561  
Rev. 2.5 1/01  
11  

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