MT5C2564EC-40/883C [AUSTIN]
64K x 4 SRAM SRAM MEMORY ARRAY; 64K ×4的SRAM SRAM存储器阵列
| 型号： | MT5C2564EC-40/883C |
| 厂家： | 
AUSTIN SEMICONDUCTOR |
| 描述： | 64K x 4 SRAM SRAM MEMORY ARRAY |
| 文件： | 总12页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRAM
MT5C2564
Austin Semiconductor, Inc.
64K x 4 SRAM
SRAM MEMORY ARRAY
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
• SMD 5962-88681
• SMD 5962-88545
• MIL-STD-883
24-Pin DIP (C)
(300 MIL)
28-Pin LCC (EC)
3
2 1 28 27
FEATURES
A0
A1
A2
A3
A4
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
A15
A14
A13
A12
A11
A10
DQ4
DQ3
DQ2
A15
A14
A13
A12
A11
A10
DQ4
DQ3
DQ2
DQ1
WE\
A2
A3
A4
A5
A6
A7
A8 1 0
A9 1 1
CE\ 1 2
4
5
6
7
8
9
• High Speed: 15, 20, 25, 35, 45, 55, and 70
• Battery Backup: 2V data retention
• Low power standby
• High-performance, low-power, CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\
• All inputs and outputs are TTL compatible
A9 10
CE\ 11
Vss 12
13 14 15 16 17
28-Pin Flat Pack (F)
OPTIONS
• Timing
MARKING
1
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE\
NC
Vss
Vcc
2
A15
A14
A13
A12
A11
A10
NC
3
15ns access
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-15
-20
-25
-35
-45
-55*
-70*
4
5
6
7
8
9
NC
1 0
1 1
1 2
1 3
1 4
DQ3
DQ2
DQ1
DQ0
WE\
• Package(s)
Ceramic DIP (300 mil)
CeramicLCC
Ceramic Flatpack
C
EC
F
No. 106
No. 204
GENERAL DESCRIPTION
• OperatingTemperature Ranges
Industrial (-40oC to +85oC)
Military (-55oC to +125oC)
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS and are fabricated using double-
layer metal, double-layer polysilicon technology.
IT
XT
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) on all
organizations. This enhancement can place the outputs in
High-Z for additional flexibility in system design. The x4
configuration features common data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is
accomplished when WE\ remains HIGH and CE\ goes LOW.
The device offers a reduced power standby mode when
disabled. This allows system designs to achieve low standby
power requirements.
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
For more products and information
please visit our web site at
www.austinsemiconductor.com
These devices operate from a single +5V power
supply and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
1
SRAM
MT5C2564
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
A0
A1
DQ4
A2
A3
262,144-BIT
MEMORY ARRAY
A4
A5
A13
A14
A15
DQ1
CE\
COLUMN DECODER
WE\
A6 A7 A8 A9 A10 A11 A12
POWER
DOWN
TRUTHTABLE
MODE
STANDBY
READ
CE\
H
L
WE\
X
H
DQ
HIGH-Z
Q
POWER
STANDBY
ACTIVE
WRITE
L
L
D
ACTIVE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
2
SRAM
MT5C2564
Austin Semiconductor, Inc.
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage onAny Pin Relative to Vss..................................-0.5V to +7V
Voltage on Vcc Supply Relative to Vss.............................-0.5V to +7V
Storage Temperature......................................................-65oC to +150oC
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................50mA
Lead Temperature (soldering 10 seconds)....................................+260oC
Junction Temperature..................................................................+175oC
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
2.2
V
1
VIH
VCC+0.5
Input Low (Logic 0) Voltage
Input Leakage Current
-0.5
-10
0.8
10
V
1, 2
VIL
ILI
µA
0V<VIN<VCC
Output(s) disabled
0V<VOUT<VCC
Output Leakage Current
-10
2.4
10
µA
ILO
Output High Voltage
Output Low Voltage
V
V
1
1
I
OH=-4.0mA
OL=8.0mA
VOH
VOL
0.4
I
MAX
PARAMETER
CONDITIONS
SYM
-15
-20
-25
-35
-45 UNITS NOTES
CE\ < VIL; VCC = MAX
f = MAX = 1/tRC (MIN)
Output Open
Power Supply
Current: Operating
165
150
45
140
120
120
25
mA
mA
3
I
cc
CE\ > VIH; All Other Inputs
Power Supply
Current: Standby
ISBT2
45
40
25
< VIL or > VIH, VCC = MAX
f = 0 Hz
CE\ > VCC -0.2V; VCC = MAX
VIL < VSS +0.2V
ISBC2
ISBC2
20
4
20
4
20
4
20
4
20
4
mA
mA
VIH > VCC -0.2V; f = 0 Hz
"L" Version Only
CAPACITANCE
DESCRIPTION
CONDITIONS
SYM
MAX
UNITS
NOTES
TA = 25oC, f = 1MHz
Input Capacitance
10
pF
pF
4
CI
VCC = 5V
Output Capacitance
12
4
CO
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
3
SRAM
MT5C2564
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC;VCC = 5V +10%)
-15
-20
-25
-35
-45
DESCRIPTION
READ CYCLE
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
SYMBOL
tRC
tAA
tACE
tOH
READ cycle time
15
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
15
15
20
20
25
25
35
35
45
45
Chip Enable access time
Output hold from address change
3
3
3
3
3
3
3
3
3
3
tLZCE
tHZCE
tPU
7
6, 7
4
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
WRITE CYCLE
8
10
20
10
25
20
35
20
45
0
0
0
0
0
tPD
15
4
tWC
tCW
tAW
WRITE cycle time
15
12
12
0
20
15
15
0
25
18
18
0
35
30
30
0
45
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to end of write
Address valid to end of write
Address setup time
tAS
tAH
Address hold from end of write
WRITE pulse width
2
2
2
5
5
tWP
12
7
15
10
0
17
12
0
30
20
0
40
20
0
tDS
Data setup time
tDH
Data hold time
0
tLZWE
tHZWE
Write disable to output in Low-Z
Write Enable to output in High-Z
0
0
0
0
0
7
0
7
0
10
0
11
0
20
0
20
6, 7
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
4
SRAM
MT5C2564
Austin Semiconductor, Inc.
ACTEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
167Ω
167Ω
Q
Q
VTH =1.73V
VTH =1.73V
5pF
30pF
Fig. 2 Output Load
Equivalent
Fig. 1 Output Load
Equivalent
allowing for actual tester RC time constant.
7. At any given temperature and voltage condition,
NOTES
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
tHZCE is less than tLZCE, and tHZWE is less than tLZWE and
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
t
HZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
9. Device is continuously selected. Chip enable is held in
its active state.
unloaded, and f =
1
Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6. tLZCE, tLZWE, tLZOE, tHZCE, tHZOE and tHZWE are
specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. tRC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM
MIN
MAX UNITS NOTES
VCC for Retention Data
2
---
V
VDR
CE\ > (VCC - 0.2V)
VCC = 2V ICCDR
1
mA
Data Retention Current
VIN > (VCC - 0.2V)
or < 0.2V
VCC = 3V
2
mA
Chip Deselect to Data
Retention Time
tCDR
tR
0
---
ns
ns
4
Operation Recovery Time
4, 11
tRC
LOWVcc DATA RETENTIONWAVEFORM
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tCDR
tR
VIH
VIL
VDR
CE\
DON’T CARE
UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
5
SRAM
MT5C2564
Austin Semiconductor, Inc.
READ CYCLE NO. 1 8, 9
t
RC
VALID
ADDRESS
Q
t
AA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 2 7, 8, 10
tR
C
CE\
tLZCE
t
tHZCE
E
ACE
DATA VALID
Q
Icc
tPU
tP
D
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
6
SRAM
MT5C2564
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
tWC
ADDRESS
tA
W
tAH
tAS
tCW
CE\
tW
P
WE\
tDH
t
DS
DATA VAILD
D
Q
HIGH Z
7, 12
WRITE CYCLE NO. 2
(Write Enabled Controlled)
tW
C
ADDRESS
tAW
tAW
tAH
tCW
CE\
tAS
t
WP
WE\
tDS
tDH
tDH
D
Q
DATA VALID
tHZWE
tLZWE
HIGH-Z
DON’T CARE
UNDEFINED
NOTE: Output enable (OE\) is inactive (HIGH).
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
7
SRAM
MT5C2564
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #106 (Package Designator C)
SMD #5962-88681, Case Outline L
D
A
Q
L
Pin 1
b
e
S1
b2
E
NOTE
c
0o to 15o
eA
SMD SPECIFICATIONS
SYMBOL
MIN
---
0.014
0.045
0.008
---
MAX
0.200
0.026
0.065
0.018
1.280
0.310
A
b
b2
c
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
Q
S1
0.125
0.015
0.005
0.200
0.060
---
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
8
SRAM
MT5C2564
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #204 (Package Designator EC)
SMD# 5962-88681, Case Outline X
D1
B2
D2
L2
e
E3
E
E1
E2
h x 45o
D
L
hx45o
B1
D3
A
A1
SMD SPECIFICATIONS
SYMBOL
MIN
MAX
0.120
0.088
0.028
A
A1
B1
B2
D
0.060
0.050
0.022
0.072 REF
0.342
0.358
D1
D2
D3
E
0.200 BSC
0.100 BSC
---
0.540
0.358
0.560
E1
E2
E3
e
0.400 BSC
0.200 BSC
---
0.558
0.050 BSC
0.040 REF
h
L
L2
0.045
0.075
0.055
0.095
NOTE: These dimensions are per the SMD. ASI's package dimensional limits
may differ, but they will be within the SMD limits.
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
9
SRAM
MT5C2564
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case (Package Designator F)
SMD 5962-88681 & 5962-88545, Case Outline Y
e
b
D
S
Top View
E
L
A
c
Q
E2
E3
SMD SPECIFICATIONS
MIN
MAX
SYMBOL
A
b
c
D
E
E2
E3
e
0.090
0.015
0.004
---
0.380
0.180
0.030
0.130
0.022
0.009
0.740
0.420
---
---
0.050 BSC
L
Q
S
0.250
0.026
0.000
0.370
0.045
---
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may
differ, but they will be within the SMD limits.
* All measurements are in inches.
MT5C2564
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.1 6/05
10
SRAM
MT5C2564
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: MT5C2564EC-45/XT
EXAMPLE: MT5C2564C-20L/IT
Device
Number
Package Speed
Device
Number
Package Speed
Options** Process
Options** Process
Type
ns
Type
ns
MT5C2564
C
-15
L
/*
MT5C2564
EC
-15
L
/*
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
C
C
C
C
C
C
-20
-25
-35
-40
-55
-70
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
EC
EC
EC
EC
EC
EC
-20
-25
-35
-40
-55
-70
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
EXAMPLE: MT5C2564F-35/883C
Device
Number
Package Speed
Options** Process
Type
ns
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
MT5C2564
F
-15
L
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
/*
F
F
F
F
F
F
-20
-25
-35
-40
-55
-70
*AVAILABLE PROCESSES
IT = IndustrialTemperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
11
SRAM
MT5C2564
Austin Semiconductor, Inc.
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator C
ASI Package Designator EC
ASI Part #
SMD Part #
5962-8868106LA
5962-8868105LA
5962-8868101LA
5962-8868102LA
5962-8868103LA
5962-8868104LA
ASI Part #
SMD Part #
MT5C2564C-20/883C
MT5C2564C-25/883C
MT5C2564C-35/883C
MT5C2564C-45/883C
MT5C2564C-55/883C
MT5C2564C-70/883C
MT5C2564EC-20/883C
MT5C2564EC-25/883C
MT5C2564EC-35/883C
MT5C2564EC-45/883C
MT5C2564EC-55/883C
MT5C2564EC-70/883C
5962-8868106XA
5962-8868105XA
5962-8868101XA
5962-8868102XA
5962-8868103XA
5962-8868104XA
MT5C2564C-35L/883C
MT5C2564C-45L/883C
MT5C2564C-55L/883C
MT5C2564C-70L/883C
5962-8854501LA
5962-8854502LA
5962-8854503LA
5962-8854504LA
MT5C2564EC-35L/883C
MT5C2564EC-45L/883C
MT5C2564EC-55L/883C
MT5C2564EC-70L/883C
5962-8854501XA
5962-8854502XA
5962-8854503XA
5962-8854504XA
ASI Package Designator F
ASI Part #
SMD Part #
MT5C2564F-20/883C
MT5C2564F-25/883C
MT5C2564F-35/883C
MT5C2564F-45/883C
MT5C2564F-55/883C
MT5C2564F-70/883C
5962-8868106YA
5962-8868105YA
5962-8868101YA
5962-8868102YA
5962-8868103YA
5962-8868104YA
MT5C2564F-35L/883C
MT5C2564F-45L/883C
MT5C2564F-55L/883C
MT5C2564F-70L/883C
5962-8854501YA
5962-8854502YA
5962-8854503YA
5962-8854504YA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C2564
Rev. 3.1 6/05
12
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