5962-8767902XA [AVAGO]
2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.4Mbps, GULL WING, HERMETIC, CERAMIC, DIP-8;
| 型号： | 5962-8767902XA |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.4Mbps, GULL WING, HERMETIC, CERAMIC, DIP-8 输出元件 光电 |
| 文件： | 总13页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hermetically Sealed, Transistor Output Optocouplers
for Analog and Digital Applications
4N55*, 5962-87679, HCPL-553X, HCPL-653X, HCPL-257K,
HCPL-655X, 5962-90854, HCPL-550X
*See matrix for available extensions.
Data Sheet
Description
Features
Theseunitsaresingle,dualandquadchannel,hermetically • Dual Marked with Device Part Number and DSCC
sealedoptocouplers.Theproductsarecapableofoperation
and storage over the full military temperature range and
can be purchased as either standard product or with full
MIL-PRF-38534 Class Level H or K testing or from the ap-
Drawing Number
• ManufacturedandTestedonaMIL-PRF-38534Certified
Line
propriateDSCCDrawing.Alldevicesaremanufacturedand
tested on a MIL-PRF-38534 certified line and are included
in the DSCC Qualified Manufacturers List QML-38534 for
Hybrid Microcircuits.
• QML-38534, Class H and K
• Five Hermetically Sealed Package Configurations
• Performance Guaranteed over Full Military
Temperature Range: -55°C to +125°C
Applications
• High Speed: Typically 400 kBit/s
• 9 MHz Bandwidth
• Military and Space
• Open Collector Output
• High Reliability Systems
• Vehicle Command, Control, Life Critical Systems
• Line Receivers
• 2-18 Volt V Range
CC
• 1500 Vdc Withstand Test Voltage
• High Radiation Immunity
• 6N135, 6N136, HCPL-2530/2531,
Function Compatibility
• Switching Power Supply
• Voltage Level Shifting
• Analog Signal Ground Isolation
(see Figures 7, 8, and 13)
• Reliability Data
• Isolated Input Line Receiver
• Isolated Output Line Driver
• Logic Ground Isolation
• Harsh Industrial Environments
• Isolation for Test Equipment Systems
The connection of a 0.1 µF bypass capacitor between V and GND is recommended.
CC
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
EachchannelcontainsaGaAsPlightemittingdiodewhich
is optically coupled to an integrated photon detector.
Separate connections for the photodiodes and output
transistor collectors improve the speed up to a hundred
times that of a conventional phototransistor optocoupler
by reducing the base-collector capacitance.
Truth Table
(Positive Logic)
Input
On (H)
Off (L)
Output
L
These devices are suitable for wide bandwidth analog
applications, as well as for interfacing TTL to LSTTL or
H
Functional Diagram
CMOS. Current Transfer Ratio (CTR) is 9% minimum at I
F
= 16 mA. The 18V V capability will enable the designer
CC
Multiple Channel Devices Available
to interface any TTL family to CMOS. The availability of
the base lead allows optimized gain/ bandwidth adjust-
ment in analog applications. The shallow depth of the
IC photodiode provides better radiation immunity than
conventional phototransistor couplers.
V
CC
V
V
B
O
These products are also available with the transistor base
node not connected to improve common mode noise
immunity and ESD susceptibility. In addition, higher CTR
minimums are available by special request.
GND
Packagestylesforthesepartsare8and16pinDIPthrough
hole (case outlines P and E respectively), 16 pin DIP flat
pack (case outline F), and leadless ceramic chip carrier
(case outline 2). Devices may be purchased with a variety
ofleadbendandplatingoptions,seeSelectionGuideTable
for details. Standard Microcircuit Drawing (SMD) parts are
available for each package and lead style.
Because the same functional die (emitters and detectors)
are used for each channel of each device listed in this
data sheet, absolute maximum ratings, recommended
operatingconditions,electricalspecifications,andperfor-
mance characteristics shown in the figures are identical
for all parts. Occasional exceptions exist due to package
variations and limitations and are as noted. Additionally,
the same package assembly processes and materials are
used in all devices. These similarities give justification for
the use of data obtained from one part to represent other
part’s performance for die related reliability and certain
limited radiation test results.
ꢀ
Selection Guide–Package Styles and Lead Configuration Options
16 Pin Flat
Pack
Package
16 Pin DIP
8 Pin DIP
8 Pin DIP
20 Pad LCCC
Lead Style
Through Hole
Through Hole
Through Hole
Unformed
Leads
Surface Mount
Channels
ꢀ
1
ꢀ
4
ꢀ
Common Channel Wiring
Avago Part No. and Options
Commercial
None
None
V
GND
V
GND
None
CC
CC
(1)
4N55
HCPL-5500
HCPL-5501
HCPL-550K
Gold Plate
Option ꢀ00
Option 100
Option ꢁ00
HCPL-55ꢁ0
HCPL-55ꢁ1
HCPL-55ꢁK
Gold Plate
Option ꢀ00
Option 100
Option ꢁ00
HCPL-6550
HCPL-6551
HCPL-655K
Gold Plate
HCPL-65ꢁ0
HCPL-65ꢁ1
HCPL-65ꢁK
Solder Pads *
MIL-PRF-ꢁ85ꢁ4 Class H
MIL-PRF-ꢁ85ꢁ4 Class K
Standard Lead Finish
Solder Dipped *
4N55/88ꢁB
HCPL-ꢀ57K
Gold Plate
Option ꢀ00
Option 100
Option ꢁ00
Butt Joint/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
Either Gold or Soldered
Gold Plate
596ꢀ-
596ꢀ-
596ꢀ-
596ꢀ-
596ꢀ-
8767901EX
8767901EC
8767901EA
8767901UC
8767901UA
8767901TA
9085401HPX
9085401HPC
9085401HPA
9085401HYC
9085401HYA
9085401HXA
876790ꢀPX
876790ꢀPC
876790ꢀPA
876790ꢀYC
876790ꢀYA
876790ꢀXA
8767904FX
8767904FC
876790ꢁꢀX
Solder Dipped*
876790ꢁꢀA
Butt Joint/Gold Plate
Butt Joint/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Either Gold or Soldered
Gold Plate
596ꢀ-
596ꢀ-
596ꢀ-
596ꢀ-
596ꢀ-
8767905KEX
8767905KEC
8767905KEA
8767905KUC
8767905KUA
8767905KTA
9085401KPX
9085401KPC
9085401KPA
9085401KYC
9085401KYA
9085401KXA
8767906KPX
8767906KPC
8767906KPA
8767906KYC
8767906KYA
8767906KXA
8767908KFX
8767908KFC
8767907KꢀX
Solder Dipped *
8767907KꢀA
Butt Joint/Gold Plate
Butt Joint/Soldered*
Gull Wing/Soldered*
1. JEDEC registered part.
* Solder contains lead
ꢁ
8 Pin Ceramic DIP Single Channel Schematic
I
I
I
CC
8
7
6
I
F
2
V
V
V
CC
B
ANODE
+
B
V
F
O
-
O
CATHODE
3
5
GND
Note, base is pin 7.
Functional Diagrams
16 Pin DIP
Through Hole
ꢀ Channels
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
ꢀ Channels
16 Pin Flat Pack
Unformed Leads
4 Channels
ꢀ0 Pad LCCC
Surface Mount
ꢀ Channels
15 14
1
V
16
1
16
B1
V
V
CCꢀ
Bꢀ
Oꢀ
1
V
8
1
V
V
8
CC
V
CC
O1
19
ꢀ0
1ꢁ
1ꢀ
ꢀ
ꢁ
4
V
15
14
1ꢁ
ꢀ
ꢁ
4
V
V
V
V
V
15
14
1ꢁ
V
CC1
CC
O1
Oꢀ
Oꢁ
O4
ꢀ
ꢁ
4
7
6
5
ꢀ
ꢁ
4
7
6
5
B
GND
ꢀ
V
O1
V
V
OUT
Oꢀ
V
CC1
ꢀ
ꢁ
10
9
V
7
O1
GND
V
B1
GND
1
GND
GND
5
1ꢀ
5
1ꢀ
V
Bꢀ
8
V
6
7
8
11
10
9
6
7
8
11
10
9
CCꢀ
GND
GND
V
Oꢀ
Note: 8 pin DIP and flat pack devices have common V and ground. 16 pin DIP and LCCC (leadless ceramic chip carrier) packages have isolated
CC
channels with separate V and ground connections.
CC
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Leaded Device Marking
Leadless Device Marking
Avago DESIGNATOR
Avago P/N
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
A QYYWWZ
XXXXXX
XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
Avago CAGE CODE*
Avago DESIGNATOR
Avago P/N
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
Avago CAGE CODE*
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Outline Drawings
16 Pin Flat Pack, 4 Channels
7.24 (0.285)
6.99 (0.275)
2.29 (0.090)
MAX.
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.88 (0.0345)
0.31 (0.012)
0.23 (0.009)
MIN.
0.89 (0.035)
0.69 (0.027)
5.23
(0.206)
MAX.
9.02 (0.355)
8.76 (0.345)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
20 Terminal LCCC Surface Mount, 2 Channels
8 Pin DIP Through Hole, 1 and 2 Channel
8.70 (0.342)
9.10 (0.358)
9.40 (0.370)
9.91 (0.390)
0.76 (0.030)
1.27 (0.050)
8.13 (0.320)
MAX.
4.95 (0.195)
5.21 (0.205)
7.16 (0.282)
7.57 (0.298)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
4.32 (0.170)
MAX.
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
0.51 (0.020)
MIN.
3.81 (0.150)
0.20 (0.008)
0.33 (0.013)
MIN.
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
1.52 (0.060)
2.03 (0.080)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
5
Hermetic Optocoupler Options
Option
Description
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This op-
tion is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for
details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
1.40 (0.055)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
100
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Lead finish is solder dipped rather than gold plated. This option is available on commercial and
hi-rel product in 8 and 16 pin DIP. DSCC drawing part numbers contain provisions for lead finish.
All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature.
200
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This
option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for
details). This option has solder dipped leads.
4.57 (0.180)
MAX.
0.51 (0.020)
1.40 (0.055)
1.65 (0.065)
MIN.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
300
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5˚ MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: Solder contains lead.
6
Absolute Maximum Ratings
No derating required up to +125° C.
Symbol
Min.
-65°
Max.
+150°
Units
Parameter
Storage Temperature Range
TS
TA
TJ
C
C
Operating Ambient Temperature
Junction Temperature
-55°
+125°
+175°
C
Case Temperature
TC
+170°
C
Lead Solder Temperature (1.6 mm below seating plane)
Average Input Forward Current
260° for 10 s
20
C
IF AVG
IFPK
mA
Peak Forward Input Current
(each channel, ≤ 1 ms duration)
40
mA
Reverse Input Voltage
BVR
IO
See Electrical Characteristics
Average Output Current, each channel
Peak Output Current, each channel
Supply Voltage
8
16
20
20
36
50
200
mA
IO
mA
V
VCC
VO
-0.5
-0.5
Output Voltage
V
Input Power Dissipation, each channel
Output Power Dissipation, each channel
Package Power Dissipation, each channel
mW
mW
mW
PD
Single Channel 8 Pin, Dual Channel 16 Pin, and LCCC Only
Symbol
VEBO
IB
Min.
Max.
Units
V
Parameter
Emitter Base Reverse Voltage
3
5
Base Current, each channel
mA
ESD Classification
(MIL-STD-883, Method 3015)
4N55, 4N55/883B, HCPL-257K, HCPL-5500/01/0K, and HCPL-6530/31/3K
HCPL-5530/31/3K, HCPL-6550/51/5K
( ), Class 1
D
(Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
µA
Input Current, Low Level
Input Current, High Level
Supply Voltage, Output
IFL
IFH
250
20
12
2
mA
V
VCC
18
7
Electrical Characteristics
T = -55° C to +1ꢀ5° C, unless otherwise specified. See Note 1ꢀ.
A
Group A,
Sub-
Symbol group
Limits
Parameter
Test Conditions
Min. Typ.* Max. Units Fig.
Notes
Current Transfer Ratio
CTR
1, 2, 3
1, 2, 3
VO = 0.4V, IF = 16 mA,
VCC = 4.5V
9
20
%
2, 3
1, 2, 10
Logic High Output
Current
IOH
IF = 0,
IF (other channels) =
20 mA
5
100 mA
4
1
VO = VCC = 18 V
Output Leakage Current IOLeak
1, 2, 3
IF = 250 mA,
IF (other channels) =
20 mA,
30
250 mA
4
1
1
VO = VCC = 18 V
Input-Output Insulation II-O
Leakage Current
1
VI-O = 1500 Vdc,
RH ≤ 65%,
TA = 25°C, t = 5 s
1.0
mA
3, 9
Input Forward Voltage
VF
1, 2, 3
IF = 20 mA
1.55
1.8
1.9
V
1, 14
1, 13
Reverse Breakdown
Voltage
BVR
ICCH
1, 2, 3
1, 2, 3
IR = 10 mA
5
3
V
1, 14
1, 13
1
Logic High
Supply
Single
Channel
VCC = 18 V, IF = 0 mA
0.1
0.2
0.4
35
10
20
40
mA
Current
Dual
VCC = 18 V, IF = 0 mA
(all channels)
1,4
1
Channel
Quad
Channel
VCC = 18 V, IF = 0 mA
(all channels)
Logic Low
Supply
Single
Channel
ICCL
1, 2, 3
VCC = 18 V, IF = 20 mA
200 mA
400
1
Current
Dual
VCC = 18 V, IF1 = IF2
20 mA
=
=
70
1, 4
1
Channel
Quad
Channel
VCC = 18 V, IF1 = IF2
IF3 = IF4 = 20 mA
140
800
Propagation Delay
Time to Logic High at
Output
tPLH
9, 10, 11
RL = 8.2 kW,
CL = 50 pF,
IF = 16 mA,
VCC = 5 V
1.0
0.4
6.0
2.0
ms
6, 9
1, 6
Propagation Delay
Time to Logic Low at
Output
tPHL
*All typical values are at V = 5 V, T = ꢀ5°C.
CC
A
8
Typical Characteristics
All typical values are at T = 25°C, V = 5 V, unless otherwise specified.
A
CC
Parameter
Symbol
Test Conditions
VF = 0 V, f = 1 MHz
IF = 20 mA
Typ.
60
Units
pF
Fig.
Notes
Input Capacitance
CIN
1
1
Input Diode Temperature
Coefficient
DVF/DTA
-1.5
mV/°C
W
Resistance (Input-Output)
RI-O
VI-O = 500 V
1012
1.0
3
Capacitance (Input-Output)
Transistor DC Current Gain
Small Signal Current Transfer Ratio
CI-O
f = 1 MHz
pF
-
1, 11
1
hFE
VO = 5 V, IO = 3 mA
VCC = 5 V, VO = 2 V
250
21
DIO/DIF
|CMH|
%
7
1
Common Mode Transient Immu-
nity at Logic High Level Output
IF = 0 mA, RL = 8.2 kW,
VO (min) = 2.0 V,
VCM = 10 VP-P
1000
V/ms
10
1, 7
Common Mode Transient Immu-
nity at Logic Low Level Output
|CML|
BW
IF = 16 mA, RL = 8.2 kW,
VO (max) = 0.8 V,
VCM = 10 VP-P
-1000
9
V/ms
10
8
1, 7
8
Bandwidth
MHz
Multi-Channel Product Only
Parameter
Symbol
Test Conditions
Typ.
Units
Notes
Input-Input Insulation Leakage
Current
II-I
RH ≤ 65%, VI-I = 500 V, t = 5 s
1
pA
5, 9
1012
0.8
5
5
W
Resistance (Input-Input)
Capacitance (Input-Input)
RI-I
CI-I
VI-I = 500 V
f=1 MHz
pF
Notes:
1. Each channel of a multi-channel device.
2. Current Transfer Ratio is defined as the ratio of output collector current, I , to the forward LED input current, I , times 100%. CTR is known to
O
F
degrade slightly over the unit’s lifetime as a function of input current, temperature, signal duty cycle, and system on time. Refer to Application
Note 1002 for more detail. ln short, it is recommended that designers allow at least 20-25% guardband for CTR degradation.
3. Alldevicesareconsideredtwo-terminaldevices;measuredbetweenallinputleadsorterminalsshortedtogetherandalloutputleadsorterminals
shorted together.
4. The 4N55, 4N55/883B, HCPL-257K, HCPL-6530, HCPL-6531, and HCPL-653K dual channel parts function as two independent single channel units.
Use the single channel parameter limits. I = 0 mA for channel under test and I = 20 mA for other channels.
F
F
5. Measured between adjacent input pairs shorted together for each multichannel device.
6. propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the
t
PHL
output pulse. The t
propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trail-
PLH
ing edge of the output pulse.
7. CM is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (V < 0.8 V).
L
O
CM is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (V > 2.0
H
O
V).
8. Bandwidth is the frequency at which the ac output voltage is 3 dB below the low frequency asymptote. For the HCPL-5530 the typical bandwidth
is 2 MHz.
9. This is a momentary withstand test, not an operating condition.
10. Higher CTR minimums are available to support special applications.
11. Measured between each input pair shorted together and all output connections for that channel shorted together.
12. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C (Subgroups 1
and 9, 2 and 10, 3 and 11, respectively).
13. Not required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types.
14. Required for 4N55, 4N55/883B, HCPL-257K, 5962-8767901, and 5962-8767905 types only.
9
Figure 1. Input Diode Forward Current vs. For-
ward Voltage.
Figure 2. DC and Pulsed Transfer Character-
istic.
Figure 3. Normalized Current Transfer Ratio vs.
Input Diode Forward Current.
100
I
I
= 250 µA,
(OTHER CHANNELS) = 20 mA
F
F
I
I
= 0 µA,
10
1
F
F
(OTHER CHANNELS) = 20 mA
I
= I (OTHER CHANNELS)
F
= 0 mA
F
0.1
V
= V = 18 V
O
CC
0.01
0.001
-60 -40 -20
0
20 40 60 80 100 120 140
TA - TEMPERATURE - ˚C
Figure 4. Logic High Output Current vs. Tem-
perature.
Figure 6. Propagation Delay vs. Temperature.
Figure 5. Logic Low Supply Current vs. Input
Diode Forward Current.
Figure 7. Normalized Small Signal Current
Transfer Ratio vs. Quiescent Input Current.
+12 V
D.U.T.
+12 V
1.2 k Ω
9.1 k Ω
V
CC
0.01 µF
0.01 µF
2.1 k Ω
100 Ω
Q
3
0.1 µF
0.1 µF
V
V
O
B
47 µF
Q
V
O
2
Q
1
(1 MΩ, 12 pF
V
IN
TEST INPUT)
15 k Ω
470
Ω
100 Ω
R
F
51 Ω
1 k Ω
GND
SINGLE CHANNEL TESTING,
INDEPENDENT V DEVICES
22 Ω
CC
1N4150
TRIM FOR UNITY GAIN
, Q , Q : 2N3904
Q
TYPICAL LINEARITY = +3 % AT V = 1 V
IN P-P
TYPICAL SNR = 50 dB
1
2
3
TYPICAL R = 375 Ω
F
TYPICAL V dc = 3.8 V
O
TYPICAL I = 9 mA
F
D.U.T.
+5 V
+15
+10
+15 V
T
= 25 ˚C
V
A
CC
100 Ω
SET I
20 k Ω
F
V
O
INDEPENDENT
DEVICES
+5
0
2N3053
1.6 Vdc
0.25 V
AC INPUT
V
CC
0.1 µF
ac
P-P
560 Ω
100 Ω
GND
COMMON
-5
COMMON V
DEVICES
CC
-10
V
DEVICES
CC
-15
-20
0.1
1.0
10
100
f - FREQUENCY - MHz
Figure 8. Frequency Response.
PULSE GEN.
Z
t
= 50 Ω
= 5 ns
O
r
D.U.T.
I
+5 V
F
V
CC
R
L
V
O
I
MONITOR
F
100 Ω
C
* = 50 pF
L
GND
SINGLE CHANNEL
OR COMMON V DEVICES
CC
10 % DUTY CYCLE
1/f < 100 µs
NOTES:
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
L
BASE LEAD NOT CONNECTED.
Figure 9. Switching Test Circuit.*
*JEDEC Registered Data.
11
IF
B
A
D.U.T.
+5 V
VCC
R
L
RM
V
O
V
FF
GND
SINGLE CHANNEL OR
COMMON VCC DEVICES
V
CM
+
-
PULSE GEN.
NOTE: BASE LEAD NOT CONNECTED.
Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.
V
5 V
CC
Logic Family
LSTTL
54LS14
5 V
CMOS
220 Ω
R
L
D.U.T.
Device No.
CD40106BM
V
CC
V
CC
5 V
8.ꢀ kW
15 V
TTL
R 5% Tolerance
L
18 kW *
ꢀꢀ kW
LOGIC GATE
0.01 µF
GND
EACH CHANNEL
*The equivalent output load resistance is affected by the LSTTL input
current and is approximately 8.2 kΩ. This is a worst case design
which takes into account 25% degradation of CTR. See App. Note
1002 to assess actual degradation and lifetime.
Figure 11. Recommended Logic Interface.
VCC
VOC
D.U.T.*
VCC
(EACH INPUT)
0.1 µF
+
-
VO
VIN
(EACH OUTPUT)
GND
NOMINAL CONDITIONS
PER CHANNEL: IF = 20 mA
IO = 4 mA
ICC = 30 µA
NOTE: BASE LEAD NOT CONNECTED.
T
= +125 ˚C
A
Figure 12. Operating Circuit for Burn-In and Steady State Life Tests. All
Channels Tested Simultaneously.
1ꢀ
OFFSET ADJUST
R
3
2
1
2
HCPL-5530
5 k Ω
I
F
-
1
220
-
U
+
Ω
U
8
7
6
5
1
2
3
4
1
+
+
I
I
C
C
3
V
I
F
IN
2
2
R
1 kΩ
4
-
U
5 k Ω GAIN ADJUST
2
-
+
50 k Ω
R
5
-15 V
-
U
+
R
R
2
2.7 k Ω
1
V
OUT
4
2.7 k Ω
U
I
, U , U , U , LM307
1
2
3
4
2
n
1
I
I
F
F
1
I
= K
C
1
2
6 mA
CC
1
1
´
n
2
I
I
F
F
´
2
I
= K
-15 V
C
2
2
Figure 13. Isolation Amplifier Application Circuit.
Description
MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Program
The schematic uses a dualchannel, high-speed optocou-
pler (HCPL-5530) to function as a servo type dc isolation
amplifier. This circuit operates on the principle that two
optocouplerswilltrackeachotheriftheirgainchangesby
the same amount over a specific operating region.
Avago Technologies’s Hi-Rel Optocouplers are in compli-
ance with MIL-PRF-38534 Classes H and K. Class H and
Class K devices are also in compliance with DSCC draw-
ings 5962-87679, and 5962-90854. Testing consists of
100% screening and quality conformance inspection to
MIL-PRF-38534.
Performance of Circuit
• 1% linearity for 10 V peak-to-peak dynamic range
• Gain drift: -0.03%/°C
• Offset Drift: 1 mV/°C
• 25 kHz bandwidth (limited by Op-Amps U1, U2)
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved.
5989-1659EN - June 13, 2007
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