首页 |元器件品牌

AFBR-5103ATZ [AVAGO]

FIBER OPTIC TRANSCEIVER, 1270-1380nm, 125Mbps(Tx), 125Mbps(Rx), BOARD/PANEL MOUNT, SIP, ST CONNECTOR, ROHS COMPLIANT, SIP-9;
AFBR-5103ATZ
型号： AFBR-5103ATZ
厂家： AVAGO TECHNOLOGIES LIMITED    AVAGO TECHNOLOGIES LIMITED
描述：

FIBER OPTIC TRANSCEIVER, 1270-1380nm, 125Mbps(Tx), 125Mbps(Rx), BOARD/PANEL MOUNT, SIP, ST CONNECTOR, ROHS COMPLIANT, SIP-9

光纤
文件： 总20页 (文件大小：242K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
AFBR-5103Z/-5103TZ 1300 nm 2000 m AFBR-5103AZ/-  
5103ATZ/-5103PZ/-5103PEZ  
FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers in  
Low Cost 1x9 Package Style  
Data Sheet  
Description  
Features  
The AFBR-5100Z family of trans­eivers from Avago Te­h-  
nologies provide the system designer with produ­ts to  
implementarangeofFDDIandATM(Asyn­hronousTrans-  
fer Mode) designs at the 100 Mbps/125 MBd rate.  
•
FullComplian­ewiththeOpti­alPerforman­eRequire-  
ments of the FDDI PMD Standard  
•
•
Full Complian­e with the FDDI LCF-PMD Standard  
FullComplian­ewiththeOpti­alPerforman­eRequire-  
ments of the ATM 100 Mbps Physi­al Layer  
The trans­eivers are all supplied in the new industry  
standard 1x9 SIP pa­kage style with either a duplex SC or  
a duplex ST* ­onne­tor interfa­e.  
•
•
FullComplian­ewiththeOpti­alPerforman­eRequire-  
ments of 100 Base-FX Version of IEEE802.3u  
FDDI PMD, ATM and Fast Ethernet 2000 m Ba­kbone  
Links  
Multisour­ed 1x9 Pa­kage Style with Choi­e of Duplex  
SC or Duplex ST* Re­epta­le  
The AFBR-5103Z/-5103TZare 1300 nm produ­ts with  
opti­al performan­e ­ompliant with the FDDI PMD  
standard. The FDDI PMD standard is ISO/IEC 9314-3:  
1990 and ANSI X3.166 - 1990.  
•
•
Wave Solder and Aqueous Wash Pro­ess Compatible  
RoHS Complian­e  
Applications  
These trans­eivers for 2000 meter multimode fiber ba­k-  
bones are supplied in the small 1x9 duplex SC or ST pa­k-  
age style for those designers who want to avoid the larger  
MIC/R (Media Interfa­e Conne­tor/Re­epta­le) defined in  
the FDDI PMD standard.  
•
•
•
Multimode Fiber Ba­kbone Links  
Multimode Fiber Wiring Closet to Desktop Links  
Multimode Fiber Media Converter  
Note: The “T” in the produ­t numbers indi­ates a trans­eiver with a  
duplex ST ­onne­tor re­epta­le. Produ­t numbers without a “T” indi­ate  
AvagoTe­hnologiesalsoprovidesseveralotherFDDIprod-  
u­ts­ompliantwiththePMDandSM-PMDstandards.These  
produ­ts are available with MIC/R, ST and FC ­onne­tor  
trans­eivers with a duplex SC ­onne­tor re­epta­le.  
©
styles. They are available in the 1x13 and 2x11 trans­eiver  
and 16 pin transmitter/re­eiver pa­kage styles for those  
designs that require these alternate ­onfigurations.  
The AFBR-5103Z/-5103TZ is also useful for both ATM 100  
Mbps interfa­es and Fast Ethernet 100 Base-FX interfa­es.  
TheATMForumUser-NetworkInterfa­e(UNI)Standard,Ver-  
sion3.0,definesthePhysi­alLayerfor100MbpsMultimode  
Fiber Interfa­e for ATM in Se­tion 2.3 to be the FDDI PMD  
Standard. Likewise, the Fast Ethernet Allian­e defines the  
Physi­al Layer for 100 Base-FX for Fast Ethernet to be the  
FDDI PMD Standard.  
*ST is a registered trademark of AT&T Lightguide Cable Conne­tors.  
ATM appli­ations for physi­al layers other than 100 Mbps  
Multimode Fiber Interfa­e are supported by Avago Te­h-  
nologies. Produ­ts are available for both the single mode  
and the multimode fiber SONET-OC-3C (STS-3C) ATM  
interfa­e and the 155 Mbps ATM 94 MBd multimode fiber  
ATM interfa­e as spe­ified in the ATM Forum UNI.  
Figure 2b shows the outline drawing for options that  
in­lude mezzanine height with extended shield.  
The pa­kage outline drawing and pin out are shown in  
Figures 2, 2a and 3. The details of this pa­kage outline  
and pin out are ­ompliant with the multisour­e definition  
of the 1x9 SIP. The low profile of the Avago Te­hnologies  
trans­eiver design ­omplies with the maximum height al-  
lowed for the duplex SC ­onne­tor over the entire length  
of the pa­kage.  
Transmitter Sections  
The transmitter se­tions of the AFBR-5103Z series utilize  
1300 nm Surfa­e Emitting InGaAsP LEDs. These LEDs  
are pa­kaged in the opti­al subassembly portion of the  
transmitter se­tion. They are driven by a ­ustom sili­on  
IC whi­h ­onverts differential PECL logi­ signals, ECL ref-  
eren­ed (shifted) to a +5 Volt supply, into an analog LED  
drive ­urrent.  
The opti­alsubassemblies utilize a high volume assembly  
pro­esstogetherwithlow­ostlenselementswhi­hresult  
in a ­ost effe­tive building blo­k.  
The ele­tri­al subassembly ­onsists of a high volume  
multilayer printed ­ir­uit board on whi­h the IC ­hips  
and various surfa­e-mounted passive ­ir­uit elements  
are atta­hed.  
Receiver Sections  
The re­eiver se­tions of the AFBR-5103Z series utilize  
InGaAs PIN photodiodes ­oupled to a ­ustom sili­on  
transimpedan­e preamplifier IC. These are pa­kaged in  
the opti­al subassembly portion of the re­eiver.  
The pa­kage in­ludes internal shields for the ele­tri­al  
and opti­al subassemblies to ensure low EMI emissions  
and high immunity to external EMI fields.  
The outer housing in­luding the duplex SC ­onne­tor  
re­epta­le or the duplex ST ports is molded of filled  
non-­ondu­tive plasti­ to provide me­hani­al strength  
and ele­tri­al isolation. The solder posts of the Avago  
Te­hnologies’ design are isolated from the ­ir­uit design  
of the trans­eiver and do not require ­onne­tion to a  
ground plane on the ­ir­uit board.  
These PIN/preamplifier ­ombinations are ­oupled to a  
­ustom quantizer IC whi­h provides the final pulse shap-  
ing for the logi­ output and the Signal Dete­t fun­tion.  
The data output is differential. The signal dete­t output  
is single-ended. Both data and signal dete­t outputs are  
PECL ­ompatible, ECL referen­ed (shifted) to a +5 Volt  
power supply.  
The trans­eiver is atta­hed to a printed ­ir­uit board with  
the nine signal pins and the two solder posts whi­h exit  
the bottom of the housing. The two solder posts provide  
the primary me­hani­al strength to withstand the loads  
imposed on the trans­eiver by mating with duplex or  
simplex SC or ST ­onne­tored fiber ­ables.  
Package  
The overall pa­kage ­on­ept for the Avago Te­hnologies  
trans­eivers ­onsists of the following basi­ elements; two  
opti­al subassemblies, an ele­tri­al subassembly and the  
housing as illustrated in Figure1 and Figure 1a.  
ELECTRICAL SUBASSEMBLY  
DUPLEX SC  
RECEPTACLE  
DIFFERENTIAL  
DATA OUT  
PIN PHOTODIODE  
SINGLE-ENDED  
SIGNAL  
DETECT OUT  
QUANTIZER IC  
PREAMP IC  
OPTICAL  
SUBASSEMBLIES  
DIFFERENTIAL  
DATA IN  
LED  
DRIVER IC  
TOP VIEW  
Figure 1. SC Block Diagram  
ꢀ
ELECTRICAL SUBASSEMBLY  
DUPLEX ST  
RECEPTACLE  
DIFFERENTIAL  
DATA OUT  
PIN PHOTODIODE  
SINGLE-ENDED  
SIGNAL  
DETECT OUT  
QUANTIZER IC  
PREAMP IC  
OPTICAL  
SUBASSEMBLIES  
DIFFERENTIAL  
DATA IN  
LED  
DRIVER IC  
TOP VIEW  
Figure 1a. ST Block Diagram.  
39.12  
(1.540)  
12.70  
(0.500)  
6.35  
(0.250)  
MAX.  
AREA  
RESERVED  
FOR  
PROCESS  
PLUG  
25.40  
(1.000)  
12.70  
(0.500)  
MAX.  
AFBR-5XXXZ  
DATE CODE (YYWW)  
SINGAPORE  
A
5.93 0.1  
(0.233 0.004)  
+ 0.0ꢀ  
0.75  
- 0.05  
3.30 0.3ꢀ  
+ 0.003  
- 0.002  
10.35  
(0.407)  
)
(0.030  
(0.130 0.015)  
MAX.  
2.92  
(0.115)  
1ꢀ.52  
(0.729)  
+ 0.25  
- 0.05  
1.27  
0.46  
(0.01ꢀ)  
NOTE 1  
+ 0.010  
- 0.002  
4.14  
(0.163)  
)
∅�  
(9x)  
(0.050  
NOTE 1  
23.55  
(0.927)  
20.32  
(0.ꢀ00)  
16.70  
(0.657)  
17.32  
20.32  
23.32  
[ꢀx(2.54/.100)]  
(0.6ꢀ2) (0.ꢀ00) (0.91ꢀ)  
0.ꢀ7  
(0.034)  
23.24  
(0.915)  
15.ꢀꢀ  
(0.625)  
Figure 2. Package Outline Drawing with Standard Height.  
ꢁ
42  
(1.654)  
MAX.  
5.99  
(0.236)  
24.ꢀ  
(0.976)  
12.7  
(0.500)  
25.4  
(1.000)  
MAX.  
AFBR-5103TZ  
DATE CODE (YYWW)  
SINGAPORE  
+ 0.0ꢀ  
- 0.05  
+ 0.003  
0.5  
(0.020)  
(
(
- 0.002  
12.0  
(0.471)  
MAX.  
2.6 0.4  
(0.102 0.016)  
0.46  
3.3 0.3ꢀ  
(0.130) ( 0.015)  
0.3ꢀ  
0.015)  
20.32  
(
∅�  
(0.01ꢀ)  
NOTE 1  
2.6  
∅�  
+ 0.25  
- 0.05  
1.27  
(0.102)  
+ 0.010  
- 0.002  
0.050  
(
(
20.32  
(0.ꢀ00)  
17.4  
(0.6ꢀ5)  
[(ꢀx (2.54/0.100)]  
20.32  
(0.ꢀ00)  
22.ꢀ6  
21.4  
(0.900)  
(0.ꢀ43)  
3.6  
(0.142)  
1.3  
(0.051)  
23.3ꢀ  
(0.921)  
1ꢀ.62  
(0.733)  
NOTE 1: PHOSPHOR BRONZE IS THE BASE MATERIAL FOR THE POSTS AND PINS. FOR LEAD-FREE SOLDERING,  
THE SOLDER POSTS HAVE TIN COPPER OVER NICKEL PLATING AND THE ELECTRICAL PINS HAVE PURE TIN  
OVER NICKEL PLATING.  
DIMENSIONS IN MILLIMETERS (INCHES).  
Figure 2a. ST Package Outline Drawing with Standard Height.  
ꢂ
29.6  
(1.16)  
UNCOMPRESSED  
39.6  
(1.56)  
12.70  
(0.50)  
4.7  
(0.1ꢀ5)  
MAX.  
AREA  
RESERVED  
FOR  
PROCESS  
PLUG  
25.4  
(1.00)  
12.7  
(0.50)  
MAX.  
2.0 0.1  
(0.079 0.004)  
0.51  
(0.02)  
SLOT WIDTH  
SLOT DEPTH  
+0.1  
-0.05  
+0.004  
-0.002  
0.25  
2.09  
UNCOMPRESSED  
10.2  
(0.40)  
9.ꢀ  
(0.3ꢀ6)  
MAX.  
MAX.  
(0.0ꢀ)  
(
0.010  
)
1.3  
(0.05)  
3.3 0.3ꢀ  
(0.130 0.015)  
20.32  
(0.ꢀ0)  
15.ꢀ 0.15  
(0.622 0.006)  
+0.25  
-0.05  
0.46  
+0.25  
1.27  
9X ∅�  
+0.010  
-0.002  
-0.05  
2X ∅�  
(
0.01ꢀ  
)
+0.010  
(
0.050  
)
-0.002  
2.54  
(0.100)  
ꢀX  
20.32  
(0.ꢀ00)  
23.ꢀ  
(0.937)  
20.32  
(0.ꢀ00)  
1.3  
(0.051)  
2X ∅�  
DIMENSIONS ARE IN MILLIMETERS (INCHES).  
ALL DIMENSIONS ARE 0.025 ꢁꢁ UNLESS OTHERWISE SPECIFIED.  
Figure 2b. Package Outline Drawing – Mezzanine Height with Extended Shield.  
1 = V  
EE  
N/C  
2 = RD  
Rx  
Tx  
3 = RD  
4 = SD  
5 = V  
CC  
6 = V  
CC  
7 = TD  
ꢀ = TD  
9 = V  
N/C  
EE  
TOP VIEW  
Figure 3. Pin Out Diagram.  
ꢃ
Application Information  
14  
12  
10  
ꢀ
The Appli­ations Engineering group in the Avago Te­h-  
nologies Opti­al Communi­ation Division is available to  
assist you with the te­hni­al understanding and design  
trade-offs asso­iated with these trans­eivers. You ­an  
­onta­t them through your Avago Te­hnologies sales  
representative.  
AFBR-5103Z, 62.5/125 µꢁ  
6
The following information is provided to answer some  
of the most ­ommon questions about the use of these  
parts.  
AFBR-5103Z,  
50/125 µꢁ  
4
Transceiver Optical Power Budget versus Link  
Length  
2
0
0.15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0  
Opti­al Power Budget (OPB) is the available opti­al power  
forafiberopti­linktoa­­ommodatefiber­ablelossesplus  
losses due to in-line ­onne­tors, spli­es, opti­al swit­hes,  
andtoprovidemarginforlinkagingandunplannedlosses  
due to ­able plant re­onfiguration or repair.  
FIBER OPTIC CABLE LENGTH (kꢁ)  
Figure 4. Optical Power Budget at BOL versus Fiber  
Optic Cable Length.  
Figure 4 illustrates the predi­ted OPB asso­iated with the  
trans­eiver series spe­ified in this data sheet at the Begin-  
ning of Life (BOL).These ­urves represent the attenuation  
and ­hromati­ plus modal dispersion losses asso­iated  
with the 62.5/125 µm and 50/125 µm fiber ­ables only.  
The area under the ­urves represents the remaining OPB  
at any link length, whi­h is available for over­oming non-  
fiber ­able related losses.  
Transceiver Signaling Operating Rate Range and BER  
Performance  
For purposes of definition, the symbol (Baud) rate, also  
­alledsignalingrate,isthere­ipro­aloftheshortestsymbol  
time. Data rate (bits/se­) is the symbol rate divided by the  
en­oding fa­tor used to en­ode the data (symbols/bit).  
When used in FDDI and ATM 100 Mbps appli­ations the  
performan­e of the 1300 nm trans­eivers is guaranteed  
overthesignalingrateof10MBdto125MBdtothefull­on-  
ditions listed in individual produ­t spe­ifi­ation tables.  
Avago te­hnologies’LED te­hnology has produ­ed 1300  
nmLEDdevi­eswithloweraging­hara­teristi­sthannor-  
mally asso­iated with these te­hnologies in the industry.  
The industry ­onvention is 1.5 dB aging for 1300 nm LEDs.  
TheAvagoTe­hnologies1300nmLEDswillexperien­eless  
than 1dB of aging over normal ­ommer­ial equipment  
mission life periods. Conta­t your Avago Te­hnologies  
sales representative for additional details.  
The trans­eivers may be used for other appli­ations at  
signaling rates outside of the 10 MBd to 125 MBd range  
with some penalty in the link opti­al power budget pri-  
marily ­aused by a redu­tion of re­eiver sensitivity. Figure  
5 gives an indi­ation of the typi­al performan­e of these  
1300 nm produ­ts at different rates.  
Figure 4 was generated with an Avago Te­hnologies’  
fiber opti­ link model ­ontaining the ­urrent industry  
­onventions for fiber ­able spe­ifi­ations and the FDDI  
PMD and LCF-PMD opti­al parameters. These parameters  
are refle­ted in the guaranteed performan­e of the trans-  
­eiver spe­ifi­ations in this data sheet. This same model  
has been used extensively in the ANSI and IEEE ­ommit-  
tees, in­luding the ANSI X3T9.5 ­ommittee, to establish  
the opti­al performan­e requirements for various fiber  
opti­ interfa­e standards. The ­able parameters used  
­ome from the ISO/IEC JTC1/SC 25/WG3 Generi­ Cabling  
for Customer Premises per DIS 11801 do­ument and the  
EIA/TIA-568-A Commer­ial Building Tele­ommuni­ations  
Cabling Standard per SP-2840.  
Thesetrans­eivers­analsobeusedforappli­ationswhi­h  
requiredifferentBitErrorRate(BER)performan­e. Figure6  
illustrates the typi­al trade-off between link BER and the  
re­eivers input opti­al power level.  
ꢄ
Transceiver Jitter Performance  
Recommended Handling Precautions  
The Avago Te­hnologies 1300 nm trans­eivers are de- Avago Te­hnologies re­ommends that normal stati­ pre-  
signed to operate per the system jitter allo­ations stated ­autions be taken in the handling and assembly of these  
in Tables E1 of Annexes E of the FDDI PMD and LCF-PMD trans­eivers to prevent damage whi­h may be indu­ed  
standards.  
by ele­trostati­ dis­harge (ESD). The AFBR-5100Z series  
of trans­eivers meet MIL-STD-883C Method 3015.4 Class  
2 produ­ts.  
TheAvagoTe­hnologies1300nmtransmitterswilltolerate  
theworst­aseinputele­tri­aljitterallowedinthesetables  
withoutviolatingtheworst­aseoutputjitterrequirements Care should be used to avoid shorting the re­eiver data or  
of Se­tions 8.1 A­tive Output Interfa­e of the FDDI PMD signal dete­t outputs dire­tly to ground without proper  
and LCF-PMD standards.  
­urrent limiting impedan­e.  
TheAvagoTe­hnologies1300nmre­eiverswilltoleratethe  
worst­aseinputopti­aljitterallowedinSe­tions8.2A­tive  
Input Interfa­e of the FDDI PMD and LCF-PMD standards  
without violating the worst ­ase output ele­tri­al jitter  
allowed in the Tables E1 of the Annexes E.  
The jitter spe­ifi­ations stated in the following 1300 nm  
trans­eiverspe­ifi­ationtablesarederivedfromthevalues  
in Tables E1 of Annexes E. They represent the worst ­ase  
jitter­ontributionthatthetrans­eiversareallowedtomake  
to the overall system jitter without violating the Annex E  
allo­ation example. In pra­ti­e the typi­al ­ontribution of  
the Avago Te­hnologies trans­eivers is well below these  
maximum allowed amounts.  
3.0  
2.5  
2.0  
-2  
1 x 10  
-3  
1 x 10  
AFBR-5103Z/5103TZ SERIES  
-4  
1 x 10  
1.5  
1.0  
0.5  
0
-5  
-6  
1 x 10  
CENTER OF SYMBOL  
1 x 10  
-7  
-ꢀ  
1 x 10  
1 x 10  
-10  
2.5 x 10  
1 x 10  
1 x 10  
-11  
-12  
0
25 50 75 100 125 150 175 200  
SIGNAL RATE (MBd)  
-6  
-4  
-2  
0
2
4
RELATIVE INPUT OPTICAL POWER - dB  
CONDITIONS:  
1. PRBS 2 -1  
CONDITIONS:  
1. 125 MBd  
2. PRBS 2 -1  
7
7
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.  
-6  
3. BER = 10  
3. CENTER OF SYMBOL SAMPLING.  
4. T = 25˚ C  
4. T
 
= 25˚ C  
A
A
Figure 5. Transceiver Relative Optical Power Budget at Con-  
stant BER vs. Signaling Rate.  
Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.  
ꢅ
Solder and Wash Process Compatibility  
Board Layout - Decoupling Circuit and Ground  
Planes  
The trans­eivers are delivered with prote­tive pro­ess  
plugs inserted into the duplex SC or duplex ST ­onne­tor Itisimportanttotake­areinthelayoutofyour­ir­uitboard  
re­epta­le.  
toa­hieveoptimumperforman­efromthesetrans­eivers.  
Figure 7 provides a good example of a s­hemati­ for a  
powersupplyde­oupling­ir­uitthatworkswellwiththese  
parts.Itisfurtherre­ommendedthata­ontiguousground  
plane be provided in the ­ir­uit board dire­tly under the  
This pro­ess plug prote­ts the opti­al subassemblies dur-  
ing wave solder and aqueous wash pro­essing and a­ts as  
a dust ­over during shipping.  
These trans­eivers are ­ompatible with either industry trans­eiver to provide a low indu­tan­e ground for signal  
standard wave or hand solder pro­esses.  
return ­urrent. This re­ommendation is in keeping with  
good high frequen­y board layout pra­ti­es.  
Shipping Container  
Board Layout - Hole Pattern  
The trans­eiver is pa­kaged in a shipping ­ontainer de-  
signed to prote­t it from me­hani­al and ESD damage The Avago Te­hnologies trans­eiver ­omplies with the  
during shipment or storage.  
­ir­uitboard“CommonTrans­eiverFootprint”holepattern  
defined in the original multisour­e announ­ement whi­h  
defined the 1x9 pa­kage style.This drawing is reprodu­ed  
in Figure 8 with the addition of ANSI Y14.5M ­ompliant  
dimensioning to be used as a guide in the me­hani­al  
layout of your ­ir­uit board.  
Rx  
Tx  
Board Layout - Mechanical  
NO INTERNAL CONNECTION  
NO INTERNAL CONNECTION  
Forappli­ationsprovidinga­hoi­eofeitheraduplexSCor  
a duplex ST ­onne­tor interfa­e, while utilizing the same  
pinout on the printed ­ir­uit board, the ST port needs to  
protrude from the ­hassis panel a minimum of 9.53 mm  
for suffi­ient ­learan­e to install the ST ­onne­tor.  
AFBR-510XZ  
TOP VIEW  
Rx  
Rx  
Tx  
Tx  
V
RD  
2
RD  
3
SD  
4
V
V
TD  
7
TD  
ꢀ
V
EE  
1
CC  
CC  
EE  
5
6
9
Please refer to Figure 8A for a me­hani­al layout detailing  
there­ommendedlo­ationoftheduplexSCandduplexST  
trans­eiver pa­kages in relation to the ­hassis panel.  
C1  
C2  
V
Forbothshieldeddesignoptions,Figure8bidentifiesfront  
panel aperture dimensions.  
CC  
R2  
R3  
C5  
L1  
L2  
TERMINATION  
AT PHY  
R1  
R4  
DEVICE  
INPUTS  
V
C3  
C4  
CC  
R5  
R7  
V
FILTER  
CC  
CC  
AT V PINS  
TRANSCEIVER  
TERMINATION  
AT TRANSCEIVER  
INPUTS  
C6  
R9  
R6  
Rꢀ  
R10  
RD  
RD  
SD  
V
TD  
TD  
CC  
NOTES:  
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT  
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT  
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.  
R1 = R4 = R6 = Rꢀ = R10 = 130 OHMS.  
R2 = R3 = R5 = R7 = R9 = ꢀ2 OHMS.  
C1 = C2 = C3 = C5 = C6 = 0.1 µF.  
C4 = 10 µF.  
Figure 7. Recommended Decoupling and Termination Circuits  
ꢆ
Regulatory Compliance  
Electromagnetic Interference (EMI)  
These trans­eiver produ­ts are intended to enable ­om- Most equipment designs utilizing these highspeed trans-  
mer­ialsystemdesignerstodevelopequipmentthat­om- ­eivers from AvagoTe­hnologies will be required to meet  
plies with the various international regulations governing the requirements of FCC in the United States, CENELEC  
­ertifi­ation of Information Te­hnology Equipment. See EN55022 (CISPR 22) in Europe and VCCI in Japan.  
the Regulatory Complian­e Table for details. Additional  
These produ­ts are suitable for use in designs ranging  
information is available from your Avago Te­hnologies  
from a desktop ­omputer with a single trans­eiver to a  
sales representative.  
­on­entrator or swit­h produ­t with a large number of  
trans­eivers.  
Electrostatic Discharge (ESD)  
In all well-designed ­hassis, two 0.5”holes for ST ­onne­-  
tors to protrude through will provide 4.6dB more shield-  
ing than one 1.2” duplex SC re­tangular ­utout. Thus, in  
a well-designed ­hassis, the duplex ST 1x9 trans­eiver  
emissionswillbeidenti­altotheduplexSC1x9trans­eiver  
emissions.  
There are two design ­ases in whi­h immunity to ESD  
damage is important.  
The first ­ase is during handling of the trans­eiver prior  
to mounting it on the ­ir­uit board. It is important to use  
normalESDhandlingpre­autionsforESDsensitivedevi­es.  
These pre­autions in­lude using grounded wrist straps,  
work ben­hes, and floor mats in ESD ­ontrolled areas.  
The se­ond ­ase to ­onsider is stati­ dis­harges to the  
exterior of the equipment ­hassis ­ontaining the trans-  
­eiver parts. To the extent that the duplex SC ­onne­tor  
is exposed to the outside of the equipment ­hassis it may  
be subje­t to whatever ESD system level test ­riteria that  
the equipment is intended to meet.  
1.9 0.1  
.075 .004  
∅�  
(2X)  
-A-  
20.32  
.ꢀ00  
¯0.000  
M A  
0.ꢀ 0.1  
.032 .004  
∅�  
(9X)  
20.32  
.ꢀ00  
¯0.000  
M A  
2.54  
.100  
(ꢀX)  
TOP VIEW  
Figure 8. Recommended Board Layout Hole Pattern  
ꢇ
42.0  
24.ꢀ  
9.53  
12.0  
(NOTE 1)  
0.51  
12.09  
25.4  
39.12  
11.1  
6.79  
0.75  
25.4  
NOTE 1: MINIMUM DISTANCE FROM FRONT  
OF CONNECTOR TO THE PANEL FACE.  
Figure 8a. Recommended Common Mechanical Layout for SC and ST 1x9 Connectored Transceivers.  
10  
0.ꢀ  
(0.032)  
2x  
0.ꢀ  
(0.032)  
2x  
+ 0.5  
Ð 0.25  
10.9  
0.43  
+ 0.02  
Ð 0.01  
(
)
6.35  
(0.25)  
MODULE  
27.4 0.50  
(1.0ꢀ 0.02)  
9.4  
(0.374)  
PROTRUSION  
PCB BOTTOM VIEW  
DIMENSIONS ARE IN MILLIMETERS (INCHES).  
ALL DIMENSIONS ARE 0.025 ꢁꢁ UNLESS OTHERWISE SPECIFIED.  
Figure 8b. Dimensions Shown for Mounting Module with Extended Shield to Panel.  
11  
Regulatory Compliance Table  
Feature  
Test Method  
Performance  
Ele­trostati­ Dis­harge (ESD) to MIL-STD-883C  
the Ele­tri­al Pins Method 3015.4  
Meets Class 2 (2000 to 3999 Volts)  
Withstand up to 2200V applied between  
ele­tri­al pins  
Ele­trostati­ Dis­harge (ESD) to Variation of IEC 801-2  
the Duplex SC Re­epta­le  
Typi­ally withstand at least 25 kV without  
damage when the Duplex SC Conne­tor  
Re­epta­le is ­onta­ted by a Human Body  
Model probe.  
Ele­tromagneti­  
Interferen­e (EMC)  
FCC CLass B  
Typi­ally provide a 13 dB margin to the  
noted standards, however, it should be  
noted that final margin depends on the  
­ustomer’s board and ­hasis design.  
CENELEC CEN55022  
Class B (CISPR 22B)  
VCCI Class 2  
Immunity  
Variation of IEC  
61000-4-3  
Typi­ally show no measurable effe­t from a  
10 V/m field swept from 10 to 450 MHz ap-  
plied to the trans­eiver when mounted to  
a ­ir­uit ­ard without a ­hassis en­losure.  
200  
3.0  
3.5  
1ꢀ0  
1.5  
160  
2.0  
140  
120  
100  
2.5  
3.0  
3.5  
t
- TRANSMITTER  
r/f  
OUTPUT OPTICAL  
RISE/FALL TIMES - ns  
1200 1300 1320 1340 1360 13ꢀ0  
l
- TRANSMITTER OUTPUT OPTICAL  
CENTER WAVELENGTH -nꢁ  
C
AFBR-5103Z FDDI TRANSMITTER TEST RESULTS  
OF l , Dl AND t ARE CORRELATED AND  
C
r/f  
COMPLY WITH THE ALLOWED SPECTRAL WIDTH  
AS A FUNCTION OF CENTER WAVELENGTH FOR  
VARIOUS RISE AND FALL TIMES.  
Figure 9. Transmitter Output Optical Spectral Width (FWHM) vs.  
Transmitter Output Optical Center Wavelength and Rise/Fall  
Times.  
1ꢀ  
Transceiver Reliability and Performance Qualification  
Data  
Immunity  
Equipment utilizing these trans­eivers will be subje­t to  
radio-frequen­y ele­tromagneti­ fields in some environ-  
ments. These trans­eivers have a high immunity to su­h  
fields.  
The 1x9 trans­eivers have passed Avago Te­hnologies’  
reliability and performan­e qualifi­ation testing and are  
undergoing ongoing quality monitoring. Details are avail-  
able from your Avago Te­hnologies’sales representative.  
For additional information regarding EMI, sus­eptibility,  
ESD and ­ondu­ted noise testing pro­edures and results  
on the 1x9 Trans­eiver family, please refer to Appli­a-  
tions Note 1075, Testing and Measuring Ele­tromagneti­  
Compatibility Performan­e of the AFBR-510X/-520X Fiber  
Opti­ Trans­eivers.  
4.40  
1.975  
1.25  
4.ꢀ50  
1.525  
0.525  
10.0  
5.6  
1.025  
0.075  
1.00  
0.975  
0.90  
100% TIME  
INTERVAL  
40 0.7  
0.50  
0.10  
0.725  
0.725  
0% TIME  
INTERVAL  
0.025  
0.0  
0.075  
-0.025  
-0.05  
1.525  
0.525  
5.6  
1.975  
4.40  
10.0  
4.ꢀ50  
ꢀ0 500 ꢂꢂꢁ  
TIME - ns  
THE AFBR-5103Z OUTPUT OPTICAL PULSE SHAPE SHALL FIT WITHIN THE BOUNDARIES  
OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTS.  
Figure 10. Output Optical Pulse Envelope.  
1ꢁ  
Accessory Duplex SC Connectored Cable Assemblies  
Applications Support Materials  
AvagoTe­hnologiesre­ommendsforoptimal­ouplingthe  
use of flexible-body duplex SC ­onne­tored ­able.  
Conta­t your lo­al AvagoTe­hnologies Component Field  
SalesOffi­eforinformationonhowtoobtainPCBlayouts,  
test boards and demo boards for the 1x9 trans­eivers.  
Accessory Duplex ST Connectored Cable Assemblies  
Evaluation Kits  
AvagoTe­hnologiesre­ommendstheuseofDuplexPush-  
AvsgoTe­hnologies has available three evaluation kits for Pull ­onne­tored ­able for the most repeatable opti­al  
the1x9trans­eivers.Thepurposeofthesekitsistoprovide power ­oupling performan­e.  
thene­essarymaterialstoevaluatetheperforman­eofthe  
AFBR-510XZ family in a pre-existing 1x13 or 2x11 pinout  
systemdesign­onfigurationorwhen­onne­toredtovari-  
ous test equipment.  
1. HFBR-0319 Evaluation Test Fixture Board  
This test fixture ­onverts +5 V ECL 1x9 trans­eivers to –5  
V ECL BNC ­oax ­onne­tions so that dire­t ­onne­tions  
to industry standard fiber opti­ test equipment ­an be  
a­­omplished.  
5
AFBR-5103Z SERIES  
4
3
-10  
2.5 x 10 BER  
2
-12  
1.0 x 10 BER  
1
0
-4 -3 -2 -1  
EYE SAMPLING TIME POSITION (ns)  
CONDITIONS:  
0
1
2
3
4
1.T = 25˚ C  
A
2. V = 5 Vdc  
CC  
3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.  
4. INPUT OPTICAL POWER IS NORMALIZED TO  
CENTER OF DATA SYMBOL.  
5. NOTE 20 AND 21 APPLY.  
Figure 11. Relative Input Optical Power vs. Eye Sampling Time  
Position.  
1ꢂ  
-31.0 dBꢁ  
MIN (P + 4.0 dB OR -31.0 dBꢁ)  
O
P (P + 1.5 dB  
A
O
< P < -31.0 dBꢁ)  
P
= MAX (P OR -45.0 dBꢁ)  
S
S
A
O
2
(P = INPUT POWER FOR BER < 10 )  
INPUT OPTICAL POWER  
INPUT OPTICAL POWER  
(
>
>
4.0 dB STEP DECREASE)  
(
1.5 dB STEP INCREASE)  
-45.0 dBꢁ  
ANS MAX  
-
AS MAX  
-
SIGNAL DETECT  
-
(ON)  
SIGNAL DETECT  
-
(OFF)  
TIME  
AS MAX - MAXIMUM ACQUISITION TIME (SIGNAL).  
-
AS MAX IS THE MAXIMUM SIGNAL DETECT ASSERTION TIME FOR THE STATION.  
-
-
AS MAX SHALL NOT EXCEED 100.0 µs (130 µs FOR -40˚C to 0˚C).  
-
THE DEFAULT VALUE OF AS MAX IS 100.0 µs.  
-
ANS MAX - MAXIMUM ACQUISITION TIME (NO SIGNAL).  
-
ANS MAX IS THE MAXIMUM SIGNAL DETECT DEASSERTION TIME FOR THE STATION.  
-
-
ANS MAX SHALL NOT EXCEED 350 µs (130 µs FOR -40˚C to 0˚C).  
-
THE DEFAULT VALUE OF AS MAX IS 350 µs.  
-
Figure 12. Signal Detect Thresholds and Timing.  
AFBR-5103Z Series  
Absolute Maximum Ratings  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
100  
260  
10  
Unit  
°C  
Reference  
Storage Temperature  
Lead Soldering Temperature  
Lead Soldering Time  
Supply Voltage  
T
S
-40  
T
°C  
SOLD  
SOLD  
t
se­.  
V
V
CC  
-0.5  
-0.5  
7.0  
Data Input Voltage  
Differential Input Voltage  
Output Current  
V
I
V
CC  
V
V
D
1.4  
50  
V
Note 1  
I
mA  
O
1ꢃ  
AFBR-5103Z Series  
Recommended Operating Conditions*  
Parameter  
Symbol  
Min.  
0
Typ.  
Max.  
70  
Unit  
°C  
V
Reference  
Ambient Operating Temperature  
Supply Voltage  
T
A
V
CC  
4.75  
-1.810  
-1.165  
5.25  
Data Input Voltage - Low  
Data Input Voltage - High  
Data and Signal Dete­t Output Load  
V - V  
IL CC  
-1.475  
-0.880  
V
V
- V  
V
IH CC  
R
L
50  
ý
Note 2  
*Applies to AFBR-5103Z & AFBR-5103TZ & AFBR-5103PZ/-5103PEZ Series ex­ept for AFBR-5103AZ/-5103ATZ. T for  
A
AFBR-5103AZ/-5103ATZ is -40°C and 85°C.  
Transꢁitter Electrical Characteristics*  
(T = 0°C to ꢅ0°C, V = ꢂ.ꢅꢃ V to ꢃ.ꢀꢃ V)  
A
CC  
Parameter  
Symbol  
Min.  
Typ.  
145  
0.76  
0
Max.  
185  
Unit  
mA  
W
Reference  
Supply Current  
I
Note 3  
CC  
Power Dissipation  
P
DISS  
0.97  
Data Input Current - Low  
Data Input Current - High  
I
I
-350  
µA  
IL  
IH  
14  
350  
µA  
*Applies to AFBR-5103Z & AFBR 5103TZ & AFBR-5103PZ/-5103PEZ Series ex­ept for AFBR-5103AZ/-5103ATZ. T for  
A
AFBR-5103AZ/-5103ATZ is -40°C and 85°C..  
Receiver Electrical Characteristics  
(T = 0°C to 70°C, V = 4.75 V to 5.25 V)*  
A
CC  
Parameter  
Symbol Min.  
Typ.  
82  
Max.  
145  
0.5  
Unit  
mA  
W
Reference  
Note 4  
Note 5  
Note 6  
Note 6  
Note 7  
Note 7  
Note 6  
Note 6  
Note 7  
Note 7  
Supply Current  
I
CC  
Power Dissipation  
P
DISS  
0.3  
Data Output Voltage - Low  
Data Output Voltage - High  
Data Output Rise Time  
V
- V  
-1.83  
-1.085  
0.35  
-1.55  
-0.88  
2.2  
V
OL  
CC  
V
OH  
- V  
V
CC  
t
t
ns  
ns  
V
r
Data Output Fall Time  
0.35  
2.2  
f
Signal Dete­t Output Voltage - Low  
Signal Dete­t Output Voltage - High  
Signal Dete­t Output Rise Time  
Signal Dete­t Output Fall Time  
V
- V  
-1.83  
-1.085  
0.35  
-1.55  
-0.88  
2.2  
OL  
CC  
V
OH  
- V  
V
CC  
t
t
ns  
ns  
r
0.35  
2.2  
f
*Applies to AFBR-5103Z & AFBR 5103TZ & AFBR-5103PZ and 5103PEZ Series ex­ept for AFBR-5103AZ/-5103ATZ. T for AFBR-5103AZ/-5103ATZ is  
A
-40°C and 85°C.  
1ꢄ  
AFBR-5103Z/-5103TZ  
Transmitter Optical Characteristics  
(T = 0°C to 70°C, V = 4.75 V to 5.25 V)  
A
CC  
Parameter  
Symbol Min.  
Typ.  
Max.  
Unit  
Reference  
Output Opti­al Power  
62.5/125 µm, NA = 0.275 Fiber EOL  
BOL  
P
O
-19  
-20  
-16.8  
-14  
dBm avg.  
Note 11  
Output Opti­al Power  
50/125 µm, NA = 0.20 Fiber  
BOL  
EOL  
P
-22.5  
-23.5  
-20.3  
-14  
dBm avg.  
Note 11  
Note 12  
Note 13  
O
Opti­al Extin­tion Ratio  
10  
-10  
%
dB  
Output Opti­al Power at Logi­ “0”State  
Center Wavelength  
P
O
(“0”)  
-45  
1380  
200  
3.0  
dBm avg.  
l
C
1270  
1308  
137  
1.0  
nm  
Note 14  
Figure 9  
Spe­tral Width - FWHM  
Opti­al Rise Time  
Ðl  
nm  
Note 14  
Figure 9  
t
t
0.6  
0.6  
ns  
Note 14, 15  
Figure 9, 10  
r
f
Opti­al Fall Time  
2.1  
3.0  
ns  
Note 14, 15  
Figure 9, 10  
Duty Cy­le Distortion  
Contributed by the  
Transmitter  
DCD  
DDJ  
0.02  
0.6  
ns p-p  
Note 16  
Data Dependent Jitter  
Contributed by the  
Transmitter  
0.02  
0.6  
ns p-p  
Note 17  
1ꢅ  
AFBR-5103Z/-5103TZ  
Receiver Optical and Electrical Characteristics  
(T = 0°C to 70°C, V = 4.75 V to 5.25 V)  
A
CC  
Parameter  
Symbol  
Min.  
Typ. Max.  
Unit  
dBm avg.  
Reference  
Input Opti­al Power Minimum at  
Window Edge  
P
P
(W)  
-33.5 -31  
Note 19  
Figure 11  
IN Min.  
IN Min.  
IN Max.  
Input Opti­al Power Minimum at  
Eye Center  
(C)  
-34.5 -31.8 dBm avg.  
Note 20  
Figure 11  
Input Opti­al Power Maximum  
Operating Wavelength  
P
l
-14  
-11.8  
dBm avg.  
Note 19  
1270  
1380 nm  
Duty Cy­le Distortion Contributed DCD  
by the Re­eiver  
0.02 0.4  
ns p-p  
Note 8  
Note 9  
Note 10  
Data Dependent Jitter Contributed DDJ  
by the Re­eiver  
0.35 1.0  
ns p-p  
Random Jitter Contributed by the RJ  
Re­eiver  
1.0  
2.14 ns p-p  
Signal Dete­t - Asserted  
Signal Dete­t - Deasserted  
Signal Dete­t - Hysteresis  
P
P + 1.5 dB  
-33  
dBm avg.  
dBm avg.  
Note 21, 22  
Figure 12  
A
D
P
-45  
Note 23, 24  
Figure 12  
D
P - P  
A
1.5  
0
2.4  
55  
dB  
µs  
Figure 12  
D
Signal Dete­t Assert Time (off to  
on)  
AS_Max  
100  
130  
350  
Note 21,  
Figure 12  
SignalDete­tAssert Time (off to on) AS_Max  
for -40°C to 0°C  
0
0
55  
µs  
µs  
Note 21,  
Figure 12  
Signal Dete­t Deassert Time (on  
to off)  
ANS_Max  
110  
Note 23, 24  
Figure 12  
Notes:  
1. This is the maximum voltage that ­an be applied a­ross the Differen-  
tial Transmitter Data Inputs to prevent damage to the input ESD  
prote­tion ­ir­uit.  
9. Data Dependent Jitter ­ontributed by the re­eiver is spe­ified with  
the FDDI DDJ test pattern des­ribed in the FDDI PMD Annex A.5. The  
inputopti­alpowerlevelis-20dBmaverage.SeeAppli­ationInforma-  
tion - Trans­eiver Jitter Se­tion for further information.  
2. The outputs are terminated with 50ý ­onne­ted to V -2 V.  
CC  
3. The power supply ­urrent needed to operate the transmitter is  
provided to differential ECL ­ir­uitry.This ­ir­uitry maintains a nearly  
­onstant­urrentflowfromthepowersupply.Constant­urrentopera-  
tionhelpstopreventunwantedele­tri­alnoisefrombeinggenerated  
and ­ondu­ted or emitted to neighboring ­ir­uitry.  
10. Random Jitter ­ontributed by the re­eiver is spe­ified with an IDLE  
Line State, 125 MBd (62.5 MHz square-wave), input signal. The input  
opti­al power level is at maximum “P  
(W)”. See Appli­ation  
IN Min.  
Information - Trans­eiver Jitter Se­tion for further information.  
11. These opti­al power values are measured with the following  
­onditions:  
• The Beginning of Life (BOL) to the End of Life (EOL) opti­al power  
degradation is typi­ally 1.5 dB per the industry ­onvention for  
long wavelength LEDs. The a­tual degradation observed in Avago  
Te­hnologies’ 1300 nm LED produ­ts is < 1 dB, as spe­ified in this  
data sheet.  
• Over the spe­ified operating voltage and temperature ranges.  
• With HALT Line State, (12.5 MHz square-wave), input signal.  
• At the end of one meter of noted opti­al fiber with ­ladding modes  
removed.Theaveragepowervalue­anbe­onvertedtoapeakpower  
value by adding 3 dB. Higher output opti­al power transmitters are  
available on spe­ial request.  
12. The Extin­tion Ratio is a measure of the modulation depth of the  
opti­al signal. The data“0”output opti­al power is ­ompared to the  
data “1” peak output opti­al power and expressed as a per­entage.  
With the transmitter driven by a HALT Line State (12.5 MHz square-  
wave) signal, the average opti­al power is measured. The data “1”  
4. This value is measured with the outputs terminated into 50 ý ­on-  
ne­ted to V - 2 V and an Input Opti­al Power level of -14 dBm  
CC  
average.  
5. The power dissipation value is the power dissipated in the re­eiver  
itself. Power dissipation is ­al­ulated as the sum of the produ­ts of  
supply voltage and ­urrents, minus the sum of the produ­ts of the  
output voltages and ­urrents.  
6. These values are measured with respe­t to V with the output  
CC  
terminated into 50 ý ­onne­ted to V - 2 V.  
CC  
7. The output rise and fall times are measured between 20% and 80%  
levels with the output ­onne­ted to V -2 V through 50 ý.  
CC  
8. Duty Cy­le Distortion ­ontributed by the re­eiver is measured at  
the 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz  
square-wave), input signal. The input opti­al power level is -20 dBm  
average. See Appli­ation Information - Trans­eiver Jitter Se­tion for  
further information.  
1ꢆ  
peak power is then ­al­ulated by adding 3 dB to the measured  
average opti­al power. The data “0” output opti­al power is found  
by measuring the opti­al power when the transmitter is driven by a  
logi­“0”input. The extin­tion ratio is the ratio of the opti­al power at  
the“0”level ­ompared to the opti­al power at the“1”level expressed  
as a per­entage or in de­ibels.  
ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the re­eiver.  
To test a re­eiver with the worst ­ase FDDI PMD A­tive Input jitter  
­onditionrequiresexa­ting­ontroloverDCD,DDJandRJjitter­ompo-  
nents that is diffi­ult to implement with produ­tion test equipment.  
The re­eiver ­an be equivalently tested to the worst ­ase FDDI PMD  
input jitter ­onditions and meet the minimum output data window  
time-width of 2.13 ns. This is a­­omplished by using a nearly ideal  
inputopti­alsignal(noDCD,insignifi­antDDJandRJ)andmeasuring  
for a wider window time-width of 4.6 ns. This is possible due to the  
­umulative effe­t of jitter ­omponents through their superposition  
(DCD and DDJ are dire­tly additive and RJ ­omponents are rms ad-  
ditive). Spe­ifi­ally, when a nearly ideal input opti­al test signal is  
used and the maximum re­eiver peak-to-peak jitter ­ontributions  
of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns) exist, the minimum  
window time-width be­omes 8.0 ns -0.4 ns - 1.0 ns - 2.14 ns = 4.46  
ns, or ­onservatively 4.6ns. This wider window time-width of 4.6 ns  
guarantees the FDDI PMD Annex E minimum window time-width  
of 2.13 ns under worst ­ase input jitter ­onditions to the Avago  
Te­hnologies re­eiver.  
13. Thetransmitterprovides­omplian­ewiththeneedforTransmit_Dis-  
able ­ommands from the FDDI SMT layer by providing an Output  
Opti­al Power level of <-45 dBm average in response to a logi­ “0”  
input. This spe­ifi­ation applies to either 62.5/125 µm or 50/125 µm  
fiber ­ables.  
14. This parameter ­omplies with the FDDI PMD requirements for the  
tradeoffs between ­enter wave-length, spe­tral width, and rise/fall  
times shown in Figure 9.  
15. Thisparameter­omplieswiththeopti­alpulseenvelopefromtheFDDI  
PMD shown in Figure 10. The opti­al rise and fall times are measured  
from 10% to 90% when the transmitter is driven by the FDDI HALT  
Line State (12.5 MHz square-wave) input signal.  
16. Duty Cy­le Distortion ­ontributed by the transmitter is measured at  
a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz square-  
wave), input signal. See Appli­ation Information - Trans­eiver Jitter  
Performan­e Se­tion of this data sheet for further details.  
17. Data Dependent Jitter ­ontributed by the transmitter is spe­ified  
with the FDDI test pattern des­ribed in FDDI PMD Annex A.5. See  
Appli­ation Information - Trans­eiver Jitter Performan­e Se­tion of  
this data sheet for further details.  
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5  
MHz square-wave), input signal to simulate any ­ross-talk present  
between the transmitter and re­eiver se­tions of the trans­eiver.  
20. All­onditionsofNote19applyex­eptthatthemeasurementismade  
at the ­enter of the symbol with no window time-width.  
21. This value is measured during the transition from low to high levels  
of input opti­al power.  
18. Random Jitter ­ontributed by the transmitter is spe­ified with an  
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See  
Appli­ation Information - Trans­eiver Jitter Performan­e Se­tion of  
this data sheet for further details.  
19. This spe­ifi­ation is intended to indi­ate the performan­e of the  
re­eiver se­tion of the trans­eiver when Input Opti­al Power signal  
­hara­teristi­s are present per the following definitions. The Input  
Opti­al Power dynami­ range from the minimum level (with a win-  
dow time-width) to the maximum level is the range over whi­h the  
22. The Signal Dete­t output shall be asserted within 100 µs (130 µs for  
—40°C to 0°C) after a step in­rease of the Input Opti­al Power. The  
step will be from a low Input Opti­al Power, —45 dBm, into the range  
between greater than P , and —14 dBm.The BER of the re­eiver out-  
A
-2  
put will be 10 or better during the time, LS_Max (15 µs) after Signal  
Dete­t has been asserted. See Figure 12 for more information.  
23. This value is measured during the transition from high to low levels  
ofinputopti­alpower.Themaximumvaluewillo­­urwhentheinput  
opti­al power is either -45 dBm average or when the input opti­al  
-2  
re­eiver is guaranteed to provide output data with a Bit Error Ratio  
power yields a BER of 10 or better, whi­hever power is higher.  
-10  
(BER) better than or equal to 2.5 x 10  
• At the Beginning of Life (BOL)  
.
24. Signal dete­t output shall be de-asserted within 350 µs after a step  
de­rease in the Input Opti­al Power from a level whi­h is the lower  
• Over the spe­ified operating temperature and voltage ranges  
• Input symbol pattern is the FDDI test pattern defined in FDDI PMD  
Annex A.5 with 4B/5B NRZI en­oded data that ­ontains a duty ­y­le  
base-line wander effe­t of 50kHz. This sequen­e ­auses a near worst  
­ase ­ondition for inter-symbol interferen­e.  
• Re­eiver data window time-width is 2.13 ns or greater and ­entered  
at mid-symbol. This worst ­ase window time-width is the minimum  
allowedeye-openingpresentedtotheFDDIPHYPM._Dataindi­ation  
input(PHYinput)pertheexampleinFDDIPMDAnnexE.Thisminimum  
windowtime-widthof2.13nsisbasedupontheworst­aseFDDIPMD  
A­tive Input Interfa­e opti­al ­onditions for peak-to-peak DCD (1.0  
of; -31 dBm or P + 4 dB (P is the power level at whi­h signal dete­t  
D
D
wasdeasserted),toapowerlevelof-45dBmorless.Thisstepde­rease  
will have o­­urred in less than 8 ns. The re­eiver output will have a  
-2  
BER of 10 or better for a period of 12 µs or until signal dete­t is  
deasserted.The input data stream is the Quiet Line State. Also, signal  
dete­t will be deasserted within a maximum of 350µs after the BER  
-2  
of the re­eiver output degrades above 10 for an input opti­al data  
stream that de­ays with a negative ramp fun­tion instead of a step  
fun­tion. See Figure 12 for more information.  
1ꢇ  
Ordering Information:  
1300nm LED, 125 MBd, FDDI, 100 Mbps ATM and  
Fast Eternet  
temperature range 0°C to +70°C  
AFBR-5103Z Duplex SC Conne­tor 1X9, Standard Height  
AFBR-5103TZ Duplex ST Conne­tor 1X9  
AFBR-5103PZ Duplex SC Conne­tor 1x9, Mezzanine  
Height  
AFBR-5103PEZ Duplex SC Conne­tor 1x9, Mezzanine  
Height with Extended Shield  
1300nm LED, 125 MBd, FDDI, 100 Mbps ATM and  
Fast Ethernet  
temperature range –40°C to +85°C  
AFBR-5103AZ Duplex SC Conne­tor 1X9  
AFBR-5103ATZ Duplex ST Conne­tor 1X9  
For product information and a complete list of distributors, please go to our web site: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.  
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.  
5989-2292EN - April 4, 2006  

相关型号：

AFBR-5103AZ

 FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers in Low Cost 1x9 Package Style
AVAGO

AFBR-5103PEZ

 FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers in Low Cost 1x9 Package Style
AVAGO

AFBR-5103PZ

 FDDI, 100 Mbps ATM, and Fast Ethernet Transceivers in Low Cost 1x9 Package Style
AVAGO

AFBR-5103TZ

 Transceiver, Through Hole Mount,
AGILENT

AFBR-5103TZ

 FIBER OPTIC TRANSCEIVER, 1270-1380nm, 125Mbps(Tx), 125Mbps(Rx), BOARD/PANEL MOUNT, SIP, ST CONNECTOR, ROHS COMPLIANT, SIP-9
AVAGO

AFBR-5103Z

 FIBER OPTIC TRANSCEIVER, 1270-1380nm, 125Mbps(Tx), 125Mbps(Rx), BOARD/PANEL MOUNT, SIP, SC CONNECTOR, ROHS COMPLIANT, SIP-9
AVAGO

AFBR-5205APZ

 ATM Multimode Fiber Transceivers for SONET OC-3/SDH STM-1 in Low Cost 1x9 Package Style
BOARDCOM

AFBR-5205ATZ

 FIBER OPTIC TRANSCEIVER, 1270-1380nm, 155Mbps(Tx), 155Mbps(Rx), PANEL MOUNT, SIP, ST CONNECTOR, ROHS COMPLIANT, SIP-9
AVAGO

AFBR-5205ATZ

 ATM Multimode Fiber Transceivers for SONET OC-3/SDH STM-1 in Low Cost 1x9 Package Style
BOARDCOM

AFBR-5205AZ

 ATM Multimode Fiber Transceivers for SONET OC-3/SDH STM-1 in Low Cost 1x9 Package Style
BOARDCOM

AFBR-5205PEZ

 Multimode fi ber ATM backbone links
AVAGO

AFBR-5205PEZ

 ATM Multimode Fiber Transceivers for SONET OC-3/SDH STM-1 in Low Cost 1x9 Package Style
BOARDCOM
©2020 ICPDF网 联系我们和版权申明