HCPL-063N#060 [AVAGO]
1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, 0.400 INCH, SOIC-8;
| 型号： | HCPL-063N#060 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, 0.400 INCH, SOIC-8 输出元件 光电 |
| 文件： | 总17页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-261A, HCPL-061A, HCPL-263A, HCPL-063A
HCPL-261N, HCPL-061N, HCPL-263N, HCPL-063N
HCMOS Compatible, High CMR, 10 MBd Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Features
Description
• HCMOS/LSTTL/TTL performance compatible
The HCPL-261A family of optically coupled gates shown
on this data sheet provide all the benefits of the in-
dustry standard 6N137 family with the added benefit
of HCMOS compatible input current. This allows direct
interface to all common circuit topologies without ad-
ditional LED buffer or drive components. The AlGaAs
LED used allows lower drive currents and reduces
degradation by using the latest LED technology. On
the single channel parts, an enable output allows the de-
tector to be strobed. The output of the detector IC is an
open collector schottky-clamped transistor. The internal
shield provides a minimum common mode transient im-
munity of 1000V/µs for the HCPL-261A family and 15000
V/µs for the HCPL-261N family.
• 1000 V/µs minimum Common Mode Rejection (CMR)
at VCM = 50 V (HCPL-261A family) and 15 kV/µs
minimum CMR at VCM = 1000 V (HCPL-261N family)
• High speed: 10 MBd typical
• AC and DC performance specified over industrial
temperature range -40°C to +85°C
• Available in 8 pin DIP, SOIC-8 packages
• Safety approval:
– UL recognized per UL1577 3750Vrms for 1 minute
and 5000Vrms for 1 minute (Option 020)
– CSA Approved
– IEC/EN/DIN EN 60747-5-2 approved
Functional Diagram
Applications
HCPL-261A/261N
HCPL-061A/061N
HCPL-263A/263N
HCPL-063A/063N
• Low input current (3.0 mA) HCMOS compatible
NC
ANODE
CATHODE
NC
1
2
V
V
V
ANODE
CATHODE
CATHODE
ANODE
1
2
V
V
8
7
8
7
CC
CC
O1
O2
1
1
version of 6N137 optocoupler
E
• Isolated line receiver
V
3
4
6
5
3
4
6
5
O
2
2
• Simplex/multiplex data transmission
• Computer-peripheral interface
• Digital isolation for A/D, D/A conversion
• Switching power supplies
GND
GND
SHIELD
SHIELD
TRUTH TABLE
TRUTH TABLE
(POSITIVE LOGIC)
(POSITIVE LOGIC)
LED ENABLE OUTPUT
LED OUTPUT
• Instrumentation input/output isolation
• Ground loop elimination
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
L
H
H
H
L
ON
OFF
L
H
•ꢀ Pulse transformer replacement
H
The connection of a 0.1 µF bypass capacitor between pins 5 and 8 is
required.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
Widebody
Hermetic
Input
Minimum CMR
8-Pin DIP (300 Mil)
Small-Outline SO-8 (400 Mil)
On-
Current
(mA)
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
Dual
Channel
Package
Single
Channel
Package
Single and
Dual Channel
Packages
dV/dt
(V/µs)
V
Output
Enable
(CVM)
NA
NA
50
5
YES
NO
YES
NO
YES
NO
YES
YES
YES
NO
YES
6N137[1]
HCPL-0600[1]
HCPL-0601[1]
HCPL-0611[1]
HCNW137[1]
HCNW2601[1]
HCNW2611[1]
HCPL-2630[1]
HCPL-2631[1]
HCPL-4661[1]
HCPL-0630[1]
HCPL-0631[1]
HCPL-0661[1]
5,000
10,000
HCPL-2601[1]
HCPL-2611[1]
1,000
1,000
3,500
1,000
50
300
50
HCPL-2602[1]
HCPL-2612[1]
HCPL-261A
3
HCPL-061A
HCPL-061N
HCPL-263A
HCPL-263N
HCPL-063A
HCPL-063N
1,000[2]
1,000
1,000
50
HCPL-261N
NO
[3]
12.5
HCPL-193X[1]
HCPL-56XX[1]
HCPL-66XX[1]
Notes:
1. Technical data are on separate Avago publications.
2. 15 kV/µs with VCM = 1 kV can be achieved using Avago application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
Schematic
HCPL-261A/261N
HCPL-061A/061N
HCPL-263A/263N
HCPL-063A/063N
I
I
F
CC
I
CC
V
V
CC
O1
V
V
CC
O
8
7
8
6
2+
1
+
I
F1
I
O1
I
O
V
F1
–
2
V
F
–
3
SHIELD
GND
5
SHIELD
I
E
7
E
3
–
I
F2
V
I
O2
V
O2
6
5
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 16).
V
F2
+
4
GND
SHIELD
2
Ordering Information
HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577
UL 5000
Vrms/ 1
Minute
rating
Option
Part
number
RoHS
Non RoHS
Compliant Compliant
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN EN
60747-5-2 Quantity
Package
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-560E
-000E
-500E
-520E
-060E
-560E
No option
#300
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
X
X
X
X
#500
X
X
X
HCPL-261A
HCPL-261N
HCPL-263A
HCPL-263N
#020
X
X
X
#320
300mil DIP-8
X
X
X
X
#520
#060
X
X
X
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
#360
X
X
X
X
#560
No option
#500
HCPL-061A
HCPL-061N
HCPL-063A
HCPL-063N
X
X
X
X
X
X
#520
SO-8
X
#060
X
X
100 per tube
1500 per reel
#560
X
X
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry. Combination of Option 020 and Option 060 is not available.
Example 1:
HCPL-261A-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-261N to order product of 300mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation‘#XXX’is used for existing products, while (new) products launched since 15th July 2001 and RoHS
compliant option will use ‘-XXXE‘.
3
HCPL-261A/261N/263A/263N Outline Drawing
Pin Location (for reference only)
9.40 (0.370)
9.90 (0.390)
8
1
7
6
5
4
TYPE NUMBER
0.20 (0.008)
0.33 (0.013)
OPTION CODE*
DATE CODE
6.10 (0.240)
6.60 (0.260)
A XXXXZ
YYWW
7.36 (0.290)
7.88 (0.310)
5 TYP.
2
3
PIN ONE
1.78 (0.070) MAX.
1.19 (0.047) MAX.
DIMENSIONS IN MILLIMETERS AND (INCHES).
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.92 (0.115) MIN.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
0.76 (0.030)
1.40 (0.056)
0.65 (0.025) MAX.
2.28 (0.090)
2.80 (0.110)
Figure 1. 8-Pin dual in-line package device outline drawing.
LAND PATTERN RECOMMENDATION
1.02 (0.040)
9.65 ± 0.25
(0.380 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2
3
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
0.20 (0.008)
0.33 (0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12 NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.540
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Figure 2. Gull wing surface mount option #300.
4
HCPL-061A/061N/063A/063N Outline Drawing
LAND PATTERN RECOMMENDATION
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXX
3.937 ± 0.127
(0.155 ± 0.005)
YWW
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
1
2
3
4
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
7
* 5.080 ± 0.127
(0.200 ± 0.005)
45
X
(0.017)
3.175 ± 0.127
(0.125 ± 0.005)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
*
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Figure 3. 8-Pin Small Outline Package Device Drawing.
Solder Reflow Thermal Profile
Regulatory Information
300
The HCPL-261A and HCPL-261N
families have been approved by the
following organizations:
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5 C ± 0.5°C/SEC.
UL
SOLDERING
TIME
200°C
30
160°C
150°C
140°C
Recognized under UL 1577, Com-
ponent Recognition Program, File
E55361.
SEC.
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
CSA
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
0
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
IEC/EN/DIN EN 60747-5-2
Approved under:
Recommended Pb-Free IR Profile
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
t
p
20-40 SEC.
260 +0/-5 °C
T
T
p
217 °C
(Option 060 only)
L
RAMP-UP
3 C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
150 - 200 °C
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 °C, = 150 °C
T
T
smin
smax
Note: Non-halide flux should be used.
5
Insulation and Safety Related Specifications
8-Pin DIP
(300 Mil)
Value
SO-8
Value
Parameter
Symbol
Units Conditions
Minimum External Air
Gap (External
Clearance)
L(101)
7.1
4.9
mm
mm
mm
Measured from input terminals to
output terminals, shortest distance
through air.
Minimum External
Tracking (External
Creepage)
L(102)
7.4
4.8
Measured from input terminals to
output terminals, shortest distance
path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08
0.08
Through insulation distance, conductor
to conductor, usually the direct
distance between the photoemitter and
photodetector inside the optocoupler
cavity.
Tracking Resistance
(Comparative Tracking
Index)
CTI
200
IIIa
200
IIIa
Volts DIN IEC 112/ VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89,
Table 1)
Option 300 – surface mount classification is Class A in accordance with CECC 00802.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
Description
Symbol
PDIP Option 060
SO-8 Option 60
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V rms
I-IV
I-III
I-II
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 600 V rms
I-IV
I-III
Climatic Classification
55/85/21
55/85/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test
with tm = 1 sec, Partial Discharge < 5 pC
2
630
2
566
VIORM
VPR
Vpeak
Vpeak
1181
1063
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
VPR
945
849
Vpeak
Vpeak
Highest Allowable Overvoltage*
VIOTM
6000
4000
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(See below for Thermal Derating Curve Figures)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
TS
IS,INPUT
PS,OUTPUT
175
230
600
≥ 109
150
150
600
≥ 109
˚C
mA
mW
RS
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
6
Absolute Maximum Ratings
Parameter
Symbol
Min.
-55
-40
Max.
125
+85
10
3
Units
°C
Note
Storage Temperature
TS
Operating Temperature
Average Input Current
Reverse Input Voltage
T
°C
A
IF(AVG)
VR
mA
1
2
Volts
Volts
Volts
mA
Supply Voltage
V
-0.5
-0.5
7
CC
Enable Input Voltage
VE
IO
5.5
50
60
7
Output Collector Current (Each Channel)
Output Power Dissipation (Each Channel)
Output Voltage (Each channel)
PO
VO
mW
Volts
3
-0.5
Lead Solder Temperature
(Through Hole Parts Only)
260°C for 10 s, 1.6 mm Below Seating Plane
Solder Reflow Temperature Profile
(Surface Mount Parts Only)
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
VFL
Min.
-3
Max.
0.8
10
Units
V
Input Voltage, Low Level
Input Current, High Level
Power Supply Voltage
High Level Enable Voltage
Low Level Enable Voltage
Fan Out (at RL = 1 kΩ)
Output Pull-up Resistor
Operating Temperature
IFH
3.0
4.5
2.0
0
mA
V
5.5
Volts
Volts
Volts
CC
VEH
VEL
N
V
CC
0.8
5
TTL Loads
RL
TA
330
-40
4k
85
Ω
°C
7
Electrical Specifications
Over recommended operating temperature (T = -40°C to +85°C) unless otherwise specified.
A
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
High Level Output
Current
IOH
3.1
100
µA
V
CC = 5.5 V, VO = 5.5 V,
4
18
VF = 0.8 V, VE = 2.0 V
Low Level Output
Voltage
VOL
0.4
0.6
V
VCC = 5.5 V, IOL = 13 mA
(sinking), IF = 3.0 mA,
VE = 2.0 V
5, 8 4, 18
High Level Supply
Current
ICCH
7
9
10
15
mA VE = 0.5 V**
V
CC = 5.5 V
4
IF = 0 mA
Dual Channel
Products***
Low Level Supply
Current
ICCL
8
13
21
mA
VE = 0.5 V**
V
CC = 5.5 V
IF = 3.0 mA
12
Dual Channel
Products***
High Level Enable
Current**
IEH
IEL
-0.6
-0.9
1.3
-1.6
-1.6
1.6
mA
mA
V
V
CC = 5.5 V, VE = 2.0 V
CC = 5.5 V, VE = 0.5 V
IF = 4 mA
Low Level Enable
Current**
V
Input Forward
Voltage
VF
1.0
3
6
4
4
Temperature Co-
efficient of Forward
Voltage
∆VF/∆T
-1.25
mV/°C IF = 4 mA
A
Input Reverse
Breakdown Voltage
BVR
CIN
5
V
IR = 100 µA
4
Input Capacitance
60
pF
f = 1 MHz, VF = 0 V
*All typical values at TA = 25°C, VCC = 5 V
**Single Channel Products only (HCPL-261A/261N/061A/061N)
***Dual Channel Products only (HCPL-263A/263N/063A/063N)
8
Switching Specifications
Over recommended operating temperature (T = -40°C to +85°C) unless otherwise specified.
A
Parameter
Symbol
Min.
Typ.*
Max.
Units
Test Conditions
Fig.
Note
Input Current Threshold
High to Low
ITHL
1.5
3.0
mA V = 5.5 V, VO = 0.6 V,
IOCC>13 mA (Sinking)
7, 10
18
Propagation Delay
Time to High Output
Level
tPLH
52
53
11
100
100
ns
ns
ns
IF = 3.5 mA
CC = 5.0 V,
VE = Open,
CL =15pF,
RL = 350 Ω
9, 11, 4, 9,
12 18
V
Propagation Delay
Time to Low Output
Level
tPHL
9, 11, 4, 10,
12 18
Pulse Width Distortion
PWD
|tPHL - tPLH
45
60
9, 13 17, 18
|
Propagation Delay Skew
Output Rise Time
tPSK
tR
ns
ns
ns
ns
24 11, 18
9, 14 4, 18
9, 14 4, 18
42
12
19
Output Fall Time
tF
Propagation Delay
Time of Enable
from VEH to VEL
tEHL
IF = 3.5 mA
15,
16
12
VCC = 5.0 V,
VEL = 0 V, VEH =3 V,
CL =15 pF,
RL =350Ω
Propagation Delay
Time of Enable
from VEL to VEH
tELH
30
ns
15,
16
12
*All typical values at T = 25°C, VCC = 5 V.
A
Common Mode Transient Immunity Specifications, All values at T = 25°C
A
Parameter
Device
Symbol Min.
Typ. Max. Units
Test Conditions
Fig. Note
Output High
Level Common
Mode Transient HCPL-263A
HCPL-261A
HCPL-061A
|CMH|
1
5
kV/µs VCM = 50 V
VCC = 5.0 V,
RL = 350 Ω,
IF = 0 mA,
17 4, 13,
15, 18
Immunity
HCPL-063A
T = 25°C
VO(MIN) = 2 V
A
HCPL-261N
HCPL-061N
1
15
1
5
25
5
kV/µs V = 1000 V
CM
HCPL-263N
HCPL-063N
kV/µs
Using Avago
App Circuit
20 4, 13,
15
Output Low
Level Common
Mode Transient HCPL-263A
Immunity
HCPL-261A
HCPL-061A
|CML|
kV/µs VCM = 50 V
VCC = 5.0 V,
RL = 350 Ω,
IF = 3.5 mA,
VO(MAX) = 0.8 V
17 4, 14,
15, 18
HCPL-063A
T = 25°C
HCPL-261N
HCPL-061N
1
5
kV/µs V = 1000 V
A
CM
HCPL-263N
HCPL-063N
15
25
kV/µs
Using Avago
App Circuit
20 4, 14,
15
9
Package Characteristics
All Typicals at T = 25°C
A
Parameter
Sym.
Package*
Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output
Momentary With-
stand Voltage**
V
3750
V rms RH ≤ 50%,
t = 1 min.,
5, 6
ISO
OPT 020†
5000
5, 7
4, 8
T = 25°C
A
Input-Output
Resistance
RI-O
CI-O
II-I
1012
0.6
Ω
VI-O = 500 Vdc
Input-Output
Capacitance
pF
µA
f = 1 MHz,
4, 8
19
T = 25°C
A
Input-Input
Insulation
Leakage Current
Dual Channel
Dual Channel
0.005
RH ≤ 45%,
t = 5 s,
V = 500 V
I-I
Resistance
(Input-Input)
RI-I
CI-I
1011
Ω
19
19
Capacitance
(Input-Input)
Dual 8-pin DIP
Dual SO-8
0.03
0.25
pF
f = 1 MHz
*Ratings apply to all devices except otherwise noted in the Package column.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equip-
ment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
†For 8-pin DIP package devices (HCPL-261A/261N/263A/263N) only.
Notes:
1. Peaking circuits may be used which produce transient input currents up to 30 mA, 50 ns maximum pulse width, provided the average current
does not exceed 10 mA.
2. 1 minute maximum.
3. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
4. Each channel.
5. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
6. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in the
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 VRMS for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA).
8. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together.
9. The tPLH propagation delay is measured from the 1.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge of
the output pulse.
10. The tPHL propagation delay is measured from the 1.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge of
the output pulse.
11. Propagation delay skew (tPSK) is equal to the worst case difference in tPLH and/or tPHL that will be seen between any two units under the same
test conditions and operating temperature.
12. Single channel products only (HCPL-261A/261N/061A/061N).
13. Common mode transient immunity in a Logic High level is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that
the output will remain in a Logic High state (i.e., Vo > 2.0 V).
14. Common mode transient immunity in a Logic Low level is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that
the output will remain in a Logic Low state (i.e., VO < 0.8 V).
15. For sinusoidal voltages
(|dVCM/dt|)max = πfCM
V
.
16. Bypassing of the poweCrMs(Pu-Pp) ply line is required with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as shown in Figure 19. Total
lead length between both ends of the capacitor and the isolator pins should not exceed 10 mm.
17. Pulse Width Distortion (PWD) is defined as the difference between tPLH and tPHL for any given device.
18. No external pull up is required for a high logic state on the enable input of a single channel product. If the VE pin is not used, tying VE to V
CC
will result in improved CMR performance.
19. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel parts only.
10
15
10
100.0
80
V
V
V
V
= 5.5 V
= 5.5 V
= 2 V
CC
V
V
V
= 5 V
CC
O
E
F
= 2 V
E
OL
= 0.6 V
= 0.8 V
10.0
1.0
60
40
I
= 3.5 mA
F
T
= 85 C
A
T
T
= 40 C
= 25 C
A
A
5
0
0.1
20
0
I
+
F
V
F
–
0.01
-60 -40 -20
0
20 40 60 80 100
1.0
1.1
1.2
1.3
1.4
1.5
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – C
A
V
– FORWARD VOLTAGE – V
T
– TEMPERATURE – C
F
A
Figure 4. Typical high level output current vs. tem-
perature.
Figure 5. Low level output current vs. temperature.
Figure 6. Typical diode input forward current charac-
teristic.
0.6
5.0
4.0
V
V
= 5.5 V
CC
= 2 V
E
I
= 3.0 mA
F
0.5
I
I
= 16 mA
O
O
R
= 350 Ω
= 1 kΩ
L
= 12.8 mA
3.0
2.0
R
0.4
0.3
0.2
L
R
= 4 kW
L
I
I
= 9.6 mA
= 6.4 mA
O
O
1.0
0
-60 -40 -20
0
20 40 60 80 100
0
0.5
1.0
1.5
2.0
T
– TEMPERATURE – C
A
I
– FORWARD INPUT CURRENT – mA
F
Figure 7. Typical output voltage vs. forward input
current.
Figure 8. Typical low level output voltage vs. tem-
perature.
HCPL-261A/261N
+5 V
I
F
PULSE GEN.
= 50 Ω
1
2
3
4
V
8
7
6
5
CC
Z
O
t
= t = 5 ns
f
r
0.1 µF
R
L
BYPASS
OUTPUT V
INPUT
MONITORING
NODE
O
MONITORING
NODE
*C
L
R
M
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
V
I
= 3.5 mA
OH
F
90%
90%
INPUT
I
= 1.75 mA
I
F
F
t
10%
10%
t
PHL
PLH
V
OL
OUTPUT
V
O
1.5 V
t
t
fall
rise
Figure 9. Test circuit for tPHL and tPLH
.
11
2.0
1.5
120
120
TPLH
= 4 kΩ
TPLH
R = 4 kΩ
L
R
L
100
80
100
80
R
R
= 350 Ω
= 1 kΩ
L
L
TPLH
= 1 kΩ
1.0
0.5
0
R
TPLH
= 1 kΩ
L
60
60
R
L
TPLH
= 350 Ω
R
= 4 kΩ
L
TPHL
= 350 Ω, 1 kΩ, 4 kΩ
R
40
40
L
TPHL
= 350 Ω, 1 kΩ, 4 kΩ
R
L
R
L
V
V
= 5 V
CC
= 0.6 V
TPLH
= 350 kΩ
20
0
20
0
O
R
L
V
I
= 5 V
V
T
= 5 V
= 25 C
CC
= 3.5 mA
CC
A
F
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
0
2
4
6
8
10
12
T
– TEMPERATURE – C
A
T
– TEMPERATURE – C
I
– PULSE INPUT CURRENT – mA
A
F
Figure 12. Typical propagation delay vs. pulse input
current.
Figure 10. Typical input threshold current vs. tem-
perature.
Figure 11. Typical propagation delay vs. temperature.
60
160
V
I
= 5 V
t
t
CC
= 3.5 mA
rise
fall
R
= 4 kΩ
L
F
50
40
30
20
140
120
60
V
= 5 V
= 3.5 mA
CC
R
= 4 kΩ
L
I
F
R
R
= 1 kΩ
L
40
= 350 Ω
L
R
= 1 kΩ
L
10
0
20
0
R
= 350 Ω
L
R
= 350 Ω, 1 kΩ, 4 kΩ
20 40 60 80 100
L
0
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
T
– TEMPERATURE – C
T – TEMPERATURE – C
A
A
Figure 13. Typical pulse width distortion vs. tempera-
ture.
Figure 14. Typical rise and fall time vs. temperature.
12
PULSE GEN.
= 50 Ω
Z
O
t
= t = 5 ns
r
f
INPUT
V
E
MONITORING NODE
HCPL-261A/261N
V
+5 V
1
2
3
4
8
7
6
5
CC
3.5 mA
0.1 µF
BYPASS
R
L
I
F
OUTPUT V
O
MONITORING
NODE
120
*C
L
V
V
V
= 5 V
= 3 V
= 0 V
CC
EH
EL
GND
I
= 3.5 mA
F
90
60
t
, R = 4 kΩ
L
ELH
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
t
, R = 1 kΩ
ELH
L
3.0 V
1.5 V
INPUT
30
0
V
t
, R = 350 Ω
L
E
ELH
t
t
EHL
ELH
t
, R = 350 Ω, 1k Ω, 4 kΩ
L
EHL
OUTPUT
-60 -40 -20
0
20 40 60 80 100
V
O
1.5 V
T
– TEMPERATURE – C
A
Figure 15. Test circuit for tEHL and tELH
.
Figure 16. Typical enable propagation delay vs. temperature.
HCPL-261A/-261N/-061A/-061N Only.
HCPL-261A/261N
V
1
2
3
4
8
+5 V
CC
V
0.1 µF
BYPASS
CM
350
Ω
7
6
5
I
HCPL-261A/261N OPTION 060 ONLY
800
F
OUTPUT V
MONITORING
NODE
O
P
(mW)
A
B
S
700
600
500
400
300
200
100
0
I
(mA)
S
V
GND
FF
_
+
PULSE GEN.
O
Z
= 50 Ω
V
(PEAK)
CM
V
CM
0 V
5 V
SWITCH AT A:
SWITCH AT B:
I
= 0 mA
F
CM
CM
H
V
O
V
(min.)
(max.)
O
I
= 3.5 mA
F
V
O
V
O
0.5 V
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – C
L
T
S
Figure 17. Test circuit for common mode transient immunity and typical waveforms.
Figure 18. Thermal derating curve, dependence of safety limiting
value with case temperature per IEC/EN/DIN EN 60747-5-2.
13
SINGLE CHANNEL PRODUCTS
GND BUS (BACK)
Application Information
Common-Mode Rejection for HCPL-
261A/HCPL-261N Families:
V
BUS (FRONT)
N.C.
CC
Figure 20 shows the recommended
drive circuit for the HCPL-261N/-
261A for optimal common-mode
rejection performance. Two main
points to note are:
ENABLE
(IF USED)
0.1µF
OUTPUT 1
N.C.
N.C.
1. The enable pin is tied to VCC rather
than floating (this applies to
single-channel parts only).
ENABLE
(IF USED)
0.1µF
2. Two LED-current setting resistors
are used instead of one. This is
to balance ILED variation during
common-mode transients.
N.C.
OUTPUT 2
If the enable pin is left floating, it is
possible for common-mode tran-
sients to couple to the enable pin,
resulting in common-mode failure.
This failure mechanism only occurs
when the LED is on and the output
is in the Low State. It is identified as
occurring when the transient output
voltage rises above 0.8 V. Therefore,
the enable pin should be connected
to either VCC or logic-level high for
best common-mode performance
with the output low (CMRL). This
failure mechanism is only present
in single-channel parts (HCPL-261N,
-261A, -061N, -061A) which have the
enable function.
10 mm MAX. (SEE NOTE 16)
DUAL CHANNEL PRODUCTS
GND BUS (BACK)
V
BUS (FRONT)
CC
OUTPUT 1
OUTPUT 2
0.1µF
10 mm MAX. (SEE NOTE 16)
Also, common-mode transients can
capacitively couple from the LED an-
ode (or cathode) to the output-side
ground causing current to be shunt-
ed away from the LED (which can be
bad if the LED is on) or conversely
cause current to be injected into the
LED (bad if the LED is meant to be
off). Figure 21 shows the parasitic
capacitances which exists between
LED anode/cathode and output
ground (CLA and CLC). Also shown in
Figure 21 on the input side is an AC-
equivalent circuit.
Figure 19. Recommended printed circuit board layout.
HCPL-261A/261N
8
*
1
V
CC
V
V
CC+
0.01 µF
357
(MAX.)
Ω
350
Ω
2
7
6
357
(MAX.)
Ω
3
4
O
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
5
GND
SHIELD
*
GND1
GND2
*Higher CMR may be obtainable by connecting pins 1, 4 to input ground (Gnd1).
Figure 20. Recommended drive circuit for HCPL-261A/-261N families for high-CMR (similar for HCPL-263A/-263N).
14
Table 1 indicates the directions of ILP and ILN flow depend-
ing on the direction of the common-mode transient.
CMR with Other Drive Circuits
CMR performance with drive circuits other than that
shown in Figure 20 may be enhanced by following these
guidelines:
For transients occurring when the LED is on, common-
mode rejection (CMRL, since the output is in the “low”
state) depends upon the amount of LED current drive (IF).
For conditions where IF is close to the switching thresh-
old (ITH), CMRL also depends on the extent which ILP and ILN
balance each other. In other words, any condition where
common-mode transients cause a momentary decrease
in IF (i.e. when dVCM/dt>0 and |IFP| > |IFN|, referring to Table
1) will cause common-mode failure for transients which
are fast enough.
1. Use of drive circuits where current is shunted from the
LED in the LED “off” state (as shown in Figures 22 and
23). This is beneficial for good CMRH.
2. Use of IFH > 3.5 mA. This is good for high CMRL.
Using any one of the drive circuits in Figures 22-24 with IF =
10 mA will result in a typical CMR of 8 kV/µs for the HCPL-
261N family, as long as the PC board layout practices are
followed. Figure 22 shows a circuit which can be used with
any totem-pole-output TTL/LSTTL/HCMOS logic gate. The
buffer PNP transistor allows the circuit to be used with
logic devices which have low current-sinking capability.
It also helps maintain the driving-gate power-supply cur-
rent at a constant level to minimize ground shifting for
other devices connected to the input-supply ground.
Likewise for common-mode transients which occur when
the LED is off (i.e. CMRH, since the output is “high”), if an
imbalance between ILP and ILN results in a transient IF equal
to or greater than the switching threshold of the optocou-
pler, the transient “signal” may cause the output to spike
below 2 V (which constitutes a CMRH failure).
By using the recommended circuit in Figure 20, good CMR
can be achieved. (In the case of the -261N families, a mini-
mum CMR of 15 kV/µs is guaranteed using this circuit.)
The balanced ILED-setting resistors help equalize ILP and
ILN to reduce the amount by which ILED is modulated from
transient coupling through CLA and CLC.
When using an open-collector TTL or open-drain CMOS
logic gate, the circuit in Figure 23 may be used. When
using a CMOS gate to drive the optocoupler, the circuit
shown in Figure 24 may be used. The diode in parallel with
the RLED speeds the turn-off of the optocoupler LED.
1
2
8
7
V
+
CC
1/2 R
1/2 R
0.01 µF
LED
350 Ω
I
LP
LED
C
I
LA
LN
3
4
6
5
V
O
15 pF
C
LC
GND
SHIELD
+
–
V
CM
Figure 21. AC equivalent circuit for HCPL-261X.
V
CC
HCPL-261X
1
2
420 Ω
(MAX)
2N3906
(ANY PNP)
74L504
(ANY
LED
TTL/CMOS
GATE)
3
4
Figure 22. TTL interface circuit for the HCPL-261A/-261N families.
15
V
V
CC
CC
HCPL-261X
HCPL-261A/261N
1
2
1N4148
1
2
820 Ω
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
750 Ω
74HC04
(OR ANY
TOTEM-POLE
OUTPUT LOGIC
GATE)
LED
LED
3
4
3
4
LOGIC GATE)
Figure 23. TTL open-collector/open drain gate drive circuit for HCPL-261A/-
261N families.
Figure 24. CMOS gate drive circuit for HCPL-261A/-261N families.
Table 1. Effects of Common Mode Pulse Direction on Transient ILED
If |ILP| < |ILN|,
LED IF Current
Is Momentarily:
If |ILP| > |ILN|,
LED IF Current
Is Momentarily:
If dV /dt Is:
then ILP Flows:
and ILN Flows:
CM
positive (>0)
away from LED
anode through CLA
toward LED
away from LED
cathode through CLC
toward LED
increased
decreased
increased
negative (<0)
decreased
anode through CLA
cathode through CLC
tion of signals on parallel data lines is a concern. If the par-
allel data is being sent through a group of optocouplers,
differences in propagation delays will cause the data to ar-
rive at the outputs of the optocouplers at different times.
If this difference in propagation delay is large enough it
will determine the maximum rate at which parallel data
can be sent through the optocouplers.
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation delay is a figure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (tPLH) is the amount of
time required for an input signal to propagate to the out-
put, causing the output to change from low to high. Simi-
larly, the propagation delay from high to low (tPHL) is the
amount of time required for the input signal to propagate
to the output, causing the output to change from high to
low (see Figure 9).
Propagation delay skew is defined as the difference be-
tween the minimum and maximum propagation delays,
either tPLH or tPHL, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same drive current, supply voltage, output load, and oper-
ating temperature). As illustrated in Figure 25, if the inputs
of a group of optocouplers are switched either ON or OFF
at the same time, tPSK is the difference between the short-
est propagation delay, either tPLH or tPHL, and the longest
Pulse-width distortion (PWD) results when tPLH and tPHL dif-
fer in value. PWD is defined as the difference between tPLH
and tPHL and often determines the maximum data rate ca-
pability of a transmission system. PWD can be expressed
in percent by dividing the PWD (in ns) by the minimum
pulse width (in ns) being transmitted. Typically, PWD on
the order of 20-30% of the minimum pulse width is tolera-
ble; the exact figure depends on the particular application
(RS232, RS422, T-1, etc.).
propagation delay, either tPLH or tPHL
.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 26 is the timing
diagram of a typical parallel data application with both
the clock and the data lines being sent through optocou-
plers.
Propagation delay skew, tPSK, is an important parameter to
consider in parallel data applications where synchroniza-
The figure shows data and clock signals at the inputs and
outputs of the optocouplers. To obtain the maximum data
transmission rate, both edges of the clock signal are being
used to clock the data; if only one edge were used, the
clock signal would need to be twice as fast.
before the clock signal has arrived. From these considera-
tions, the absolute minimum pulse width that can be sent
through optocouplers in a parallel application is twice tPSK
.
A cautious design should use a slightly longer pulse width
to ensure that any additional uncertainty in the rest of the
circuit does not cause a problem.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op- The tPSK specified optocouplers offer the advantages of
tocoupler. Figure 26 shows that there will be uncertainty in guaranteed specifications for propagation delays, pulse-
both the data and the clock lines. It is important that these width distortion, and propagation delay skew over the
two areas of uncertainty not overlap, otherwise the clock recommended temperature, input current, and power
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
supply ranges.
I
F
50%
1.5 V
V
O
TPHL
TPLH
I
50%
F
V
1.5 V
O
t
PSK
Figure 25. Illustration of propagation delay skew – tPSK
.
DATA
INPUTS
CLOCK
DATA
OUTPUTS
t
PSK
CLOCK
t
PSK
Figure 26. Parallel data transmission example.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes 5989-2129EN
AV01-0561EN May 17, 2007
17
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