HCPL-0720-060 [AVAGO]
暂无描述;
| 型号： | HCPL-0720-060 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 暂无描述 光电 输出元件 |
| 文件： | 总18页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-0720, HCPL-7720, HCPL-0721 and HCPL-7721
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
• +5 V CMOS compatibility
• 20 ns maximum prop. delay skew
• High speed: 25 MBd
• 40 ns max. prop. delay
• 10 kV/µs minimum common mode rejection
• –40 to 85°C temperature range
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-772X or HCPL-072X optocouplers
utilize the latest CMOS IC technology to achieve out-
standing performance with very low power consump-
tion. The HCPL-772X/072X require only two bypass ca-
pacitors for complete CMOS compatability.
Basic building blocks of the HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver IC
which supplies current to the LED. The detector IC incor-
porates an integrated photodiode, a high-speed tran-
simpedance amplifier, and a voltage comparator with an
output driver.
• Safety and regulatory approvals
UL recognized
– 3750 Vrms for 1 min. per UL 1577
– 5000 Vrms for 1 min. per UL 1577
(for HCPL-772X option 020)
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– VIORM = 630 Vpeak for HCPL-772X option 060
– VIORM = 567 Vpeak for HCPL-072X option 060
Functional Diagram
**V
1
2
8
7
V
**
DD2
DD1
Applications
• Digital fieldbus isolation: CC-Link, DeviceNet, Profi-
bus, SDS
V
NC*
I
I
• AC plasma display panel level shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
O
3
4
6
5
*
V
O
LED1
GND
GND
2
1
SHIELD
*
Pin 3 is the anode of the internal LED and must be left unconnected
for guaranteed data sheet performance. Pin 7 is not connected
internally.
** A 0.1 µF bypass capacitor must be connected between pins 1 and
4, and 5 and 8.
TRUTH TABLE
POSITIVE LOGIC
VI
H
L
LED1
OFF
ON
Vo OUTPUT
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
8-Pin DIP
(300 Mil)
Small Outline
SO-8
Data Rate
25 MB
PWD
6 ns
8 ns
HCPL-7721
HCPL-7720
HCPL-0721
HCPL-0720
25 MB
Ordering Information
HCPL-0720, HCPL-0721, HCPL-7720 and HCPL-7721 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
Number
RoHS
non RoHS
Surface Gull
Tape
UL 5000 Vrms
/
IEC/EN/DIN
Compliant Compliant Package
Mount
Wing & Reel 1 Minute rating EN 60747-5-5 Quantity
-000E
-300E
-500E
no option
#300
50 per tube
X
X
X
X
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
#500
X
X
HCPL-7720 -020E
HCPL-7721 -320E
-520E
-020
300 mil
DIP-8
X
X
X
-320
X
X
X
X
-520
-060E
#060
X
X
X
-360E
#360
X
X
X
X
X
X
X
X
X
X
X
X
-560E
#560
X
X
X
-000E
no option
#500
HCPL-0720 -500E
HCPL-0721 -060E
-560E
SO-8
#060
X
X
#560
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7720-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-5 Safety Approval and RoHS compliant.
Example 2:
HCPL-0721 to order product of Small Outline SO-8 package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
2
Package Outline Drawing
HCPL-772X 8-Pin DIP Package
9.65 ꢀ.ꢁ5
(ꢀ.38ꢀ ꢀ.ꢀ0ꢀꢂ
7.6ꢁ ꢀ.ꢁ5
(ꢀ.3ꢀꢀ ꢀ.ꢀ0ꢀꢂ
OPTION ꢀ6ꢀ CODE*
DATE CODE
TYPE NUMBER
8
7
6
5
6.35 ꢀ.ꢁ5
(ꢀ.ꢁ5ꢀ ꢀ.ꢀ0ꢀꢂ
A XXXXV
YYWW
0
ꢁ
3
4
0.78 (ꢀ.ꢀ7ꢀꢂ MAX.
0.09 (ꢀ.ꢀ47ꢂ MAX.
+ ꢀ.ꢀ76
- ꢀ.ꢀ50
ꢀ.ꢁ54
5° TYP.
+ ꢀ.ꢀꢀ3ꢂ
- ꢀ.ꢀꢀꢁꢂ
(ꢀ.ꢀ0ꢀ
3.56 ꢀ.03
(ꢀ.04ꢀ ꢀ.ꢀꢀ5ꢂ
4.7ꢀ (ꢀ.085ꢂ MAX.
ꢀ.50 (ꢀ.ꢀꢁꢀꢂ MIN.
ꢁ.9ꢁ (ꢀ.005ꢂ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢂ.
*OPTION 3ꢀꢀ AND 5ꢀꢀ NOT MARKED.
0.ꢀ8ꢀ ꢀ.3ꢁꢀ
(ꢀ.ꢀ43 ꢀ.ꢀ03ꢂ
ꢀ.65 (ꢀ.ꢀꢁ5ꢂ MAX.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.ꢁ5 mm (0ꢀ milsꢂ MAX.
ꢁ.54 ꢀ.ꢁ5
(ꢀ.0ꢀꢀ ꢀ.ꢀ0ꢀꢂ
3
Package Outline Drawing
HCPL-772X Package with Gull Wing Surface Mount Option 300
LAND PATTERN RECOMMENDATION
ꢁ.0ꢁ6 (0.040ꢂ
9.65 0.ꢀ5
(0.380 0.0ꢁ0ꢂ
6
5
8
ꢁ
7
6.350 0.ꢀ5
(0.ꢀ50 0.0ꢁ0ꢂ
ꢁ0.9 (0.430ꢂ
ꢀ.0 (0.080ꢂ
ꢀ
3
4
ꢁ.ꢀ7 (0.050ꢂ
9.65 0.ꢀ5
ꢁ.780
(0.070ꢂ
MAX.
(0.380 0.0ꢁ0ꢂ
ꢁ.ꢁ9
(0.047ꢂ
MAX.
7.6ꢀ 0.ꢀ5
(0.300 0.0ꢁ0ꢂ
+ 0.076
0.ꢀ54
- 0.05ꢁ
3.56 0.ꢁ3
(0.ꢁ40 0.005ꢂ
+ 0.003ꢂ
- 0.00ꢀꢂ
(0.0ꢁ0
ꢁ.080 0.3ꢀ0
(0.043 0.0ꢁ3ꢂ
0.635 0.ꢀ5
(0.0ꢀ5 0.0ꢁ0ꢂ
ꢁꢀ° NOM.
0.635 0.ꢁ30
(0.0ꢀ5 0.005ꢂ
ꢀ.54
(0.ꢁ00ꢂ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢂ.
LEAD COPLANARITY = 0.ꢁ0 mm (0.004 INCHESꢂ.
NOTE: FLOATING LEAD PROTRUSION IS 0.ꢀ5 mm (ꢁ0 milsꢂ MAX.
Package Outline Drawing
HCPL-072X Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ꢀ.2ꢀ3
(ꢀ.236 ꢀ.ꢀꢀ8ꢁ
XXXV
YWW
3.937 ꢀ.127
TYPE NUMBER
(LAST 3 DIGITSꢁ
DATE CODE
7.49 (ꢀ.295ꢁ
(ꢀ.155 ꢀ.ꢀꢀ5ꢁ
3
PIN ONE
1.9 (ꢀ.ꢀ75ꢁ
ꢀ.4ꢀ6 ꢀ.ꢀ76
(ꢀ.ꢀ16 ꢀ.ꢀꢀ3ꢁ
1.27ꢀ
(ꢀ.ꢀ5ꢀꢁ
BSC
ꢀ.64 (ꢀ.ꢀ25ꢁ
ꢀ.432
(ꢀ.ꢀ17ꢁ
*
7°
5.ꢀ8ꢀ ꢀ.127
(ꢀ.2ꢀꢀ ꢀ.ꢀꢀ5ꢁ
45° X
3.175 ꢀ.127
(ꢀ.125 ꢀ.ꢀꢀ5ꢁ
ꢀ ~ 7°
ꢀ.228 ꢀ.ꢀ25
(ꢀ.ꢀꢀ9 ꢀ.ꢀꢀ1ꢁ
1.524
(ꢀ.ꢀ6ꢀꢁ
ꢀ.2ꢀ3 ꢀ.1ꢀ2
(ꢀ.ꢀꢀ8 ꢀ.ꢀꢀ4ꢁ
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASHꢁ
5.2ꢀ7 ꢀ.254 (ꢀ.2ꢀ5 ꢀ.ꢀ1ꢀꢁ
*
ꢀ.3ꢀ5
(ꢀ.ꢀ12ꢁ
MIN.
DIMENSIONS IN MILLIMETERS (INCHESꢁ.
LEAD COPLANARITY = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 INCHESꢁ MAX.
OPTION NUMBER 5ꢀꢀ NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS ꢀ.15 mm (6 milsꢁ MAX.
4
Solder Reflow Thermal Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-
Halide Flux should be used.
Regulatory Information
The HCPL-772X/072X have been approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-5
Insulation and Safety Related Specifications
Value
Parameter
Symbol
772X
072X
Units
Conditions
Minimum External Air
Gap (Clearance)
L(I01)
7.1
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(I02)
CTI
7.4
4.8
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08
0.08
Insulation thickness between emitter and
detector; also known as distance through
insulation.
Tracking Resistance
(Comparative Tracking
Index)
≥175
IIIa
≥175
IIIa
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group
(DIN VDE 0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance the surface of a printed circuit board between the solder
inherent to the optocoupler component itself. These fillets of the input and output leads must be considered.
dimensions are needed as a starting point for the equip- There are recommended techniques such as grooves
ment designer when determining the circuit insulation and ribs which may be used on a printed circuit board to
requirements. However, once mounted on a printed achieve desired creepage and clearances. Creepage and
circuit board, minimum creepage and clearance require- clearance distances will also change depending on fac-
ments must be met as specified for individual equipment tors such as pollution degree and insulation level.
standards. For creepage, the shortest distance path along
5
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060)
Characteristic
HCPL-7720
HCPL-7721
HCPL-0720
HCPL-0721
Description
Symbol
Unit
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I-IV
I-IV
I-IV
I-IV
I-III
I-III
Climatic Classification
55/85/21
2
55/85/21
2
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
V
IORM
630
567
Vpeak
Vpeak
Input-to-Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
VPR
1181
1063
Input-to-Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
VPR
1008
8000
907
Vpeak
Highest Allowable Overvoltage
VIOTM
6000
Vpeak
(Transient Overvoltage, tini = 60 sec)
Safety Limiting Values –
maximum values allowed in the event of a failure
Case Temperature
TS
175
230
600
150
150
600
°C
mA
mW
Input Current
Output Power
IS,INPUT
PS,OUTPUT
Insulation Resistance at TS, V10 = 500 V
RIO
≥109
≥109
Ω
*
Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/
EN/DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
Note:
These optocouplers are suitable for “safe electrical isolation”only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
The surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Symbol
TS
Min.
–55
–40
0
Max.
125
Units
°C
Figure
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltages
TA
+85
°C
VDD1, VDD2
6.0
Volts
Volts
Volts
mA
Input Voltage
V
I
–0.5
–0.5
VDD1 +0.5
VDD2 +0.5
10
Output Voltage
VO
IO
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Symbol
TA
Min.
–40
4.5
Max.
+85
5.5
Units
°C
V
Figure
Supply Voltages
VDD1, VDD2
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
V
2.0
VDD1
0.8
V
1, 2
IH
V
IL
0.0
V
tr, tf
1.0
ms
6
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25 °C, VDD1 = VDD2 = +5 V.
Parameter
Symbol
Min.
Typ.
6.0
1.5
Max.
10.0
3.0
Units
mA
mA
mA
Test Conditions
Fig.
Note
DC Specifications
Logic Low Input
Supply Current
Logic High Input
Supply Current
Output Supply Current
IDD1L
VI = 0 V
2
IDD1H
VI = VDD1
IDD2L
IDD2H
II
5.5
7.0
9.0
9.0
10
Input Current
Logic High Output
Voltage
Logic Low Output
Voltage
–10
4.4
4.0
A
µ
V
VOH
5.0
4.8
0
IO = -20 A, V = V
1, 2
µ
I
IH
IO = -4 mA, VI = VIH
IO = 20 A, V = V
VOL
0.1
0.1
1.0
V
V
µ
I
IL
I = 400 A, V = V
IL
µ
O
I
0.5
20
23
IO = 4 mA, VI = VIL
Switching Specifications
Propagation Delay Time
to Logic Low Output
Propagation Delay Time
to Logic High Output
Pulse Width
tPHL
tPLH
PW
40
40
ns
ns
CL = 15 pF
CMOS Signal Levels
3, 6
3
40
ns
Data Rate
Pulse Width Distortion
25
6
8
MBd
ns
ns
PWD
7721/0721
7720/0720
3
3
7
4
5
|tPHL - tPLH
|
Propagation Delay Skew
Output Rise Time
(10 - 90%)
Output Fall Time
(90 - 10%)
tPSK
tR
20
9
ns
ns
tF
8
Common Mode
Transient Immunity at
Logic High Output
Common Mode
Transient Immunity at
Logic Low Output
Input Dynamic Power
Dissipation
|CMH|
10
10
20
kV/ s
VI = VDD1, VO >
6
7
µ
0.8 VDD1
,
VCM = 1000 V
VI = 0 V, VO > 0.8 V,
VCM = 1000 V
|CML|
CPD1
CPD2
20
60
10
pF
Capacitance
Output Dynamic Power
Dissipation
Capacitance
7
Package Characteristics
Parameter
Input-Output Momentary
Symbol Min.
Typ. Max. Units
Test Conditions
RH ≤50%,
t = 1 min.,
TA = 25°C
Fig.
Note
8, 9,
10
072X
772X
Option 020
V
3750
3750
5000
Vrms
ISO
Withstand Voltage
Resistance
(Input-Output)
Capacitance
RI-O
CI-O
1012
0.6
Ω
V
I-O = 500 Vdc
8
pF
f = 1 MHz
(Input-Output)
Input Capacitance
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
CI
θjci
3.0
11
-772X
-072X
-772X
-072X
145
160
140
135
°C/W
mW
Thermocouple
located at center
underside of package
θjco
PPD
150
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee functionality.
2. The LED is ON when VI is low and OFF when VI is high.
3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
4. PWD is defined as |tPHL - tPLH|. %PWD(percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz.
8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-072X is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detection
current limit, II-O ≤5 µA). Each HCPL-772X is proof tested by applying an insulation test voltage ≥4500 Vrms for 1 second (leakage detection
current limit. II-O ≤ 5 µA.)
10. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 “Optocou-
pler Input-Output Endurance Voltage.”
11. CI is the capacitance measured at pin 2 (VI).
2.2
29
5
0 °C
25 °C
85 °C
2.1
2.0
1.9
27
25
23
0 °C
25 °C
85 °C
4
3
2
1
0
T
T
PLH
PHL
21
19
17
15
1.8
1.7
1.6
0
1
2
3
4
5
4.5
4.75
5
5.25
5.5
0
10 20 30 40 50 60 70 80
(C)
V (V)
V
(V)
T
A
I
DD1
Figure 1. Typical output voltage vs. input volt-
age
Figure 2. Typical input voltage switching thresh-
old vs. input supply voltage
Figure 3. Typical propagation delays vs. tem-
perature
8
4
3
2
11
10
7
6
5
4
3
2
9
8
1
0
0
20
40
60
80
0
20
40
60
80
0
20
40
60
80
T
(C)
T
(C)
T (C)
A
A
A
Figure 4. Typical pulse width distortion vs.
temperature
Figure 5. Typical rise time vs. temperature
Figure 6. Typical fall time vs. temperature
29
27
25
6
5
4
3
T
PHL
23
21
19
17
15
T
PLH
2
1
0
15 20 25 30 35 40 45 50
15 20 25 30 35 40 45 50
C (pF)
C (pF)
I
I
Figure 8. Typical pulse width distortion vs.
output load capacitance
Figure 7. Typical propagation delays vs. output
load capacitance
STANDARD 8 PIN DIP PRODUCT
800
SURFACE MOUNT SO8 PRODUCT
800
P
I
(mW)
P
I
(mW)
S
S
700
600
500
400
300
700
600
500
400
300
(mA)
(mA)
S
S
(230)
200
200
(150)
100
100
0
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
T
T
A
A
Figure 9. Thermal derating curve, dependence of safety limiting value with case temperature per
IEC/EN/DIN EN 60747-5-5.
9
Application Information
Bypassing and PC Board Layout
The HCPL-772X/072X optocouplers are extremely easy to use. No external interface circuitry is required because the
HCPL-772X/072X use high-speed CMOS IC technology allowing CMOS logic to be connected directly to the inputs
and outputs.
As shown in Figure 10, the only external components required for proper operation are two bypass capacitors. Ca-
pacitor values should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of
the capacitor and the power-supply pins should not exceed 20 mm. Figure 11 illustrates the recommended printed
circuit board layout for the HPCL-772X/072X.
V
V
8
7
6
5
DD1
1
2
3
4
DD2
C1
C2
V
I
NC
NC
V
O
GND
GND
1
2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 10. Recommended printed circuit board layout.
V
DD1
V
V
DD2
V
I
C1
C2
O
GND
GND
2
1
C1, C2 = 0.01 µF TO 0.1 µF
Figure 11. Recommended printed circuit board layout
Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew
Propagation Delay is a figure of merit that describes how quickly a logic signal propagates through a system. The
propagation delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the
output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the
amount of time required for the input signal to propagate to the output, causing the output to change from high to
low. See Figure12.
INPUT
5 V CMOS
0 V
V
50%
I
t
t
PHL
PLH
V
OH
2.5 V CMOS
OUTPUT
90%
90%
V
10%
10%
O
V
OL
Figure 12.
10
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maximum data
Propagation delay skew is defined as the difference be-
tween the minimum and maximum propagation delays,
rate capability of a transmission system. PWD can be either tPLH or tPHL, for any given group of optocouplers
expressed in percent by dividing the PWD (in ns) by the
which are operating under the same conditions (i.e., the
minimum pulse width (in ns) being transmitted. Typical- same drive current, supply voltage, output load, and op-
ly, PWD on the order of 20 - 30% of the minimum pulse erating temperature). As illustrated in Figure 13, if the in-
width is tolerable.
puts of a group of optocouplers are switched either ON
or OFF at the same time, tPSK is the difference between
the shortest propagation delay, either tPLH or tPHL, and
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchro-
nization of signals on parallel data lines is a concern. If
the longest propagation delay, either tPLH or tPHL
.
the parallel data is being sent through a group of opto- As mentioned earlier, tPSK can determine the maximum
couplers, differences in propagation delays will cause the parallel data transmission rate. Figure 14 is the timing
data to arrive at the outputs of the optocouplers at differ- diagram of a typical parallel data application with both
ent times. If this difference in propagation delay is large the clock and data lines being sent through the opto-
enough it will determine the maximum rate at which couplers. The figure shows data and clock signals at the
parallel data can be sent through the optocouplers.
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
V
I
50%
DATA
INPUTS
CLOCK
2.5 V,
CMOS
V
O
t
PSK
V
50%
I
DATA
OUTPUTS
t
PSK
CLOCK
2.5 V,
V
O
CMOS
t
PSK
Figure 13. Propagation delay skew waveform.
Figure 14. Parallel data transmission example.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an op-
tocoupler. Figure14 shows that there will be uncertainty
in both the data and clock lines. It is important that these
two areas of uncertainty not overlap, otherwise the clock
signal might arrive before all of the data outputs have
settled, or some of the data outputs may start to change
before the clock signal has arrived. From these consider-
ations,theabsoluteminimumpulsewidththatcanbesent
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-772X/072X optocouplers offer the advantage
of guaranteed specifications for propagation delays,
pulse-width distortion, and propagation delay skew
over the recommended temperature and power supply
ranges.
throughoptocouplersinaparallelapplicationistwicetPSK
.
11
Digital Field Bus Communication Networks
now receive multiple readings from field devices (sen-
sors, actuators, etc.) in addition to diagnostic informa-
tion.
To date, despite its many drawbacks, the 4 - 20 mA ana-
log current loop has been the most widely accepted
standard for implementing process control systems. In
today’s manufacturing environment, however, automat-
ed systems are expected to help manage the process,
not merely monitor it. With the advent of digital field bus
communication networks such as CC-Link, DeviceNet,
PROFIBUS, and Smart Distributed Systems (SDS), gone
are the days of constrained information. Controllers can
The physical model for each of these digital field bus
communication networks is very similar as shown in
Figure 15. Each includes one or more buses, an interface
unit, optical isolation, transceiver, and sensing and/or ac-
tuating devices.
CONTROLLER
BUS
INTERFACE
OPTICAL
ISOLATION
TRANSCEIVER
FIELD BUS
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
OPTICAL
ISOLATION
OPTICAL
ISOLATION
OPTICAL
ISOLATION
OPTICAL
ISOLATION
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
XXXXXX
YYY
SENSOR
DEVICE
CONFIGURATION
MOTOR
CONTROLLER
MOTOR
STARTER
Figure 15. Typical field bus communication physical model
12
Optical Isolation for Field Bus Networks
These components could include such things as devices
with serial ports, parallel ports, RS-232 and RS-485 type
ports. As shown in Figure 16, power from the network is
used only for the transceiver and input (network) side of
the optocouplers.
To recognize the full benefits of these networks, Avago
optocouplers are recommended to provide galvanic iso-
lation. As network communication is bi-directional (in-
volving receiving data from and transmitting data onto
the network), two Avago optocouplers are needed. By
providing galvanic isolation, data integrity is retained
via noise reduction and the elimination of false signals.
In addition, the network receives maximum protection
from power system faults and ground loops.
Isolation of nodes connected to any of the three types of
digital field bus networks is best achieved by using the
HCPL-772X/072X optocouplers. For each network, the
HCPL-772X/072X satisify the critical propagation delay
and pulse width distortion requirements over the tem-
perature range of 0 °C to +85 °C, and power supply volt-
age range of 4.5 V to5.5V.
Within an isolated node, such as the DeviceNet Node
shown in Figure 16, some of the node’s components are
referenced to a ground other than V- of the network.
AC LINE
NODE/APP SPECIFIC
LOCAL
NODE
SUPPLY
µP/CAN
GALVANIC
ISOLATION
BOUNDARY
HCPL
772x/072x
HCPL
772x/072x
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
Figure 16. Typical DeviceNet Node
13
Implementing CC-Link with the HCPL-772X/072X
Power Supplies and Bypassing
CC-Link (Control and Communication Link) is developed
The recommended CC-Link circuit is shown in Figure
to merge control and information in the low-level net- 17. Since the HCPL-772X/072X are fully compatible
work (field network) by PCs, thereby making the mul- with CMOS logic level signals, the optocoupler is con-
tivendor environment a reality. It has data control and nected directly to the transceiver. Two bypass capacitors
message-exchange function, as well as bit control func- (with values between 0.01 µF and 0.1 µF) are required
tion, and operates at the speed up to 10 Mbps.
and should be located as close as possible to the input
and output power supply pins of the HCPL-772X/072X.
For each capacitor, the total lead length between both
ends of capacitor and the power supply pins should not
exceed 20 mm. The bypass capacitors are required be-
cause of the high speed digital nature of the signals in-
side the optocoupler.
V
DD2
(5 V)
V
DD1
HCPL-7720#500
(5 V)
SN75ALS181NS
FIL
V
CC
CC
V
V
V
DD2
DD1
I
10 K
0.1 µ
DA
DB
DG
A
V
V
O
R
RE
RD1
0.1 µ
0.1 µ
0.1 µ
0.1 µ
B
GND
GND
1
DE
D
Y
Z
GND
GND
1
2
GND
GND
HCPL-7720#500
SLD
FG
V
V
V
DD1
DD2
O
V
I
SD
0.1 µ
GND
GND
HCPL-2611#560
V
V
NC
OE
DD
1 K
+
–
V
O
MPU
BOARD
OUTPUT
HC14
390
GND
HC14
NC
10 K
HCPL-2611#560
V
V
NC
OE
DD
1 K
+
–
V
O
SDGATEON
HC14
390
GND
HC14
10 K
NC
Figure 17. Recommended CC-Link application circuit
14
Implementing DeviceNet and SDS with the HCPL-772X/072X
Isolated Node Powered by the Network
With transmission rates up to 1 Mbit/s, both DeviceNet
and SDS are based upon the same broadcast-oriented,
communications protocol — the Controller Area Network
This type of node is very flexible and as can be seen in
Figure 18, is regarded as “isolated” because not all of its
components have the same ground reference. Yet, all
(CAN). Three types of isolated nodes are recommended components are still powered by the network. This node
for use on these networks: Isolated Node Powered by
the Network (Figure 18), Isolated Node with Transceiver
Powered by the Network (Figure 19), and Isolated Node
Providing Power to the Network (Figure20).
contains two regulators: one is isolated and powers the
CAN controller, node-specific application and isolated
(node) side of the two optocouplers while the other is
non-isolated. The non-isolated regulator supplies the
transceiver and the non-isolated (network) half of the
two optocouplers.
NODE/APP SPECIFIC
µP/CAN
ISOLATED
GALVANIC
SWITCHING
ISOLATION
POWER
HCPL
772x/072x
HCPL
772x/072x
BOUNDARY
SUPPLY
REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
Figure 18. Isolated node powered by the network.
*Bus V+ Sensing
Isolated Node with Transceiver Powered by the Network
It is suggested that the Bus V+ sense block shown in Fig-
ure 19 be implemented. A locally powered node with an
un-powered isolated Physical Layer will accumulate er-
rors and become bus-off if it attempts to transmit. The
Bus V+ sense signal would be used to change the BOI at-
tribute of the DeviceNet Object to the “auto-reset” (01)
value. Refer to Volume 1, Section 5.5.3. This would cause
the node to continually reset until bus power was detect-
ed. Once power was detected, the BOI attribute would
be returned to the “hold in bus-off” (00) value. The BOI
attribute should not be left in the “auto-reset” (01) value
since this defeats the jabber protection capability of the
CAN error confinement. Any inexpensive low frequency
optical isolator can be used to implement this feature.
Figure19 shows a node powered by both the network
and another source. In this case, the transceiver and iso-
lated (network) side of the two optocouplers are pow-
ered by the network. The rest of the node is powered by
the AC line which is very beneficial when an application
requires a significant amount of power. This method is
also desirable as it does not heavily load the network.
More importantly, the unique “dual-inverting” design of
the HCPL-772X/072X ensure the network will not “lock-
up”if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (VDD1) to the
HCPL-772X/072X located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-772X/
072X output voltage (VO) go HIGH.
15
AC LINE
NON ISO
5 V
NODE/APP SPECIFIC
µP/CAN
GALVANIC
ISOLATION
BOUNDARY
HCPL
772x/072x
HCPL
772x/072x
*HCPL
772x/072x
REG.
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
NETWORK
POWER
SUPPLY
* OPTIONAL FOR BUS V + SENSE
Figure 19. Isolated node with transceiver powered by the network.
Isolated Node Providing Power to the Network
More importantly, the unique “dual-inverting” design of
the HCPL-772X/072X ensure the network will not “lock-
up”if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (VDD1) to the
HCPL-772X/072X located in the transmit path is eliminat-
ed, a RECESSIVE bus state is ensured as the HCPL-772X/
072X output voltage (VO) go HIGH.
Figure 20 shows a node providing power to the network.
The AC line powers a regulator which provides 5 V local-
ly. The AC line also powers a 24 V isolated supply, which
powers the network, and another 5 V regulator, which, in
turn, powers the transceiver and isolated (network) side
of the two optocouplers. This method is recommended
when there is a limited number of devices on the net-
work, which do not require much power, thus eliminat-
ing the need for separate power supplies.
AC LINE
DeviceNet Node
NODE/APP SPECIFIC
5 V REG.
5 V REG.
µP/CAN
ISOLATED
GALVANIC
SWITCHING
ISOLATION
POWER
HCPL
772x/072x
HCPL
772x/072x
BOUNDARY
SUPPLY
TRANSCEIVER
DRAIN/SHIELD
SIGNAL
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
POWER
Figure 20. Isolated node providing power to the network.
16
Power Supplies and Bypassing
The recommended DeviceNet application circuit is
shown in Figure 21. Since the HCPL-772X/072X are fully
compatible with CMOS logic level signals, the optocoup-
to the input and output power-supply pins of the HCPL-
772X/072X. For each capacitor, the total lead length be-
tween both ends of the capacitor and the power supply
ler is connected directly to the CAN transceiver. Two by- pins should not exceed 20 mm. The bypass capacitors
pass capacitors (with values between 0.01 and 0.1 µF) are required because of the high-speed digital nature of
are required and should be located as close as possible
the signals inside the optocoupler.
GALVANIC
ISOLATION
BOUNDARY
ISO 5 V
5 V
LINEAR OR
SWITCHING
REGULATOR
+
V
V
V
DD2
1
2
8
7
DD1
IN
+
0.01
µF
TX0
HCPL-772x
HCPL-072x
V
CC
5 V+
TxD
Rs
V
O
0.01 µF
3
4
6
5
CANH
4 CAN+
3 SHIELD
2 CAN–
1 V–
82C250
GND
GND
+
1
2
2
C4
0.01 µF
CANL
REF
GND
VREF
RXD
GND
GND
GND
V
5
6
4
3
1
C1
0.01 µF
500 V
0.01
µF
D1
30 V
R1
1 M
RX0
V
O
HCPL-772x
HCPL-072x
0.01 µF
7
8
2
1
IN
V
V
DD1
DD2
ISO 5 V
5 V
Figure 21. Recommended DeviceNet application circuit
Implementing PROFIBUS with the HCPL-772X/072X
PROFIBUS USER:
CONTROL STATION
An acronym for Process Fieldbus, PROFIBUS is essentially
a twisted-pair serial link very similar to RS-485 capable
of achieving high-speed communication up to 12MBd.
As shown in Figure 22, a PROFIBUS Controller (PBC) es-
tablishes the connection of a field automation unit (con-
trol or central processing station) or a field device to
the transmission medium. The PBC consists of the line
transceiver, optical isolation, frame character transmit-
ter/receiver (UART), and the FDL/APP processor with the
interface to the PROFIBUS user.
(CENTRAL PROCESSING)
OR FIELD DEVICE
USER INTERFACE
FDL/APP
PROCESSOR
UART
PBC
OPTICAL ISOLATION
TRANSCEIVER
MEDIUM
Figure 22. PROFIBUS Controller (PBC)
17
Power Supplies and Bypassing
Being very similar to multi-station RS485 systems, the
HCPL-061N optocoupler provides a transmit disable
function which is necessary to make the bus free after
each master/slave transmission cycle. Specifically, the
HCPL-061N disables the transmitter of the line driver by
putting it into a high state mode. In addition, the HCPL-
061N switches the RX/TX driver IC into the listen mode.
The HCPL-061N offers HCMOS compatibility and the
high CMR performance (1 kV/µs at VCM = 1000 V) es-
sential in industrial communication interfaces.
The recommended PROFIBUS application circuit is
shown in Figure 23. Since the HCPL-772X/072X are fully
compatible with CMOS logic level signals, the optocoup-
ler is connected directly to the transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 µF) are
required and should be located as close as possible to
the input and output power-supply pins of the HCPL-
772X/072X. For each capacitor, the total lead length be-
tween both ends of the capacitor and the power supply
pins should not exceed 20 mm. The bypass capacitors
are required because of the high-speed digital nature of
the signals inside the optocoupler.
GALVANIC
ISOLATION
BOUNDARY
5 V
ISO 5 V
V
V
V
DD1
8
7
1
2
ISO 5 V
8
DD2
O
V
0.01 µF
IN
HCPL-772x
HCPL-072x
V
CC
0.01
µF
1
R
6
5
3
4
Rx
6
7
+
A
B
0.01
µF
RT
SHIELD
–
SN75176B
GND
GND
1
2
4
3
2
D
DE
RE
5 V
ISO 5 V
GND
5
V
V
DD2
1
2
8
7
DD1
IN
0.01
µF
1 M
0.01 µF
V
Tx
HCPL-772x
HCPL-072x
V
O
3
4
6
5
0.01 µF
GND
GND
2
1
ISO 5 V
V
1
2
8
7
CC
5 V
V
V
ANODE
HCPL-061N
CATHODE
E
680 Ω
0.01
µF
1, 0 kΩ
3
4
6
5
Tx ENABLE
O
GND
Figure 23. Recommended PROFIBUS application circuit
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0565EN
AV02-0876EN - April 5, 2013
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