HCPL-0931 [AVAGO]
High Speed Digital Isolators 15 ns max. propagation delay; 高速数字隔离器15 ns（最大值） 。传播延迟
| 型号： | HCPL-0931 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | High Speed Digital Isolators 15 ns max. propagation delay |
| 文件： | 总14页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-9000/-0900, -9030/-0930,
HCPL-9031/-0931, -900J/-090J,
HCPL-901J/-091J, -902J/-092J
High Speed Digital Isolators
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The HCPL-90xx and HCPL-09xx CMOS digital isolators
feature high speed performance and excellent transient
immunity specifications. The symmetric magnetic
coupling barrier gives these devices a typical pulse width
• +3.3V and +5V TTL/CMOS compatible
• 3 ns max. pulse width distortion
•
6 ns max. propagation delay skew
distortion of 2 ns, a typical propagation delay skew of • 15 ns max. propagation delay
4 ns and 100 Mbaud data rate, making them the indus-
try’s fastest digital isolators.
• High speed: 100 MBd
• 15 kV/µs min. common mode rejection
The single channel digital isolators (HCPL-9000/
• Tri-state output (HCPL-9000/-0900)
-0900) features an active-low logic output enable.
• 2500V RMS isolation
The dual channel digital isolators are configured as
unidirectional (HCPL-9030/-0930) and bi-directional
(HCPL-9031/-0931), operating in full duplex mode making
it ideal for digital fieldbus applications.
• UL1577 and IEC 61010-1 approved
Applications
• Digital fieldbus isolation
• Multiplexed data transmission
• Computer peripheral interface
• High speed digital systems
• Isolated data interfaces
• Logic level shifting
The quad channel digital isolators are configured as
unidirectional (HCPL-900J/-090J), two channels in one
direction and two channels in opposite direction (HCPL-
901J/-091J), and one channel in one direction and
three channels in opposite direction (HCPL-902J/-092J).
These high channel density make them ideally suited
to isolating data conversion devices, parallel buses and
peripheral interfaces.
They are available in 8-pin PDIP, 8-pin Gull Wing, 8-pin
SOIC packages, and 16–pin SOIC narrow-body and
wide-body packages. They are specified over the tem-
perature range of -40°C to +100°C.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
Device Number
Channel Configuration
Package
HCPL-9000
HCPL-0900
HCPL-9030
HCPL-0930
HCPL-9031
HCPL-0931
HCPL-900J
HCPL-090J
HCPL-901J
HCPL-091J
HCPL-902J
HCPL-092J
Single
8-pin DIP (300 Mil)
Single
8-pin Small Outline
Dual
8-pin DIP (300 Mil)
Dual
8-pin Small Outline
Dual, Bi-Directional
Dual, Bi-Directional
Quad
8-pin DIP (300 Mil)
8-pin Small Outline
16-pin Small Outline, Wide Body
16-pin Small Outline, Narrow Body
16-pin Small Outline, Wide Body
16-pin Small Outline, Narrow Body
16-pin Small Outline, Wide Body
16-pin Small Outline, Narrow Body
Quad
Quad, 2/2, Bi-Directional
Quad, 2/2, Bi-Directional
Quad, 1/3, Bi-Directional
Quad, 1/3, Bi-Directional
Ordering Information
HCPL-09xx and HCPL-90xx are UL Recognized with 2500 Vrms for 1 minute per UL1577.
Option
RoHS
Compliant
Non RoHS
Compliant
Surface
Mount
Gull
Wing
Tape &
Reel
Part number
Package
Quantity
HCPL-9000
HCPL-9030
HCPL-9031
-000E
-300E
-500E
-000E
-500E
-000E
-500E
-000E
-500E
No option
-300
50 per tube
50 per tube
1000 per reel
100 per tube
1500 per reel
50 per tube
1000 per reel
50 per tube
1000 per reel
300mil
DIP-8
X
X
X
X
X
X
X
X
X
X
-500
X
X
X
X
HCPL-0900
HCPL-0930
HCPL-0931
No option
-500
SO-8
No option
-500
HCPL-900J
HCPL-901J
HCPL-902J
HCPL-090J
HCPL-091J
HCPL-092J
Wide Body
SO-16
No option
-500
Narrow Body
SO-16
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-9031-500E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel in RoHS
compliant.
Example 2:
HCPL-0900 to order product of SO-8 package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Pin Description
Functional Diagrams
Single Channel
Symbol Description
VDD1
VDD2
INX
Power Supply 1
Truth Table
8
VDD2
VDD1
1
Power Supply 2
IN1
L
VOE
L
OUT1
L
Logic Input Signal
IN1
2
3
4
VOE
7
6
5
OUTX
GND1
GND2
VOE
Logic Output Signal
Power Supply Ground 1
Power Supply Ground 2
OUT1
GND2
NC
H
L
L
H
H
H
Z
GND1
H
Z
Logic Output Enable
HCPL-9000/0900
(Single Channel), Active Low
NC
Not Connected
Dual Channel
8
8
VDD2
VDD2
OUT1
IN2
VDD1
IN1
VDD1
IN1
1
2
1
2
OUT1
OUT2
GND2
7
6
5
7
6
5
3
4
IN2
3
4
OUT2
GND1
GND1
GND2
HCPL-9030/0930
HCPL-9031/0931
Quad Channel
VDD1
GND1
IN1
1
16
VDD1
GND1
IN1
1
VDD1
GND1
IN1
1
16
16
15
VDD2
VDD2
VDD2
GND2
GND2
OUT1
OUT2
IN3
GND2
2
3
4
5
6
7
8
15
14
13
12
11
2
3
4
5
6
7
8
15
14
13
12
11
2
3
4
5
6
7
8
14 OUT1
OUT1
OUT2
OUT3
OUT2
13
IN2
IN3
IN2
IN2
IN3
OUT3
OUT3
12
OUT4
NC
11
OUT4
NC
IN4
IN4
IN4
NC
OUT4
NC
10
10
9
NC
NC
10
9
9
GND1
GND1
GND2
GND2
GND1
GND2
HCPL-902J/-092J
HCPL-901J/-091J
HCPL-900J/-090J
3
Package Outline Drawings
HCPL-9000, HCPL-9030 and HCPL-9031 Standard DIP Packages
8
7
6
5
0.240 (6.096)
0.260 (6.604)
1
2
3
4
0.360 (9.000)
0.400 (10.160)
0.55 (1.397)
0.65 (1.651)
0.290 (7.366)
0.310 (7.874)
0.120 (3.048)
0.150 (3.810)
0.008 (0.203)
0.015 (0.381)
0.015 (0.381)
0.035 (0.889)
°
3°
8°
0.030 (0.762)
0.045 (1.143)
0.300 (7.620)
0.370 (9.398)
0.090 (2.286)
0.110 (2.794)
0.015 (0.380)
0.023 (0.584)
0.045 (1.143)
0.065 (1.651)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
HCPL-9000, HCPL-9030 and HCPL-9031 Gull Wing Surface Mount Option 300
PAD LOCATION (for reference only)
0.360 (9.000)
0.400 (10.160)
0.040 (1.016)
0.047 (1.194)
8
7
6
5
0.190
TYP.
(4.826)
0.240 (6.096)
0.260 (6.604)
0.370 (9.398)
0.390 (9.906)
1
2
3
4
0.015 (0.381)
0.025 (0.635)
0.047 (1.194)
0.070 (1.778)
0.045 (1.143)
0.065 (1.651)
0.370 (9.400)
0.390 (9.900)
0.030 (0.762)
0.045 (1.143)
0.290 (7.370)
0.310 (7.870)
0.008 (0.203)
0.013 (0.330)
0.120 (3.048)
0.150 (3.810)
0.030 (0.760)
0.056 (1.400)
0.015 (0.385)
0.035 (0.885)
12° NOM.
0.025 (0.632)
0.035 (0.892)
0.100
(2.540)
BSC
MIN
MAX
DIMENSIONS INCHES (MILLIMETERS)
LEAD COPLANARITY = 0.004 INCHES (0.10 mm)
4
HCPL-0900, HCPL-0930 and HCPL-0931 Small Outline SO-8 Package
0.189 (4.80)
0.197 (5.00)
8
7
6
5
4
0.228 (5.80)
0.244 (6.20)
0.150 (3.80)
0.157 (4.00)
2
1
3
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
0.020 (0.50)
0.008 (0.19)
0.010 (0.25)
x 45°
0.004 (0.10)
0.010 (0.25)
0.054 (1.37)
0.069 (1.75)
0.040 (1.016)
0.060 (1.524)
0.016 (0.40)
0.050 (1.27)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
HCPL-900J, HCPL-901J and HCPL-902J Wide Body SOIC-16 Package
0.397 (10.084)
0.413 (10.490)
Pin 1 indent
8
1
0.394 (10.007)
0.419 (10.643)
0.013 (0.330)
0.020 (0.508)
0.092 (2.337)
0.105 (2.670)
0.287 (7.290)
0.300 (7.620)
7° TYP
7° TYP
0.080 (2.032)
0.100 (2.54)
0.040 (1.016)
0.060 (1.524)
0.016 (0.40)
0.050 (1.27)
0.007 (0.200)
0.013 (0.330)
0.004 (0.1016)
0.012 (0.300)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
5
HCPL-090J, HCPL-091J and HCPL-092J Narrow Body SOIC-16 Package
0.386 (9.802)
0.394 (9.999)
Pin 1 indent
8
1
0.228 (5.791)
0.244 (6.197)
0.152 (3.861)
0.157 (3.988)
0.013 (0.330)
0.020 (0.508)
0.054 (1.372)
0.072 (1.800)
0.007 (0.200)
0.013 (0.330)
0.040 (1.020)
0.050 (1.270)
0.040 (1.016)
0.060 (1.524)
0.016 (0.406)
0.050 (1.270)
0.004 (0.102)
0.012 (0.300)
MIN
MAX
DIMENSIONS: INCHES (MILLIMETERS)
Package Characteristics
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Capacitance (Input-Output)[1]
CI-O
pF
f = 1 MHz
Single Channel
Dual Channel
Quad Channel
1.1
2.0
4.0
Thermal Resistance
8-Pin PDIP
θJCT
°C/W
mW
Thermocouple located at
center underside of package
54
144
41
8-Pin SOIC
16-Pin SOIC Narrow Body
16-Pin SOIC Wide Body
28
Package Power Dissipation
8-Pin PDIP
PPD
150
150
150
150
8-Pin SOIC
16-Pin SOIC Narrow Body
16-Pin SOIC Wide Body
Notes:
1. Single and dual channels device are considered two-terminal devices: pins 1-4 shorted and pins 5-8 shorted. Quad channel devices are con-
sidered two-terminal devices: pins 1-8 shorted and pins 9-16 shorted.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all inte-
grated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from
performance degradation to complete failure.
6
Insulation and Safety Related Specifications
Parameters
Condition
Min.
Typ.
Max.
Units
Barrier Impedance
Ω||pF
Single Channel
Dual Channel
Quad Channel
>1014||3
>1014||3
>1014||7
Creepage Distance (External)
mm
µA
8-Pin PDIP
8-Pin SOIC
16-Pin SOIC Narrow Body
16-Pin SOIC Wide Body
7.04
4.04
4.03
8.08
Leakage Current
240 VRMS
60 Hz
0.2
IEC61010-1 Insulation Characteristics*
HCPL-0900
HCPL-9000
HCPL-9030
HCPL-900J
HCPL-901J
HCPL-902J
HCPL-0930
HCPL-090J
HCPL-091J
HCPL-092J
Description
Symbol
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
I – III
I – IV
I – III
2
for rated mains voltage ≤ 300 Vrms
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
150
300
Vrms
Soldering Profile
The recommended reflow soldering conditions are per JEDEC Standard J-STD-020 (latest revision).
7
Absolute Maximum Ratings
Parameters
Symbol
TS
Min.
–55
–55
–0.5
–0.5
–0.5
–0.5
Max.
Units
°C
°C
V
Storage Temperature
Ambient Operating Temperature[1]
Supply Voltage
150
TA
125
VDD1, VDD2
VIN
7
Input Voltage
VDD1 +0.5
VDD2 +0.5
VDD2 +0.5
10
V
Voltage Output Enable (HCPL-9000/-0900)
Output Voltage
VOE
V
VOUT
IOUT
V
Output Current Drive
Lead Solder Temperature (10s)
ESD
mA
°C
260
2 kV Human Body Model
Notes:
1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
Recommended Operating Conditions
Parameters
Symbol
TA
Min.
–40
3.0
2.4
0
Max.
100
5.5
VDD1
0.8
1
Units
°C
V
Ambient Operating Temperature
Supply Voltage
VDD1, VDD2
VIH
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
V
VIL
V
tIR, tIF
µs
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends
that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or stor-
age could range from performance degradation to complete failure.
8
3.3V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
IDD1
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
0.008
0.008
1.5
0.018
3.3
0.01
0.01
2.0
0.02
4.0
1.5
2.0
Quiescent Supply Current 2
IDD2
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
3.3
3.3
1.5
5.5
3.3
3.0
4.0
4.0
2.0
8.0
4.0
6.0
Logic Input Current
IIN
-10
10
µA
V
Logic High Output Voltage
VOH
VDD2 –0.1
0.8*VDD2
VDD2
VDD2 –0.5
0
IOUT = -20 µA, VIN= VIH
IOUT = -4 mA, VIN= VIH
IOUT = 20 µA, VIN= VIL
IOUT = 4 mA, VIN= VIL
V
Logic Low Output Voltage
VOL
0.1
0.8
V
0.5
V
Switching Specifications
Maximum Data Rate
Clock Frequency
100
10
110
MBd CL = 15 pF
fmax
tPHL
50
18
MHz
ns
Propagation Delay Time to Logic
Low Output
12
12
Propagation Delay Time toLogic
High Output
tPLH
18
3
ns
Pulse Width
Pulse Width Distortion[1]
tPW
ns
ns
|PWD|
2
|tPHL – tPLH
|
Propagation Delay Skew[2]
Output Rise Time (10 – 90%)
Output Fall Time (10 – 90%)
tPSK
tR
4
2
2
6
4
4
ns
ns
ns
tF
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
Low to High Impedance
High Impedance to High
High Impedance to Low
tPHZ
tPLZ
tPZH
tPZL
tCSK
3
3
3
3
2
5
5
5
5
3
ns
ns
ns
ns
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH|
(Output Logic High or Logic Low)[3] |CML|
15
18
kV/µs Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
9
5V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = VDD2 = +5.0V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Quiescent Supply Current 1
IDD1
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
0.012
0.012
2.5
0.024
5.0
0.018
0.018
3.0
0.036
6.0
2.5
3.0
Quiescent Supply Current 2
IDD2
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
5.0
5.0
2.5
8.0
5.0
6.0
6.0
6.0
3.0
12.0
6.0
9.0
Logic Input Current
IIN
-10
10
µA
V
Logic High Output Voltage
VOH
VDD2– 0.1
0.8*VDD2
VDD2
VDD2 – 0.5
0
IOUT= -20 µA, VIN= VIH
IOUT= -4 mA, VIN= VIH
IOUT= 20 µA, VIN= VIL
IOUT= 4 mA, VIN= VIL
V
Logic Low Output Voltage
VOL
0.1
0.8
V
0.5
V
Switching Specifications
Maximum Data Rate
Clock Frequency
100
10
110
MBd CL = 15 pF
fmax
tPHL
50
15
MHz
ns
Propagation Delay Time to Logic
Low Output
10
10
Propagation Delay Time to Logic
High Output
tPLH
15
3
ns
Pulse Width
Pulse Width Distortion[1]
tPW
ns
ns
|PWD|
2
|tPHL – tPLH
|
Propagation Delay Skew[2]
Output Rise Time (10 – 90%)
Output Fall Time (10 – 90%)
tPSK
tR
4
1
1
6
3
3
ns
ns
ns
tF
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
Low to High Impedance
High Impedance to High
High Impedance to Low
tPHZ
tPLZ
tPZH
tPZL
tCSK
3
3
3
3
2
5
5
5
5
3
ns
ns
ns
ns
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH|
(Output Logic High or Logic Low)[3] |CML|
15
18
kV/µs Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
10
Mixed 5V/3.3V or 3.3V/5V operation: Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA=+25°C, VDD1 = +5.0V, VDD2 = +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
IDD1
0.012
0.012
2.5
0.024
5.0
0.018
0.018
3.0
0.036
6.0
2.5
3.0
Quiescent Supply Current 2
IDD2
mA
VIN = 0V
HCPL-9000/-0900
HCPL-9030/-0930
HCPL-9031/-0931
HCPL-900J/-090J
HCPL-901J/-091J
HCPL-902J/-092J
5.0
5.0
2.5
8.0
5.0
6.0
6.0
6.0
3.0
12.0
6.0
9.0
Logic Input Current
IIN
-10
10
µA
V
Logic High Output Voltage
VOH
VDD2– 0.1
0.8*VDD2
VDD2
VDD2 – 0.5
0
IOUT= -20 µA, VIN= VIH
IOUT= -4 mA, VIN= VIH
IOUT= 20 µA, VIN= VIL
IOUT= 4 mA, VIN= VIL
V
Logic Low Output Voltage
VOL
0.1
0.8
V
0.5
V
Switching Specifications
Maximum Data Rate
Clock Frequency
100
10
110
MBd CL = 15 pF
fmax
tPHL
50
18
MHz
ns
Propagation Delay Time to Logic
Low Output
12
12
Propagation Delay Time to Logic
High Output
tPLH
18
3
ns
Pulse Width
Pulse Width Distortion[1]
tPW
ns
ns
|PWD|
2
|tPHL – tPLH
|
Propagation Delay Skew[2]
Output Rise Time (10 – 90%)
Output Fall Time (10 – 90%)
tPSK
tR
4
2
2
6
4
4
ns
ns
ns
tF
Propagation Delay Enable to Output (Single Channel)
High to High Impedance
Low to High Impedance
High Impedance to High
High Impedance to Low
tPHZ
tPLZ
tPZH
tPZL
tCSK
3
3
3
3
2
5
5
5
5
3
ns
ns
ns
ns
ns
Channel-to-Channel Skew
(Dual and Quad Channels)
Common Mode Transient Immunity |CMH|
(Output Logic High or Logic Low)[3] |CML|
15
18
kV/µs Vcm = 1000V
Notes:
1. PWD is defined as |tPHL -tPLH|. %PWD is equal to the PWD divided by the pulse width.
2. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at 25°C.
3. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VOUT > 0.8VDD2. CML is the maximum common mode
input voltage that can be sustained while maintaining VOUT < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
11
Applications Information
Power Consumption
Bypassing and PC Board Layout
The HCPL-90xx and HCPL-09xx digital isolators are
extremely easy to use. No external interface circuitry is
required because the isolators use high-speed CMOS IC
technology allowing CMOS logic to be connected directly
to the inputs and outputs. As shown in Figure 1, the only
external components required for proper operation are
two 47 nF ceramic capacitors for decoupling the power
supplies. For each capacitor, the total lead length between
both ends of the capacitor and the power-supply pins
should not exceed 20 mm. Figure 2 illustrates the recom-
mended printed circuit board layout for the HCPL-9000
or HCPL-0900. For data rates in excess of 10MBd, use of
ground planes for both GND1 and GND2 is highly recom-
mended.
The HCPL-90xx and HCPL-09xx CMOS digital isolators
achieves low power consumption from the manner by
which they transmit data across isolation barrier. By
detecting the edge transitions of the input logic signal
and converting this to a narrow current pulse, which
drives the isolation barrier, the isolator then latches the
input logic state in the output latch. Since the current
pulses are narrow, about 2.5 ns wide, the power consump-
tion is independent of mark-to-space ratio and solely
dependent on frequency.
The approximate power supply current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency, fmax = 50 MHz.
Signal Status on Start-up and Shut Down
To minimize power dissipation, the input signals to the
channels of HCPL-90xx and HCPL-09xx digital isolators
are differentiated and then latched on the output side of
the isolation barrier to reconstruct the signal. This could
result in an ambiguous output state depending on power
up, shutdown and power loss sequencing. Therefore, the
designer should consider the inclusion of an initializa-
tion signal in this start-up circuit. Initialization consists of
toggling the input either high then low or low then high.
VDD1
IN1
VDD2
8
1
C2
C1
2
NC 3
4
7
6
VOE
OUT1
GND2
GND1
5
Note: C1, C2 = 47 nF ceramic capacitors
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
VDD1
VDD2
IN1
VOE
C2
C1
OUT1
GND2
GND1
Figure 2. Recommended Printed Circuit Board Layout.
12
Propagation Delay, Pulse Width Distortion and Propaga-
tion Delay Skew
Propagation Delay is a figure of merit, which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 3.
As illustrated in Figure 4, if the inputs of two or more
devices are switched either ON or OFF at the same time,
tPSK is the difference between the minimum propagation
delay, either tPLH or tPHL, and the maximum propagation
5 V CMOS
INPUT
VIN
delay, either tPLH or tPHL
.
50%
0 V
t
t
PHL
PLH
VIN
50%
V
OH
2.5 V CMOS
OUTPUT
VOUT
90%
90%
10%
10%
V
OL
2.5 V
CMOS
VOUT
tPSK
Figure 3. Timing Diagrams to Illustrate Propagation Delay, tPLH and tPHL.
50%
The propagation delay from low to high, tPLH, is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low,
tPHL, is the amount of time required for the input signal to
propagate to the output, causing the output to change
from high to low.
VIN
2.5 V
CMOS
VOUT
Figure 4. Timing Diagrams to Illustrate Propagation Delay Skew.
Pulse Width Distortion, PWD, is the difference between tPHL
and tPLH and often determines the maximum data rate ca-
pability of a transmission system. PWD can be expressed in
percent by dividing the PWD (in ns) by the minimum pulse
width (in ns) being transmitted. Typically, PWD on the order
of 20–30% of the minimum pulse width is tolerable.
As mentioned earlier, tPSK, can determine the maximum
parallel data transmission rate. Figure 5 shows the timing
diagram of a typical parallel data transmission application
with both the clock and data lines being sent through the
digital isolators. The figure shows data and clock signals at
the inputs and outputs of the digital isolators. In this case,
the data is clocked off the rising edge of the clock.
Propagation Delay Skew, tPSK, and Channel-to-Channel
Skew, tCSK, are critical parameters to consider in parallel
data transmission applications where synchronization of
signals on parallel data lines is a concern. If the parallel
data is being sent through channels of the digital
isolators, differences in propagation delays will cause
the data to arrive at the outputs of the digital isolators
at different times. If this difference in propagation delay
is large enough, it will limit the maximum transmission
rate at which parallel data can be sent through the digital
isolators.
DATA
INPUTS
CLOCK
DATA
OUTPUTS
tPSK
CLOCK
tPSK
tPSK is defined as the difference between the minimum and
maximum propagation delays, either tPLH or tPHL, among two
or more devices which are operating under the same con-
ditions (i.e., the same drive current, supply voltage, output
load, and operating temperature). tCSK is defined as the
difference between the minimum and maximum propaga-
tion delays, either tPLH or tPHL, among two or more channels
within a single device (applicable to dual and quad channel
devices) which are operating under the same conditions.
Figure 5. Parallel Data Transmission.
13
Propagation delay skew represents the uncertainty of where an edge might be after being sent through a digital
isolator. Figure 5 shows that there will be uncertainty in both the data and clock lines. It is important that these two
areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled,
or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the
absolute minimum pulse width that can be sent through digital isolators in a parallel application is twice tPSK. A cautious
design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does
not cause a problem.
Figure 6 shows the minimum pulse width, rise and fall time, and propagation delay enable to output waveforms for
HCPL-9000 or HCPL-0900.
50%
VIN
tPZL
90%
90%
tPLZ
50%
tPHZ
VOUT
10%
10%
tPZH
tPW
tF
tR
VOE
tPW
tPLZ
tPZH
Minimum Pulse Width
Propagation Delay, Low to High Impedance
Propagation Delay, High Impedance to High
tPHZ
tPZL
tR
Propagation Delay, High to High Impedance
Propagation Delay, High Impedance to Low
Rise Time
tF
Fall Time
Figure 6. Timing Diagrams to Illustrate the Minimum Pulse Width, Rise and Fall Time, and Propagation Delay Enable to Output Waveforms
for HCPL-9000 or HCPL-0900.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes 5989-0803EN
AV02-0137EN - May 20, 2013
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明