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HCPL-177K#300 [AVAGO]

4 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.1Mbps, GULL WING, HERMETIC, DIP-16;
HCPL-177K#300
型号： HCPL-177K#300
厂家： AVAGO TECHNOLOGIES LIMITED    AVAGO TECHNOLOGIES LIMITED
描述：

4 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 0.1Mbps, GULL WING, HERMETIC, DIP-16

输出元件 光电
文件： 总12页 (文件大小：201K)
中文：  中文翻译
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6N140A,* HCPL-675X, 83024, HCPL-570X, HCPL-177K, 5962-89810,  
HCPL-573X, HCPL-673X, 5962-89785, 5962-98002  
Hermetically Sealed, Low I , Wide V ,  
F
CC  
High Gain Optocouplers  
Data Sheet  
*See matrix for available extensions.  
Description  
Features  
These units are single, dual, and quad channel, hermeti- Dual marked with device part number and DLA  
cally sealed optocouplers. The products are capable of  
operation and storage over the full military temperature  
range and can be purchased as either standard product  
or with full MIL-PRF-38534 Class Level H or K testing or  
from the appropriate DLA Drawing. All devices are man-  
ufactured and tested on a MIL-PRF-38534 certified line  
and are included in the DLA Qualified Manufacturers List  
QML-38534 for Hybrid Microcircuits.  
drawing number  
Manufactured and tested on a MIL-PRF-38534 Certified  
Line  
QML-38534, Class H and K  
Five hermetically sealed package configurations  
Performance guaranteed over full military temperature  
range: -55°C to +125°C  
Low input current requirement: 0.5 mA  
High current transfer ratio: 1500% typical @ I = 0.5 mA  
Each channel contains a GaAsP light emitting diode which  
is optically coupled to an integrated high gain photon  
detector. The high gain output stage features an open  
collector output providing both lower saturation voltage  
and higher signaling speed than possible with conven-  
tional photo-Darlington optocouplers. The shallow depth  
and small junctions offered by the IC process provides  
better radiation immunity than conventional photo tran-  
sistor optocouplers.  
F
Low output saturation voltage: 0.11 V typical  
1500 Vdc withstand test voltage  
High radiation immunity  
6N138/9, HCPL-2730/31 function compatibility  
Reliability data  
Applications  
The supply voltage can be operated as low as 2.0V without  
adversely affecting the parametric performance.  
Military and aerospace  
High reliability systems  
Telephone ring detection  
Microprocessor system interface  
These devices have a 300% minimum CTR at an input  
current of only 0.5 mA making them ideal for use in low  
input current applications such as MOS, CMOS, low power  
logic interfaces or line receivers. Compatibility with high Transportation, medical, and life critical systems  
voltage CMOS logic systems is assured by specifying I  
CCH  
Isolated input line receiver  
EIA RS-232-C line receiver  
Voltage level shifting  
and I at 18 Volts.  
OH  
Isolated input line receiver  
Isolated output line driver  
Logic ground isolation  
Harsh industrial environments  
Current loop receiver  
System test equipment isolation  
Process control input/output isolation  
The connection of a 0.1 F bypass capacitor between V and GND is recommended.  
CC  
CAUTION: It is advised that normal static precautions be taken in handling and assembly  
of this component to prevent damage and/or degradation which may be induced by ESD.  
Upon special request, the following device selections can  
be made: CTR minimum of up to 600% at 0.5 mA, and  
lower output leakage current levels to 100 A.  
Functional Diagram  
Multiple Channel Devices Available  
Package styles for these parts are 8 and 16 pin DIP through  
hole (case outlines P and E respectively), 16 pin DIP flat  
pack (case outline F), and leadless ceramic chip carrier  
(case outline 2). Devices may be purchased with a variety  
of lead bend and plating options. See Selection Guide  
table for details. Standard Military Drawing (SMD) parts  
are available for each package and lead style.  
8
1
2
7
6
5
3
4
Because the same electrical die (emitters and detectors)  
are used for each channel of each device listed in this data  
sheet, absolute maximum ratings, recommended operating  
conditions, electrical specifications, and performance char-  
acteristics shown in the figures are similar for all parts  
except as noted. Additionally, the same package assembly  
processes and materials are used in all devices. These simi-  
larities justify the use of a common data base for die related  
reliability and certain limited radiation test results.  
Truth Table  
(Positive Logic)  
Input  
Output  
On (H)  
Off (L)  
L
H
Selection Guide-Package Styles and Lead Configuration Options  
Package  
Lead Style  
Channels  
16 pin DIP  
Through Hole  
4
8 pin DIP  
Through Hole  
1
8 pin DIP  
Through Hole  
2
16 pin Flat Pack  
Unformed Leads  
4
20 Pad LCCC  
Surface Mount  
2
Common Channel Wiring  
Avago Part # & Options  
Commercial  
MIL-PRF-38534 Class H  
MIL-PRF-38534 Class K  
Standard Lead Finish  
Solder Dipped*  
Butt Cut/Gold Plate  
Gull Wing/Soldered*  
Crew Cut/Gold Plate  
Class H SMD Part #  
V
, GND  
None  
V
, GND  
V , GND  
CC  
None  
CC  
CC  
[1]  
6N140A  
6N140A/883B  
HCPL-177K  
HCPL-5700  
HCPL-5701  
HCPL-570K  
Gold Plate  
Option #200  
Option #100  
Option #300  
Option #600  
HCPL-5730  
HCPL-5731  
HCPL-573K  
Gold Plate  
Option #200  
Option #100  
Option #300  
Option #600  
HCPL-6750  
HCPL-6751  
HCPL-675K  
Gold Plate  
HCPL-6730  
HCPL-6731  
HCPL-673K  
Solder Pads*  
Gold Plate  
Option #200  
Option #100  
Option #300  
Option #600  
Prescript for all below  
Gold Plate  
Solder Dipped*  
Butt Cut/Gold Plate  
Butt Cut/Soldered*  
Gull Wing/Soldered*  
Crew Cut/Gold Plate  
Crew Cut/Soldered*  
Class K SMD Part #  
None  
5962-  
5962-  
None  
8302401FC  
5962-  
8302401EC  
8302401EA  
8302401YC  
8302401YA  
8302401XA  
8302401ZC  
8302401ZA  
8981001PC  
8981001PA  
8981001YC  
8981001YA  
8981001XA  
Available  
Available  
8978501PC  
8978501PA  
8978501YC  
8978501YA  
8978501ZA  
Available  
Available  
89785022A  
Prescript for all below  
Gold Plate  
Solder Dipped*  
Butt Cut/Gold Plate  
Butt Cut/Soldered*  
Gull Wing/Soldered*  
Crew Cut/Gold Plate  
Crew Cut/Soldered*  
5962-  
5962-  
5962-  
5962-  
9800201KFC  
5962-  
9800201KEC  
9800201KEA  
9800201KYC  
9800201KYA  
9800201KXA  
9800201KZC  
9800201KZA  
8981002KPC  
8981002KPA  
8981002KYC  
8981002KYA  
8981002KXA  
Available  
8978503KPC  
8978503KPA  
8978503KYC  
8978503KYA  
8978503KZA  
Available  
8978504K2A  
Available  
Available  
*Solder contains lead.  
Note:  
1. JEDEC registered part.  
2
Functional Diagrams  
16 pin DIP  
8 pin DIP  
8 pin DIP  
16 pin Flat Pack  
Unformed Leads  
4 Channels  
20 Pad LCCC  
Through Hole  
4 Channels  
Through Hole  
1 Channel  
Through Hole  
2 Channels  
Surface Mount  
2 Channels  
15  
VCC2  
16  
8
16  
8
7
1
1
1
1
VO2  
19  
13  
12  
GND2  
5  
15  
2
2
3
4
5
6
15  
14  
13  
12  
11  
10  
9
20  
2
2
7
6
5
4  
2
VCC1  
10  
3
4
5
6
7
14  
3
4
3
4
6
5
3
GND1  
13  
VO1  
8
7
12  
11  
10  
9
7
8
8
Note: All DIP and flat pack devices have common V and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate  
CC  
V
CC  
and ground connections.  
Outline Drawings  
16 Pin DIP Through Hole, 4 Channels  
20.06 (0.790)  
20.83 (0.820)  
8.13 (0.320)  
MAX.  
0.89 (0.035)  
1.65 (0.065)  
4.45 (0.175)  
MAX.  
0.51 (0.020)  
MIN.  
3.81 (0.150)  
MIN.  
0.20 (0.008)  
0.33 (0.013)  
7.36 (0.290)  
7.87 (0.310)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
Note: Dimensions in Millimeters (Inches)  
Leaded Device Marking  
Leadless Device Marking  
Avago LOGO  
Avago P/N  
PIN ONE/  
A QYYWWZ  
XXXXXX  
COMPLIANCE INDICATOR,*  
DATE CODE, SUFFIX (IF NEEDED)  
DLA SMD*  
DLA SMD*  
Avago CAGE CODE*  
Avago LOGO  
Avago P/N  
DLA SMD*  
DLA SMD*  
PIN ONE/  
A QYYWWZ  
XXXXXX  
XXXXXXX  
XXX XXX  
COMPLIANCE INDICATOR,*  
DATE CODE, SUFFIX (IF NEEDED)  
XXXX  
XXXXXX  
t
COUNTRY OF MFR.  
Avago CAGE CODE*  
ESD IDENT  
COUNTRY OF MFR.  
50434  
t
XXX 50434  
ESD IDENT  
*QUALIFIED PARTS ONLY  
3
Outline Drawings (continued)  
16 Pin Flat Pack, 4 Channels  
7.24 (0.285)  
6.99 (0.275)  
2.29 (0.090)  
MAX.  
1.27 (0.050)  
REF.  
11.13 (0.438)  
10.72 (0.422)  
0.46 (0.018)  
0.36 (0.014)  
8.13 (0.320)  
MAX.  
2.85 (0.112)  
MAX.  
0.88 (0.0345)  
MIN.  
0.31 (0.012)  
0.23 (0.009)  
0.89 (0.035)  
0.69 (0.027)  
5.23  
(0.206)  
MAX.  
9.02 (0.355)  
8.76 (0.345)  
Note: Dimensions in Millimeters (Inches)  
20 Terminal LCCC Surface Mount, 2 Channels  
8 Pin DIP Through Hole, 1 and 2 Channel  
8.70 (0.342)  
9.10 (0.358)  
9.40 (0.370)  
9.91 (0.390)  
8.13 (0.320)  
MAX.  
4.95 (0.195)  
5.21 (0.205)  
1.78 (0.070)  
2.03 (0.080)  
0.76 (0.030)  
1.27 (0.050)  
7.16 (0.282)  
7.57 (0.298)  
1.02 (0.040) (3 PLCS)  
1.14 (0.045)  
1.40 (0.055)  
4.32 (0.170)  
MAX.  
8.70 (0.342)  
9.10 (0.358)  
4.95 (0.195)  
5.21 (0.205)  
TERMINAL 1 IDENTIFIER  
2.16 (0.085)  
0.51 (0.020)  
3.81 (0.150)  
MIN.  
0.20 (0.008)  
0.33 (0.013)  
MIN.  
METALIZED  
CASTILLATIONS (20 PLCS)  
1.78 (0.070)  
2.03 (0.080)  
0.64  
(0.025)  
(20 PLCS)  
0.51 (0.020)  
7.36 (0.290)  
7.87 (0.310)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
1.52 (0.060)  
2.03 (0.080)  
Note: Dimensions in Millimeters (Inches).  
Solder Thickness 0.127 (0.005) Max.  
Note: Dimensions in Millimeters (Inches).  
4
Hermetic Optocoupler Options  
Option  
Description  
100  
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on com-  
mercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details).  
4.32 (0.170)  
MAX.  
0.51 (0.020)  
1.14 (0.045)  
MIN.  
1.40 (0.055)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
4.32 (0.170)  
MAX.  
0.51 (0.020)  
MIN.  
1.14 (0.045)  
1.40 (0.055)  
0.20 (0.008)  
0.33 (0.013)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
7.36 (0.290)  
7.87 (0.310)  
Note: Dimensions in Millimeters (Inches).  
200  
300  
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and  
16 pin DIP. DLA Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered  
with solder dipped terminals as a standard feature.  
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on  
commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped  
leads.  
4.57 (0.180)  
MAX.  
0.51 (0.020)  
MIN.  
1.40 (0.055)  
1.65 (0.065)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
4.57 (0.180)  
MAX.  
4.57 (0.180)  
MAX.  
0.20 (0.008)  
0.33 (0.013)  
0.51 (0.020)  
1.40 (0.055)  
5° MAX.  
MIN.  
1.07 (0.042)  
1.32 (0.052)  
1.65 (0.065)  
9.65 (0.380)  
9.91 (0.390)  
2.29 (0.090)  
2.79 (0.110)  
0.51 (0.020)  
MAX.  
Note: Dimensions in Millimeters (Inches).  
600  
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on com-  
mercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). Contact factory for the availability of this  
option on DLA part types.  
3.81 (0.150)  
3.81 (0.150)  
MAX.  
MAX.  
0.20 (0.008)  
0.33 (0.013)  
0.51 (0.020)  
MIN.  
0.51 (0.020)  
MIN.  
2.29 (0.090)  
2.79 (0.110)  
1.14 (0.045)  
1.25 (0.049)  
2.29 (0.090)  
2.79 (0.110)  
1.02 (0.040)  
TYP.  
7.36 (0.290)  
7.87 (0.310)  
Note: Dimensions in Millimeters (Inches).  
Solder contains lead.  
5
Absolute Maximum Ratings  
Parameter  
Symbol  
TS  
Min.  
-65  
-55  
Max.  
Units  
°C  
Notes  
Storage Temperature  
+150  
Operating Temperature  
TA  
+125  
°C  
Case Temperature  
TC  
+170  
°C  
Junction Temperature  
TJ  
+175  
°C  
Lead Solder Temperature  
260 for 10 sec  
°C  
Output Current (each channel)  
Output Voltage (each channel)  
Supply Voltage  
IO  
40  
20  
20  
50  
20  
10  
5
mA  
V
VO  
VCC  
-0.5  
-0.5  
1
V
1
2
Output Power Dissipation (each channel)  
Peak Input Current (each channel, <1 ms duration)  
Average Input Current (each channel)  
Reverse Input Voltage (each channel)  
Package Power Dissipation (each channel)  
mW  
mA  
mA  
V
IF  
3
VR  
PD  
200  
mW  
8 Pin Ceramic DIP Single Channel Schematic  
V
8
CC  
I
I
CC  
F
2
+
ANODE  
V
F
I
–
3
O
6
5
CATHODE  
V
O
GND  
ESD Classification  
(MIL-STD-883, Method 3015)  
HCPL-5700/01/0K and 6730/31/3K  
6N140A, 6N140A/883B, HCPL-177K,  
(
), Class 2  
(Dot), Class 3  
HCPL-6750/51/5K and HCPL-5730/31/3K  
Recommended Operating Conditions  
Parameter  
Symbol  
Min.  
Max.  
0.8  
5
Units  
V
Input Voltage, Low Level (Each Channel)  
Input Current, High Level (Each Channel)  
Supply Voltage  
VF(OFF)  
IF(ON)  
VCC  
0.5  
2.0  
2.0  
mA  
V
18  
Output Voltage  
VO  
18  
V
6
Electrical Characteristics, T = -55°C to +125°C, unless otherwise specified  
A
Limits  
[13]  
Group A  
Parameter  
Symbol  
Test Conditions  
Subgroup  
Min.  
Typ.** Max.  
1500  
Units  
Fig.  
Note  
Current Transfer  
Ratio  
CTR*  
IF = 0.5 mA, VO = 0.4 V,  
VCC = 4.5 V  
1, 2, 3  
300  
%
3
4, 5  
IF = 1.6 mA, VO = 0.4 V,  
300  
200  
1000  
500  
V
CC = 4.5 V  
IF =5 mA, VO = 0.4 V,  
VCC = 4.5 V  
Logic Low Output VOL  
Voltage  
IF = 0.5 mA, IOL = 1.5 mA, 1, 2, 3  
CC = 4.5 V  
0.11  
0.13  
0.16  
0.001  
0.4  
0.4  
0.4  
V
2
4
V
IF = 1.6 mA, IOL = 4.8 mA,  
VCC = 4.5 V  
4, 16  
4
IF =5 mA, IOL = 10 mA,  
VCC = 4.5 V  
Logic High Output IOH  
*
IF =2 A, VO = 18 V,  
1, 2, 3  
1, 2, 3  
250  
250  
2
A  
A  
mA  
4
Current  
V
CC = 18 V  
IOHX  
ICCL  
4, 6  
15  
Logic  
Low  
Single  
Channel  
*
IF =1.6 mA, VCC = 18 V  
1.0  
Supply and LCCC  
Current  
Dual  
I
F1 =IF2 = 1.6 mA,  
1.0  
4
4
Channel  
V
CC = 18 V  
Quad  
Channel  
IF1 = IF2 =IF3 =IF4 =1.6 mA,  
VCC = 18 V  
1.7  
4
Single  
Channel  
and LCCC  
Logic  
High  
Supply  
Current  
ICCH  
*
IF =0 mA, VCC = 18 V  
1, 2, 3  
0.001  
20  
A  
15  
Dual  
Channel  
I
V
F1 =IF2 = 0 mA,  
CC = 18 V  
40  
40  
Quad  
Channel  
I
V
F1 = IF2 =IF3 =IF4 =0 mA,  
CC = 18 V  
Single  
and Dual  
Channel  
Input  
Forward  
Voltage  
VF*  
IF = 1.6 mA  
1
1.0  
1.0  
5
1.4  
1.7  
1.7  
1.8  
1.8  
1.7  
1.8  
V
1
4
2
3
LCCC  
1, 2, 3  
1, 2  
3
1.4  
1.4  
Quad  
Channel  
Input Reverse  
Breakdown  
Voltage  
BVR  
*
IR = 10 A  
1, 2, 3  
V
4
Input-Output  
Insulation Leakage  
Current  
II-O  
*
≤65% Relative Humidity  
TA =25°C, t = 5 s,  
VI-O = 1500 VDC  
1
4
1.0  
4
A  
pF  
7, 12  
Capacitance  
Between  
CI-O  
f= 1 MHz, TA =25°C  
4, 8  
14, 17  
Input-Output  
*
For JEDEC registered parts.  
** All typical values are at V = 5 V, T = 25°C.  
CC  
A
7
Electrical Characteristics (cont), T = -55°C to +125°C, unless otherwise specified  
A
Limits  
Typ.** Max.  
[13]  
Group A  
Parameter  
Symbol  
Test Conditions  
Subgroup  
Min.  
Units  
Fig.  
Note  
Propagation Delay tPHL  
Time to Logic Low  
*
IF = 0.5 mA, RL = 4.7 k,  
VCC =5 V  
9, 10, 11  
30  
100  
s  
5, 6,  
7, 8  
4
at Output  
tPHL  
IF = 1.6 mA, RL = 1.5 k,  
9, 10, 11  
5
30  
4, 16  
4, 17  
VCC =5 V  
tPHL*  
IF =5 mA, RL = 680 ,  
VCC =5 V  
9
2
5
10, 11  
9, 10, 11  
9, 10, 11  
10  
10  
60  
4, 16  
4
Propagation Delay tPLH  
Time to Logic High  
*
IF = 0.5 mA, RL = 4.7 k,  
VCC =5 V  
17  
14  
8
s  
5, 6,  
7, 8  
at Output  
tPLH  
IF = 1.6 mA, RL = 1.5 k,  
VCC =5 V  
9, 10, 11  
50  
4, 16  
4, 17  
tPLH*  
IF =5 mA, RL = 680 ,  
VCC =5 V  
9
20  
30  
30  
10, 11  
9, 10, 11  
9, 10, 11  
4, 16  
Common Mode  
Transient  
Immunity at Low  
Output Level  
|CML|  
|CMH|  
VCC =5 V, IF = 1.6 mA  
500  
500  
1000  
1000  
V/s  
V/s  
9
9
4, 10  
11, 14  
RL =1.5 k  
|VCM|= 25 VP-P  
[17]  
[16]  
|VCM|= 50 VP-P  
Common Mode  
Transient  
VCC =5 V, IF =0 mA  
9, 10, 11  
4, 10  
11, 14  
RL =1.5 k  
|VCM|= 25 VP-P  
[17]  
Immunity at High  
Output Level  
[16]  
|VCM|= 50 VP-P  
*
For JEDEC registered parts.  
** All typical values are at V = 5 V, T = 25°C.  
CC  
A
Typical Characteristics, T =25°C, V =5 V  
A
CC  
Parameter  
Sym.  
Typ.  
60  
Units  
Test Conditions  
VF =0 V, f = 1 MHz  
IF = 1.6 mA  
Note  
Input Capacitance  
CIN  
pF  
4
4
Input Diode Temperature  
Coefficient  
VF/TA  
-1.8  
mV/°C  
Resistance (Input-Output)  
Capacitance (Input-Output)  
Dual and Quad Channel Product Only  
Input-Input Leakage Current  
RI-O  
CI-O  
1012  
2.0  
  
VI-O = 500 V  
f = 1 MHz  
4, 8  
4, 8  
pF  
II-I  
0.5  
nA  
Relative Humidity = ≤65%,  
I-I = 500 V, t = 5 s  
9
V
Resistance (Input-Input)  
Capacitance (Input-Input)  
RI-I  
CI-I  
1012  
1.0  
  
VI-I = 500 V  
f = 1 MHz  
9
9
pF  
8
Notes:  
1. GND Pin should be the most negative voltage at the detector side.  
11. In applications where dV/dt may exceed 50,000 V/s (such as  
Keeping V as low as possible, but greater than 2.0 V, will provide  
a static discharge) a series resistor, R , should be included to  
CC  
CC  
lowest total I over temperature.  
protect the detector ICs from destructively high surge currents. The  
recommended value is:  
OH  
2. Output power is collector output power plus total supply power for  
the single channel device. For the dual channel device, output power  
is collector output power plus one half the total supply power. For  
the quad channel device, output power is collector output power  
plus one fourth of total supply power. Derate at 1.66 mW/°C above  
110°C.  
1 (V)  
R
=————— k  
CC  
0.15 I (mA)  
F
for single channel;  
1 (V)  
3. Derate I at 0.33 mA/°C above 110°C.  
F
R
=————— k  
CC  
4. Each channel.  
0.3 I (mA)  
F
5. CURRENT TRANSFER RATIO is defined as the ratio of output collector  
for dual channel;  
current, I , to the forward LED input current, I , times 100%.  
O
F
1 (V)  
6.  
I
is the leakage current resulting from channel to channel optical  
OHX  
R
=————— k  
CC  
crosstalk. I =2 μA for channel under test. For all other channels,  
I =10mA.  
F
F
0.6 I (mA)  
F
for quad channel.  
7. All devices are considered two-terminal devices; measured between  
all input leads or terminals shorted together and all output leads or  
terminals shorted together.  
8. Measured between each input pair shorted together and all output  
connections for that channel shorted together.  
12. This is a momentary withstand test, not an operating condition.  
13. Standard parts receive 100% testing at 25°C (Subgroups 1 and  
9). SMD and 883B parts receive 100% testing at 25,125, and -55°C  
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).  
9. Measured between adjacent input pairs shorted together for each  
multi-channel device.  
14. Parameters tested as part of device initial characterization and  
after design and process changes. Parameters guaranteed to limits  
specified for all lots not specifically tested.  
10. CM is the maximum rate of rise of the common mode voltage that  
L
can be sustained with the output voltage in the logic low state  
15. The HCPL-6730, HCPL-6731, and HCPL-673K dual channel parts  
function as two independent single channel units. Use the single  
channel parameter limits.  
16. Not required for 6N140A, 6N140A/883B, HCPL-177K, HCPL-  
6750/51/5K, 8302401, and 5962-9800201 types.  
(V <0.8 V). CM is the maximum rate of fall of the common mode  
O
H
voltage that can be sustained with the output voltage in the logic  
high state (V > 2.0 V).  
O
17. Required for 6N140A, 6N140A/883B, HCPL-177K, HCPL-6750/51/5K,  
8302401, and 5962-9800201 types.  
9
Figure 1. Input Diode Forward Current vs. Forward Figure 2. Normalized DC Transfer Characteristics.  
Voltage.  
Figure 3. Normalized Current Transfer Ratio vs.  
Input Diode Forward Current.  
Figure 4. Normalized Supply Current vs. Input  
Diode Forward Current.  
Figure 5. Propagation Delay to Logic Low vs. Input Figure 6. Propagation Delay vs. Temperature.  
Pulse Period.  
Figure 7. Propagation Delay vs. Input Diode  
Forward Current.  
10  
PULSE GEN.  
Z
O = 50   
tr, tf = 50 ns  
f = 100 Hz  
RCC*  
56   
RCC*  
56   
IF  
B
IF  
+5 V  
VO  
+5 V  
VO  
tPULSE = 0.5ms  
8
1
2
8
1
2
RL  
RL  
1.0 F  
1.0 F  
A
7
6
5
7
6
5
IF MONITOR  
CL**  
Rm  
3
4
3
4
VFF  
VCM  
+
–
PULSE GEN.  
* SEE NOTE 11  
* SEE NOTE 11  
** CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE.  
Figure 8. Switching Test Circuit (f, tP not JEDEC registered).  
Figure 9. Test Circuit for Transient Immunity and Typical Waveforms.  
VCC  
R1  
ILEAK  
R2  
8
1
2
2.4  VF  
IF  
VCC  VF  IF R2  
IF + ILEAK  
R2  
R1  
≥
≤
7
6
5
3
4
R2 MAY BE OMITTED  
IF ADDITIONAL FANOUT  
IS NOT USED.  
Figure 10. Recommended Drive Circuitry Using TTL Open-Collector Logic.  
11  
MIL-PRF-38534 Class H, Class K, and  
DLA SMD Test Program  
Avago’s Hi-Rel Optocouplers are in compliance with MIL-  
PRF-38534 Class H and K. Class H and Class K devices are  
also in compliance with DLA drawings 83024, 5962-89785,  
5962-89810, and 5962-98002.  
Testing consists of 100% screening and quality confor-  
mance inspection to MIL-PRF-38534.  
VCC + 18 V  
8
1
2
VOC  
0.01 F  
(EACH INPUT)  
7
6
5
+
–
3
4
VIN  
(EACH OUTPUT)  
CONDITIONS: IF = 10 mA  
IO = 40 mA  
TA = +125°C  
* ALL CHANNELS TESTED SIMULTANEOUSLY.  
Figure 11. Operating Circuit for Burn-In and Steady State Life Tests.  
For product information and a complete list of distributors, please go to our web site: www.avagotech.com  
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.  
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9400E  
AV02-1766EN - October 2, 2012  

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