HCPL-263L060 [AVAGO]
2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 15Mbps, 0.300 INCH, DIP-8;
| 型号： | HCPL-263L060 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 15Mbps, 0.300 INCH, DIP-8 输出元件 |
| 文件： | 总15页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-260L/060L/263L/063L
High Speed LVTTL Compatible 3.3 Volt Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Features
Description
•
•
Low power consumption
The HCPL-260L/060L/263L/063L are optically coupled
gates that combine a GaAsP light emitting diode and
an integrated high gain photo detector. An enable
input allows the detector to be strobed. The output of
the detector IC is an open collector Schottky-clamped
transistor. The internal shield provides a guaranteed
common mode transient immunity specification of
15 kV/µs.
15 kV/µs minimum Common Mode Rejection (CMR) at
V
= 1000 V
CM
•
•
•
•
High speed: 15 MBd typical
LVTTL/LVCMOS compatible
Low input current capability: 5 mA
Guaranteed AC and DC performance over temperature:
–40˚C to +85˚C
This unique design provides maximum AC and DC circuit
isolation while achieving LVTTL/LVCMOS compati-bility.
The optocoupler AC and DC operational parameters are
guaranteed from –40˚C to +85˚C allowing trouble-free
system performance.
•
•
•
Available in 8-pin DIP, SOIC-8
Strobable output (single channel products only)
Safety approvals: UL, CSA, IEC/EN/DIN EN 60747-5-2
These optocouplers are suitable for high speed logic
interfacing, input/output buffering, as line receivers in
environments that conventional line receivers cannot
tolerate and are recommended for use in extremely high
ground or induced noise environments.
Applications
•
•
•
•
•
•
•
•
•
Isolated line receiver
Computer-peripheral interfaces
Microprocessor system interfaces
Digital isolation for A/D, D/A conversion
Switching power supply
Functional Diagram
HCPL-260L/060L
HCPL-263L/063L
1
2
V
V
V
ANODE
CATHODE
CATHODE
ANODE
1
2
V
V
8
7
8
7
NC
CC
CC
O1
O2
1
1
Instrument input/output isolation
Ground loop elimination
ANODE
E
V
CATHODE
NC
3
4
6
5
3
4
6
5
O
2
2
Pulse transformer replacement
Field buses
GND
GND
SHIELD
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
TRUTH TABLE
(POSITIVE LOGIC)
LED ENABLE OUTPUT
LED OUTPUT
ON
OFF
ON
OFF
ON
OFF
H
H
L
L
NC
NC
L
H
H
H
L
ON
OFF
L
H
A 0.1 µF bypass capacitor must be
connected between pins 5 and 8.
H
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
HCPL-xxxx is UL Recognized with 3750 Vrms for 1 minute per UL1577
Option
UL 5000
Vrms/
Minute
rating
1
IEC/EN/DIN
EN 60747-
5-2
Part
number
RoHS
Non RoHS
Compliant Compliant
Surface
Mount
Package
Gull Wing Tape& Reel
Quantity
-000E
-500E
-060E
-560E
-000E
-500E
-060E
-560E
No option
#500
50 per tube
1000 per reel
50 per tube
1000 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
X
X
X
X
X
X
X
X
X
X
X
X
HCPL-260L
HCPL-263L
300mil DIP-8
#060
X
X
#560
No option
#500
HCPL-060L
HCPL-063L
SO-8
#060
X
X
#560
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry. Combination of Option 020 and Option 060 is not available.
Example 1:
HCPL-260L-560E to order product of 300mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with
IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-263L to order product of 300mil DIP package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation‘#XXX’is used for existing products, while (new) products launched since 15th July 2001 and RoHS
compliant option will use ‘-XXXE‘.
Schematic
HCPL-260L/060L
HCPL-263L/063L
I
F
I
I
CC
I
CC
I
V
V
V
V
CC
O
CC
O1
8
6
2+
8
7
1
+
I
F1
O
O1
V
F1
–
2
V
F
–
3
GND
SHIELD
5
SHIELD
I
E
7
E
3
–
V
I
O2
V
O2
6
5
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
V
F2
+
4
I
F2
GND
SHIELD
2
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5 TYP.
+ 0.003)
- 0.002)
3.56 ± 0.13
(0.140 ± 0.005)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
* MARKING CODE LETTER FOR OPTION NUMBERS
"V" = OPTION 060
OPTION NUMBER 500 NOT MARKED.
2.54 ± 0.25
(0.100 ± 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
8-Pin DIP Package with Gull Wing Surface Mount in Option 500
(HCPL-260L, HCPL-263L)
LAND PATTERN RECOMMENDATION
1.016 (0.040)
9.65 ± 0.25
(0.380 ± 0.010)
6
5
8
1
7
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
2
3
4
2.0 (0.080)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
– 0.051
0.254
3.56 ± 0.13
(0.140 ± 0.005)
+ 0.003
– 0.002)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12 NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
3
Small Outline SO-8 Package
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
3
PIN ONE
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025)
0.432
*
7
5.080 ± 0.127
(0.200 ± 0.005)
45 X
(0.017)
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Solder Reflow Temperature Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
100
0
2.5 C ± 0.5 C/SEC.
SOLDERING
TIME
200°C
30
160 C
150 C
140 C
SEC.
30
SEC.
3 C + 1 C/–0.5 C
PREHEATING TIME
150 C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
100
150
200
250
TIME (SECONDS)
Note: Non-halide flux should be used.
4
Recommended PB-Free IR Profile
TIME WITHIN 5 C of ACTUAL
PEAK TEMPERATURE
t
p
20-40 SEC.
260 +0/-5 C
T
T
p
217 C
L
RAMP-UP
3 C/SEC. MAX.
150 - 200 C
RAMP-DOWN
6 C/SEC. MAX.
T
smax
T
smin
t
s
t
L
60 to 150 SEC.
PREHEAT
60 to 180 SEC.
25
t 25 C to PEAK
TIME
NOTES:
THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX.
= 200 C, T = 150 C
T
smax
smin
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-260L/060L/263L/063L have been approved by the following organizations:
UL
Approval under UL 1577, Component Recognition Program, File E55361.
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
(Option 060 only)
Insulation and Safety Related Specifications
8-Pin DIP
(300 Mil)
Value
SO-8
Value
Parameter
Symbol
Units
Conditions
Minimum External Air
Gap (External Clearance)
L (101)
7.1
4.9
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking L (102)
(External Creepage)
7.4
4.8
mm
mm
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic
Gap (Internal Clearance)
0.08
0.08
Through insulation distance, conductor
to conductor, usually the direct distance
between the photoemitter and
photodetector inside the optocoupler cavity.
Tracking Resistance
(Comparative Tracking Index)
CTI
200
IIIa
200
IIIa
Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group (DIN VDE 0110, 1/89, Table 1)
5
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
Description
Symbol
PDIP Option 060
SO-8 Option 60
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 V rms
I-IV
I-III
I-II
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 600 V rms
I-IV
I-III
Climatic Classification
55/85/21
55/85/21
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
2
2
V
V
630
566
V
V
IORM
peak
V
x 1.875 = V , 100% Production Test
1181
1063
IORM
PR
PR
peak
with t = 1 sec, Partial Discharge < 5 pC
m
Input to Output Test Voltage, Method a*
V
x 1.5 = V , Type and Sample Test,
= 60 sec, Partial Discharge < 5 pC
V
V
945
849
V
V
IORM
PR
PR
peak
t
m
Highest Allowable Overvoltage*
6000
4000
IOTM
peak
(Transient Overvoltage, t = 10 sec)
ini
Safety Limiting Values
(See below for Thermal Derating Curve Figures)
Case Temperature
T
175
230
600
150
150
600
˚C
mA
mW
S
Input Current
Output Power
I
S,INPUT
P
S,OUTPUT
9
9
Insulation Resistance at T , V = 500 V
R
≥ 10
≥ 10
Ω
S
IO
S
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Thermal Derating Curve Figures
HCPL-260L/HCPL-263L
HCPL-060L/HCPL-063L
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
P
I
(mW)
(mA)
P
I
(mW)
(mA)
S
S
S
S
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – C
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – C
T
T
S
S
6
Absolute Maximum Ratings (No Derating Required up to 85˚C)
Parameter
Symbol
Package**
Min.
–55
–40
Max.
125
85
Units
˚C
Note
Storage Temperature
Operating Temperature†
Average Forward Input Current
T
S
T
A
˚C
I
Single 8-Pin DIP
Single SO-8
20
mA
2
F
Dual 8-Pin DIP
Dual SO-8
15
1, 3
1
Reverse Input Voltage
V
8-Pin DIP, SO-8
5
V
R
Input Power Dissipation
P
40
7
mW
V
I
Supply Voltage (1 Minute Maximum)
Enable Input Voltage (Not to Exceed
V
V
CC
E
Single 8-Pin DIP
Single SO-8
V
+ 0.5
V
CC
V
by more than 500 mV)
CC
Enable Input Current
I
I
5
mA
mA
V
E
Output Collector Current
Output Collector Voltage
Output Collector Power Dissipation
50
7
1
1
O
V
P
O
O
Single 8-Pin DIP
Single SO-8
85
mW
Dual 8-Pin DIP
Dual SO-8
60
1, 4
Lead Solder Temperature
(Through Hole Parts Only)
T
LS
8-Pin DIP
260˚C for 10 sec., 1.6 mm below
seating plane
Solder Reflow Temperature Profile
(Surface Mount Parts Only)
SO-8
See Package Outline Drawings
section
**Ratings apply to all devices except otherwise noted in the Package column.
Recommended Operating Conditions
Parameter
Symbol
Min.
0
Max.
250
15
Units
µA
mA
V
Input Current, Low Level
Input Current, High Level
Power Supply Voltage
I
I
*
FL
[1]
**
5
FH
V
V
V
2.7
0
3.6
0.8
CC
Low Level Enable Voltage
High Level Enable Voltage
V
EL
2.0
–40
V
CC
V
EH
Operating Temperature
T
A
85
5
˚C
[1]
Fan Out (at R = 1 kΩ)
N
TTL Loads
Ω
L
Output Pull-up Resistor
R
L
330
4 k
*The off condition can also be guaranteed by ensuring that V ≤ 0.8 volts.
FL
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be
used for best performance and to permit at least a 20% LED degradation guardband.
7
Electrical Specifications
Over Recommended Temperature (T = –40˚C to +85˚C) unless otherwise specified. All Typicals at V = 3.3 V,
A
CC
T = 25˚C. All enable test conditions apply to single channel products only. See Note 5.
A
Parameter
Sym.
Device Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
High Level
Output Current
I
*
OH
4.5
50
µA
V
V
= 3.3 V, V = 2.0 V,
1
1, 15
CC
E
= 3.3 V, I = 250 µA
O
F
Input Threshold
Current
I
3.0
5.0
0.6
mA
V
V
V
= 3.3 V, V = 2.0 V,
= 0.6 V,
(Sinking) = 13 mA
2
15
15
TH
CC
E
O
I
OL
Low Level
V
*
0.35
V
= 3.3 V, V = 2.0 V,
3
OL
CC
E
Output Voltage
I = 5 mA,
F
I
(Sinking) = 13 mA
OL
High Level
I
I
Single
Dual
4.7
6.9
7.0
8.7
–0.5
7.0
mA
mA
V = 0.5 V I = 0 mA
CCH
CCL
EH
E
F
Supply Current
10.0
10.0
15.0
–1.2
V
CC
= 3.3 V
Low Level
Supply Current
Single
Dual
V = 0.5 V I = 10 mA
E
F
V
CC
= 3.3 V
High Level
Enable Current
I
I
mA
mA
V
V
CC
V
CC
= 3.3 V, V = 2.0 V
E
Low Level
Enable Current
*
EL
–0.5
–1.2
= 3.3 V, V = 0.5 V
E
High Level
Enable Voltage
V
V
V
2.0
15
EH
EL
F
Low Level
Enable Voltage
0.8
V
Input Forward
Voltage
1.4
5
1.5
1.75*
V
T = 25˚C, I = 10 mA
5
1
1
A
F
Input Reverse
Breakdown
Voltage
BV *
V
I = 10 µA
R
R
Input Diode
Temperature
Coefficient
∆V /
∆T
A
–1.6
60
mV˚C I = 10 mA
1
1
F
F
Input
C
IN
pF
f = 1 MHz, V = 0 V
F
Capacitance
*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.
8
Switching Specifications
Over Recommended Temperature (T = –40˚C to +85˚C), V = 3.3 V, I = 7.5 mA unless otherwise specified. All Typi-
A
CC
F
cals at T = 25˚C, V = 3.3 V.
A
CC
Parameter
Sym.
Package** Min. Typ. Max. Units Test ConditionsFig.
Note
Propagation Delay
Time to High Output
Level
tPLH
90
ns
RL = 350 Ω
CL = 15 pF
6, 7, 8 1, 6, 15
Propagation Delay
Time to Low Output
Level
tPHL
75
ns
1, 7, 15
Pulse Width
Distortion
|tPHL – tPLH
|
8-Pin DIP
SO-8
25
40
ns
ns
ns
ns
ns
8
9, 15
8, 9, 15
1, 15
1, 15
10
Propagation Delay
Skew
tPSK
tr
Output Rise Time
(10-90%)
45
20
45
Output Fall Time
(90-10%)
tf
Propagation Delay
Time of Enable from
VEH tp VEL
tELH
RL = 350 Ω,
CL = 15 pF,
VEL = 0 V, VEH = 3 V
9
Propagation Delay
Time of Enable from
VEL to VEH
tEHL
30
ns
11
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter
Sym.
Device
Min.
Typ.
Units Test Conditions
Fig.
Note
Logic High
Common
Mode
Transient
Immunity
|CMH|
HCPL-263L 15,000 25,000 V/µs |VCM| = 1000 V
HCPL-063L
VCC = 3.3 V, IF = 0 mA,
VO(MIN) = 2 V,
RL = 350 Ω, TA = 25˚C
11
12, 14, 15
HCPL-260L 15,000 25,000
HCPL-060L
|VCM| = 1000 V
Logic Low
Common
Mode
Transient
Immunity
|CML|
HCPL-263L 15,000 25,000 V/µs |VCM| = 1000 V
HCPL-063L
VCC = 3.3 V, IF = 7.5 mA,
VO(MAX) = 0.8 V,
RL = 350 Ω, TA = 25˚C
11
13, 14, 15
HCPL-260L 15,000 25,000
HCPL-060L
|VCM| = 1000 V
9
Package Characteristics
All Typicals at T = 25˚C.
A
Parameter
Sym.
Package
Min. Typ.
Max
Units
Test Conditions
Fig. Note
Input-Output
Insulation
II-O*
Single 8-Pin DIP
Single SO-8
1
µA
45% RH, t = 5 s,
VI-O = 3 kV DC, TA = 25˚C
16, 17
Input-Output
Momentary
Withstand
Voltage**
VISO
8-Pin DIP, SO-8
3750
V rms
RH ≤ 50%, t = 1 min,
TA = 25˚C
16, 17
Input-Output
Resistance
RI-O
CI-O
II-I
8-Pin, SO-8
1012
0.6
Ω
VI-O =500 V dc
1, 16, 19
1, 16, 19
20
Input-Output
Capacitance
8-Pin DIP, SO-8
Dual Channel
pF
µA
f = 1 MHz, TA = 25˚C
Input-Input
Insulation
Leakage
0.005
RH ≤ 45%, t = 5 s,
VI-I = 500 V
Current
Resistance
(Input-Input)
RI-I
CI-I
Dual Channel
1011
Ω
20
20
Capacitance
(Input-Input)
Dual 8-Pin Dip
Dual SO-8
0.03
0.25
pG
f = 1 MHz
*The JEDEC Registration specifies 0˚C to +70˚C. Avago specifies –40˚C to +85˚C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equip-
ment level safety specification or Avago Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage."
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not
exceed 15 mA.
4. Derate linearly above +80˚C free-air temperature at a rate of 2.7 mW/˚C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 11. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The t
propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the rising edge
PLH
of the output pulse.
7. The t
propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the falling edge
PHL
of the output pulse.
8. t is equal to the worst case difference in t
and/or t
that will be seen between units at any given temperature and specified test condi-
PSK
PHL
PLH
tions.
9. See test circuit for measurement details.
10. The t
enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V point on the
ELH
rising edge of the output pulse.
11. The t enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point on the fall-
ELH
ing edge of the output pulse.
12. CM is the maximum tolerable rate of rise on the common mode voltage to assure that the output will remain in a high logic state
H
(i.e., V > 2.0 V).
o
13. CM is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
L
(i.e., V < 0.8 V).
14. For sinusoidal voltages, (|dV | / dt)
o
= πf
V
(p-p).
CM
max
CM CM
15. No external pull up is required for a high logic state on the enable input. If the V pin is not used, tying V to V will result in improved
E
E
CC
CMR performance. For single channel products only. See application information provided.
16. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
17. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second (leakage
detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
I-O
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
18. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second (leakage
detection current limit, I ≤ 5 µA). This test is performed before the 100% production test for partial discharge (Method b) shown in the
I-O
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
19. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only.
20. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
10
8-PIN DIP, SO-8
= 3.3 V
8-PIN DIP, SO-8
15
10
12
10
0.8
0.7
V
V
V
= 3.3 V
= 3.3 V
= 2.0 V*
= 250 µA
V
V
V
V
I
= 3.3 V * FOR SINGLE
CC
O
E
CC
= 0.6 V
CC
= 2.0 V*
E
= 5.0 mA
CHANNEL
PRODUCTS ONLY
O
F
I
F
0.6
0.5
0.4
0.3
0.2
8
6
4
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
R
= 350 KΩ
L
R
= 1 KΩ
L
I
= 13 mA
O
5
0
2
0
0.1
0
R
= 4 KΩ
L
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40
80 100
-60 -40 -20
0
20 40
80 100
60
60
T
– TEMPERATURE – C
A
T
– TEMPERATURE – C
A
T
– TEMPERATURE – C
A
Figure 1. Typical high level output current vs. tem-
perature.
Figure 2. Typical input threshold current vs. tempera-
ture.
Figure 3. Typical low level output voltage vs. tem-
perature.
8-PIN DIP, SO-8
1000
70
V
V
V
= 3.3 V
= 2.0 V*
= 0.6 V
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
CC
E
OL
T
= 25 C
A
100
10
I
F
60
50
+
F
V
–
1.0
I
= 5.0 mA
F
0.1
0.01
40
20
0.001
1.1
1.2
1.3
1.4
1.5
1.6
-60 -40 -20
0
20 40
80 100
60
V
– FORWARD VOLTAGE – V
F
T
– TEMPERATURE – C
A
Figure 4. Typical low level output current vs. tem-
perature.
Figure 5. Typical input diode forward characteristic.
PULSE GEN.
Z
= 50 Ω
r
O
t = t = 5 ns
f
SINGLE CHANNEL
DUAL CHANNEL
3.3 V
3.3 V
I
F
I
F
PULSE GEN.
V
V
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC
CC
Z
= 50 Ω
O
R
L
t
= t = 5 ns
f
r
INPUT
MONITORING
NODE
OUTPUT V
O
MONITORING
NODE
0.1 µF
BYPASS
R
L
0.1 µF
BYPASS
OUTPUT V
MONITORING
NODE
INPUT
MONITORING
NODE
O
*C
L
R
C *
L
M
R
M
GND
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
I
I
= 7.50 mA
= 3.75 mA
F
F
INPUT
I
F
t
t
PLH
PHL
OUTPUT
V
O
1.5 V
Figure 6. Test circuit for t and t
.
PHL
PLH
11
50
40
30
20
10
0
150
120
V
I
= 3.3 V
V
I
= 3.3 V
CC
= 7.5 mA
CC
= 7.5 mA
F
F
t
, R = 350 Ω
L
PLH
90
60
R
= 350 Ω
L
t
, R = 350 Ω
L
PHL
30
0
-60
-40 -20
0
20 40
80 100
60
-60 -40 -20
0
20 40
80 100
60
T
– TEMPERATURE – C
T
– TEMPERATURE – C
A
A
Figure 7. Typical propagation delay vs. temperature.
Figure 8. Typical pulse width distortion vs. temperature.
PULSE GEN.
Z
= 50 Ω
r
O
t = t = 5 ns
f
INPUT V
MONITORING NODE
E
+5 V
V
3.0 V
1.5 V
1
2
3
4
8
7
6
5
CC
INPUT
V
7.5 mA
E
0.1 µF
BYPASS
R
L
I
F
t
t
ELH
EHL
OUTPUT V
MONITORING
NODE
O
OUTPUT
V
O
1.5 V
*C
L
GND
*C IS APPROXIMATELY 15 pF WHICH INCLUDES
L
PROBE AND STRAY WIRING CAPACITANCE.
Figure 9. Test circuit for t and t
.
EHL
ELH
I
F
SINGLE CHANNEL
DUAL CHANNEL
B
A
I
F
V
V
+5 V
8
7
6
5
+5 V
1
2
3
4
8
7
6
5
1
2
3
4
CC
CC
R
B
A
L
OUTPUT V
MONITORING
NODE
O
0.1 µF
BYPASS
R
L
V
FF
OUTPUT V
MONITORING
NODE
O
V
0.1 µF
BYPASS
FF
GND
GND
V
V
CM
CM
+
–
+
–
PULSE
GENERATOR
PULSE
GENERATOR
Z
= 50 Ω
Z = 50 Ω
O
O
V
(PEAK)
(MIN.)
CM
V
CM
0 V
5 V
SWITCH AT A: I = 0 mA
F
CM
H
V
O
V
O
SWITCH AT B: I = 7.5 mA
F
V
(MAX.)
O
V
O
0.5 V
CM
L
Figure 10. Test circuit for common mode transient immunity and typical waveforms.
12
GND BUS (BACK)
V
BUS (FRONT)
NC
CC
ENABLE
OUTPUT
0.1µF
NC
10 mm MAX.
(SEE NOTE 5)
SINGLE CHANNEL
DEVICE ILLUSTRATED.
Figure 11. Recommended printed circuit board layout.
SINGLE CHANNEL DEVICE
3.3 V
3.3 V
8
6
V
CC1
V
CC2
R
L
220 Ω
I
F
+
2
3
D1*
V
0.1 µF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
V
E
7
1
2
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
3.3 V
3.3 V
8
7
V
CC1
V
CC2
R
L
220 Ω
I
F
+
1
2
D1*
V
0.1 µF
BYPASS
F
–
5
GND 1
GND 2
SHIELD
1
2
Figure 12. Recommended LVTTL interface circuit.
13
Application Information
Common-Mode Rejection for HCPL-260L Families:
Also, common-mode transients can capacitively couple
from the LED anode (or cathode) to the output-side
ground causing current to be shunted away from the LED
(which can be bad if the LED is on) or conversely cause
current to be injected into the LED (bad if the LED is meant
to be off). Figure 14 shows the parasitic capacitances
which exists between LED anode/cathode and output
Figure 13 shows the recommended drive circuit for optimal
common-mode rejection performance. Two main points to
note are:
1. The enable pin is tied to V rather than floating (this
CC
applies to single-channel parts only).
2. Two LED-current setting resistors are used instead of
one. This is to balance I
mode transients.
variation during common-
LED
ground (C and C ). Also shown in Figure 14 on the input
LA
LC
side is an AC-equivalent circuit.
If the enable pin is left floating, it is possible for common-
mode transients to couple to the enable pin, resulting in
common-mode failure. This failure mechanism only occurs
when the LED is on and the output is in the Low State.
It is identified as occurring when the transient output
voltage rises above 0.8 V. Therefore, the enable pin should
For transients occurring when the LED is on, common-
mode rejection (CMR , since the output is in the “low”
L
state) depends upon the amount of LED current drive (I ).
F
For conditions where I is close to the switching threshold
F
(I ), CMR also depends on the extent which I and I
TH
L
LP
LN
balance each other. In other words, any condition where
common-mode transients cause a momentary decrease
be connected to either V or logic-level high for best
CC
common-mode performance with the output low (CMR ).
L
in I will cause common-mode failure for transients which
F
This failure mechanism is only present in single-channel
parts which have the enable function.
are fast enough.
HCPL-260L
*
1
8
7
V
V
CC
CC+
0.01 µF
220 Ω
220 Ω
350 Ω
2
3
4
6
5
V
O
74LS04
OR ANY TOTEM-POLE
OUTPUT LOGIC GATE
GND
SHIELD
*
GND1
GND2
* HIGHER CMR MAY BE OBTAINABLE BY CONNECTING PINS 1, 4 TO INPUT GROUND (GND1).
Figure 13. Recommended drive circuit for High-CMR.
1
2
8
7
V
V
+
CC
1/2 R
1/2 R
0.01 µF
LED
350 Ω
I
LP
LED
C
I
LA
LN
3
4
6
5
O
15 pF
C
LC
GND
SHIELD
+
–
V
CM
Figure 14. AC equivalent circuit.
14
V
Likewise for common-mode transients which occur when
the LED is off (i.e. CMR , since the output is “high”), if an
CC
H
HCPL-260L
imbalance between I and I results in a transient I
equal to or greater than the switching threshold of the
optocoupler, the transient“signal”may cause the output to
LP
LN
F
1
2
420 Ω
(MAX)
2N3906
(ANY PNP)
spike below 2 V (which constitutes a CMR failure).
H
74L504
(ANY
LED
TTL/CMOS
GATE)
By using the recommended circuit in Figure 13, good CMR
3
4
can be achieved. The balanced I -setting resistors help
LED
equalize I and I to reduce the amount by which I is
LP
LN
LED
modulated from transient coupling through C and C
.
LC
LA
CMR with Other Drive Circuits
CMR performance with drive circuits other than that
shown in Figure 13 may be enhanced by following these
guidelines:
Figure 15. TTL interface circuit.
1. Use of drive circuits where current is shunted from the
LED in the LED “off” state (as shown in Figures 15 and
V
CC
HCPL-260L
1
2
16). This is beneficial for good CMR .
H
R
2. Use of I > 3.5 mA. This is good for high CMR .
FH
L
74HC00
(OR ANY
OPEN-COLLECTOR/
OPEN-DRAIN
Figure 15 shows a circuit which can be used with any
totem-pole-output TTL/LSTTL/HCMOS logic gate. The
buffer PNP transistor allows the circuit to be used with
logic devices which have low current-sinking capability. It
also helps maintain the driving-gate power-supply current
at a constant level to minimize ground shifting for other
devices connected to the input-supply ground.
LED
3
4
LOGIC GATE)
When using an open-collector TTL or open-drain CMOS
logic gate, the circuit in Figure 16 may be used. When using
a CMOS gate to drive the optocoupler, the circuit shown in
Figure 16. TTL open-collector/open drain gate drive circuit.
Figure 17 may be used. The diode in parallel with the R
speeds the turn-off of the optocoupler LED.
LED
V
CC
HCPL-260L
1N4148
1
2
220 Ω
74HC04
(OR ANY
LED
TOTEM-POLE
OUTPUT LOGIC
GATE)
3
4
Figure 17. CMOS gate drive circuit.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0581EN
AV02-0616EN - July 24, 2007
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