HCPL-4504-560E [AVAGO]
High CMR, High Speed Optocouplers; 高CMR ，高速光电耦合器
| 型号： | HCPL-4504-560E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | High CMR, High Speed Optocouplers |
| 文件： | 总19页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-4504/J454/0454, HCNW4504
High CMR, High Speed Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
• Short propagation delays for TTL and IPM applications
The HCPL-4504 and HCPL-0454 contain a GaAsP LED
while the HCPL-J454 and HCNW4504 contain an AlGaAs • 15 kV/μs minimum Common Mode Transient immu-
LED. The LED is optically coupled to an integrated high
nity at VCM = 1500 V for TTL/load drive
gain photo detector.
• High CTR at TA = 25°C
>25% for HCPL-4504/0454
>23% for HCNW4504
>19% for HCPL-J454
The HCPL-4504 series has short propagation delays and
high CTR. The HCPL-4504 series also has a guaranteed
propagation delay difference (tPLH-tPHL). These features
make the HCPL-4504 series an excellent solution to IPM
• Electrical specifications for common IPM applications
inverter dead time and other switching problems. The • TTL compatible
CTR, propagation delay, and CMR are specified both for
TTL and IPM conditions which are provided for ease of
application. These single channel, diode-transistor opto-
couplers are available in 8-Pin DIP, SO-8, and Widebody
package configurations. An insulating layer between a
LED and an integrated photodetector provide electrical
insulation between input and output. Separate connec-
tions for the photodiode bias and output-transistor col-
lector increase the speed up to a hundred times that of
a conventional phototransistor coupler by reducing the
base collector capacitance.
• Open collector output
• Safety approval:
UL recognized
– 3750 V rms/1min. for HCPL-4504/0454/J454
– 5000 V rms/1min. for HCPL-4504 Option 020 and
HCNW4504
CSA approved
IEC/EN/DIN EN 60747-5-2 approved
– VIORM = 560 Vpeak for HCPL-0454 Option 060
– VIORM = 630 Vpeak for HCPL-4504 Option 060
– VIORM = 891 Vpeak for HCPL-J454
Functional Diagram
– VIORM = 1414 Vpeak for HCNW4504
Applications
8
7
6
5
NC
ANODE
CATHODE
NC
1
2
3
4
V
CC
• Inverter circuits and Intelligent Power Module (IPM)
interfacing: High Common Mode Transient immunity
(> 10 kV/μs for an IPM load/drive) and (tPLH - tPHL
Specified (see Power Inverter Dead Time section)
TRUTH TABLE
NC
LED
V
O
)
ON
OFF
LOW
HIGH
V
O
• Line receivers: Short propagation delays and low in-
put-output capacitance
GND
• High speed logic ground isolation: TTL/TTL, TTL/
CMOS, TTL/LSTTL
A 0.1 μF bypass capacitor between pins 5 and 8 is recommended.
Schematic
• Replaces pulse transformers: Save board space and
weight
I
CC
8
V
CC
• Analog signal ground isolation: Integrated photode-
tector provides improved linearity over phototransis-
tors
I
F
+
2
ANODE
V
F
I
O
6
5
–
3
V
O
CATHODE
SHIELD
GND
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
HCPL-0454, HCPL-4504 and HCPL-J454 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
HCNW4504 is UL Recognized with 5000 Vrms for 1 minute per UL1577. HCPL-0454, HCPL-4504, HCPL-J454 and
HCNW4504 are approved under CSA Component Acceptance Notice #5, File CA 88324.
UL 1577
Option
non RoHS
Compliant Compliant
5000 Vrms/
1 Minute
rating
Part
RoHS
Surface
Mount
Gull
Wing
Tape
& Reel
IEC/EN/DIN
Number
Package
EN 60747-5-2 Quantity
-000E
-300E
-500E
-020E
-320E
-520E
-060E
-360E
-560E
-000E
-300E
-400E
-500E
-600E
-000E
-500E
-060E
-560E
-000E
-300E
-500E
no option
#300
50 per tube
X
X
X
X
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
1000 per reel
50 per tube
50 per tube
50 per tube
1000 per reel
750 per reel
100 per tube
1500 per reel
100 per tube
1500 per reel
42 per tube
42 per tube
750 per reel
#500
X
X
X
#020
X
X
X
300 mil
DIP-8
HCPL-4504
#320
X
X
X
X
#520
#060
X
X
X
X
X
X
X
X
#360
X
X
X
X
#560
no option
#300
X
X
X
X
X
X
X
X
X
X
X
X
300 mil
DIP-8
HCPL-J454
NA
#500
X
X
NA
no option
#500
X
X
HCPL-0454
HCNW4504
SO-8
#060
X
X
X
X
X
#560
no option
#300
X
X
X
400 mil
Widebody
DIP-8
X
X
X
X
#500
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-4504-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging
with IEC/EN/DIN EN 60747-5-2 Safety Approval and RoHS compliant.
Example 2:
HCPL-4504 to order product of 300 mil DIP package in Tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’is used for existing products, while (new) products launched since July 15, 2001 and
RoHS compliant will use ‘–XXXE.’
2
Package Outline Drawings
HCPL-4504 Outline Drawing
7.62 0.25
(0.300 0.010ꢀ
9.65 0.25
(0.380 0.010ꢀ
8
1
7
6
5
6.35 0.25
(0.250 0.010ꢀ
TYPE NUMBER
OPTION CODE*
DATE CODE
A XXXXZ
YYWW
U R
UL
2
3
4
RECOGNITION
1.78 (0.070ꢀ MAX.
1.19 (0.047ꢀ MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003ꢀ
- 0.002ꢀ
3.56 0.13
(0.140 0.005ꢀ
(0.010
4.70 (0.185ꢀ MAX.
0.51 (0.020ꢀ MIN.
2.92 (0.115ꢀ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢀ.
1.080 0.320
(0.043 0.013ꢀ
0.65 (0.025ꢀ MAX.
* MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.54 0.25
(0.100 0.010ꢀ
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
HCPL-4504 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
1.016 (0.040ꢀ
9.65 0.25
(0.380 0.010ꢀ
6
5
8
1
7
6.350 0.25
(0.250 0.010ꢀ
10.9 (0.430ꢀ
2
3
4
2.0 (0.080ꢀ
1.27 (0.050ꢀ
9.65 0.25
1.780
(0.070ꢀ
MAX.
(0.380 0.010ꢀ
1.19
(0.047ꢀ
MAX.
7.62 0.25
(0.300 0.010ꢀ
+ 0.076
0.254
- 0.051
3.56 0.13
(0.140 0.005ꢀ
+ 0.003ꢀ
- 0.002ꢀ
(0.010
1.080 0.320
(0.043 0.013ꢀ
0.635 0.25
(0.025 0.010ꢀ
12° NOM.
0.635 0.130
(0.025 0.005ꢀ
2.54
(0.100ꢀ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
3
Package Outline Drawings
HCPL-J454 Outline Drawing
7.62 0.25
(0.300 0.010ꢀ
9.80 0.25
(0.386 0.010ꢀ
8
7
6
5
6.35 0.25
(0.250 0.010ꢀ
TYPE NUMBER
DATE CODE
A XXXX
YYWW
U R
UL
1
2
3
4
RECOGNITION
1.78 (0.070ꢀ MAX.
1.19 (0.047ꢀ MAX.
+ 0.076
- 0.051
0.254
5 TYP.
+ 0.003ꢀ
- 0.002ꢀ
3.56 0.13
(0.140 0.005ꢀ
(0.010
4.70 (0.185ꢀ MAX.
0.51 (0.020ꢀ MIN.
2.92 (0.115ꢀ MIN.
DIMENSIONS IN MILLIMETERS AND (INCHESꢀ.
1.080 0.320
(0.043 0.013ꢀ
0.65 (0.025ꢀ MAX.
OPTION NUMBERS 300 AND 500 NOT MARKED.
2.54 0.25
(0.100 0.010ꢀ
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 milsꢀ MAX.
HCPL-J454 Gull Wing Surface Mount Option 300 Outline Drawing
LAND PATTERN RECOMMENDATION
1.016 (0.040ꢀ
9.80 0.25
(0.386 0.010ꢀ
6
5
8
1
7
6.350 0.25
(0.250 0.010ꢀ
10.9 (0.430ꢀ
2
3
4
2.0 (0.080ꢀ
1.27 (0.050ꢀ
9.65 0.25
1.780
(0.070ꢀ
MAX.
(0.380 0.010ꢀ
1.19
(0.047ꢀ
MAX.
7.62 0.25
(0.300 0.010ꢀ
+ 0.076
0.254
- 0.051
3.56 0.13
(0.140 0.005ꢀ
+ 0.003ꢀ
- 0.002ꢀ
(0.010
1.080 0.320
(0.043 0.013ꢀ
0.635 0.25
(0.025 0.010ꢀ
12° NOM.
0.635 0.130
(0.025 0.005ꢀ
2.54
(0.100ꢀ
BSC
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 milsꢀ MAX.
4
HCPL-J454-400E/600E Widelead Gullwing Surface Mount Outline Drawing
LAND PATTERN RECOMMENDATION
9.80 ±0.25
0.386 ±0.010
1.016
0.040
TYPE NUMBER
12.9
0.508
A XXXX
6.35 ±0.25
DATE CODE
0.250 ±0.010
YYWW
U R
1.27
0.050
UL
RECOGNITION
2.0
0.08
[0.65] 0.025 MAX
[11.75 0.25]
0.460 0.010
[1.19]
0.047
MAX.
7.62 ±0.51
0.300±0.020
[0.20] 0.008
[0.33] 0.013
3.56 ±0.13
0.140 ±0.005
[0.152] 0.006
[0.406] 0.016
[1.080] 0.320
0.043 0.013
0.625 ±0.254
0.025 ±0.010
2.54
0.100
BSC
30° NOM.
LEAD COPLANARITY
MAXIMUM: [0.102] 0.004
DIMENSIONS IN [MILLIMETERS] INCHES
OPTION NUMBERS 400 AND 600 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
HCPL-0454 Outline Drawing (8-Pin Small Outline Package)
LAND PATTERN RECOMMENDATION
8
1
7
2
6
5
4
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
7.49 (0.295ꢀ
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
3
1.9 (0.075ꢀ
PIN ONE
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
0.64 (0.025ꢀ
0.432
(0.017)
*
7
5.080 ± 0.127
(0.200 ± 0.005)
45 X
3.175 ± 0.127
(0.125 ± 0.005)
0 ~ 7
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
*
0.305
(0.012)
MIN.
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
5
HCNW4504 Outline Drawing (8-Pin Widebody Package)
11.00
(0.433ꢀ
11.15 0.15
(0.442 0.006ꢀ
MAX.
9.00 0.15
(0.354 0.006ꢀ
7
6
5
8
TYPE NUMBER
DATE CODE
A
HCNWXXXX
YYWW
1
3
2
4
10.16 (0.400ꢀ
TYP.
1.55
(0.061ꢀ
MAX.
7° TYP.
+ 0.076
- 0.0051
0.254
+ 0.003ꢀ
- 0.002ꢀ
(0.010
5.10
(0.201ꢀ
MAX.
3.10 (0.122ꢀ
3.90 (0.154ꢀ
0.51 (0.021ꢀ MIN.
2.54 (0.100ꢀ
TYP.
1.78 0.15
(0.070 0.006ꢀ
0.40 (0.016ꢀ
0.56 (0.022ꢀ
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
HCNW4504 Gull Wing Surface Mount Option 300 Outline Drawing
11.15 0.15
(0.442 0.006ꢀ
LAND PATTERN RECOMMENDATION
7
6
5
8
9.00 0.15
(0.354 0.006ꢀ
13.56
(0.534ꢀ
1
3
2
4
2.29
(0.09ꢀ
1.3
(0.051ꢀ
12.30 0.30
1.55
(0.061ꢀ
MAX.
(0.484 0.012ꢀ
11.00
MAX.
(0.433ꢀ
4.00
MAX.
(0.158ꢀ
1.78 0.15
(0.070 0.006ꢀ
1.00 0.15
(0.039 0.006ꢀ
0.75 0.25
(0.030 0.010ꢀ
+ 0.076
- 0.0051
2.54
(0.100ꢀ
BSC
0.254
+ 0.003ꢀ
- 0.002ꢀ
(0.010
DIMENSIONS IN MILLIMETERS (INCHESꢀ.
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHESꢀ.
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 milsꢀ MAX.
6
Solder Reflow Temperature Profile
300
PREHEATING RATE 3 °C + 1 °C/–0.5 °C/SEC.
REFLOW HEATING RATE 2.5 °C 0.5 °C/SEC.
PEAK
TEMP.
245 °C
PEAK
TEMP.
240 °C
PEAK
TEMP.
230 °C
200
100
0
2.5 C 0.5 °C/SEC.
SOLDERING
30
TIME
160 °C
150 °C
140 °C
SEC.
200 °C
30
SEC.
3 °C + 1 °C/–0.5 °C
PREHEATING TIME
150 °C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
ROOM
TEMPERATURE
LOOSE
0
50
100
150
200
250
TIME (SECONDS)
NOTE: NON-HALIDE FLUX SHOULD BE USED.
Recommended Pb-Free IR Profile
TIMEWITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
tp
15 SEC.
* 260 +0/-5 °C
RAMP-UP
Tp
217 °C
TL
RAMP-DOWN
6 °C/SEC. MAX.
3 °C/SEC. MAX.
150 - 200 °C
Tsmax
Tsmin
ts
tL
PREHEAT
60 to 150 SEC.
60 to 180 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THETIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
NOTE: NON-HALIDE FLUX SHOULD BE USED.
* RECOMMENDED PEAK TEMPERATURE FORWIDEBODY 400mils PACKAGE IS 245 °C
7
Regulatory Information
The devices contained in this data sheet have been approved by the following agencies:
Agency/Standard
HCPL-4504
HCPL-J454
HCPL-0454
HCNW4504
UL1577
3750 Vrms /
1 minute,
3750 Vrms /
1 minute
3750 Vrms /
1 minute
5000 Vrms /
1 minute
Underwriters Laboratories (UL)
Recognized under UL1577,
Option 020 5000
Vrms / 1 minute
Component Recognition Program,
Category FPQU2, File E55361
Component 3750 Vrms /
3750 Vrms /
1 minute
3750 Vrms /
1 minute
5000 Vrms /
1 minute
Canadian Standards Association (CSA)
File CA88324
Acceptance
Notice #5
1 minute,
Option 020 5000
Vrms / 1 minute
Option 060
VIORM = 630 Vpeak
VIORM = 891
Vpeak
Option 060
VIORM = 560
Vpeak
VIORM = 1414
Vpeak
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01
Insulation and Safety Related Specifications
Value
HCPL-
J454
HCPL-J454
All other
HCPL-
HCPL-
HCNW
Parameter
Symbol
4504 -400E/-600E options
0454
4504 Units Conditions
Minimum External
Air Gap
(External Clearance)
L(101)
7.1
8.0
7.4
8.0
4.9
9.6
mm Measured from input ter-
minals to output terminals,
shortest distance through air.
Minimum External
Tracking
(External Creepage)
L(102)
7.4
8.0
4.8
10.0
mm Measured from input ter-
minals to output terminals,
shortest distance path along
body.
Minimum Internal
Plastic Gap
0.08
0.5
0.5
0.08
1.0
mm Through insulation distance,
conductor to conductor,
(Internal Clearance)
usually the direct distance
between the photoemitter
and photodetector inside the
optocoupler cavity.
Minimum Internal
Tracking (Internal
Creepage)
NA
≥175
IIIa
NA
≥175
IIIa
NA
≥175
IIIa
NA
≥175
IIIa
4.0
mm Measured from input ter-
minals to output terminals,
along internal cavity.
Tracking Resistance
(Comparative
Tracking Index)
CTI
≥200 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa
Material Group (DIN VDE
0110, 1/89, Table 1)
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These di-
mensions are needed as a starting point for the equip-
ment designer when determining the circuit insulation
requirements.
creepage, the shortest distance path along the surface
of a printed circuit board between the solder fillets of
the input and output leads must be considered. There
are recommended techniques such as grooves and ribs
which may be used on a printed circuit board to achieve
desired creepage and clearances. Creepage and clear-
ance distances will also change depending on factors
such as pollution degree and insulation level.
However, once mounted on a printed circuit board, mini-
mum creepage and clearance requirements must be
met as specified for individual equipment standards. For
8
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
HCPL-0454
OPTION 060
HCPL-4504
OPTION 060
Description
Symbol
HCPL-J454
HCNW4504
Unit
Installation classification per
DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
for rated mains voltage ≤450 V rms
for rated mains voltage ≤600 V rms
for rated mains voltage ≤1000 V rms
I-IV
I-III
I-IV
I-IV
I-III
I-IV
I-IV
I-III
I-III
I-IV
I-IV
I-IV
I-IV
I-III
Climatic Classification
55/100/21
55/100/21
55/100/21
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
2
2
2
V
IORM
560
630
891
1414
V peak
V peak
V
IORM x 1.875 = VPR, 100% Production
VPR
1050
840
1181
945
1670
1336
6000
2652
2121
8000
Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample
VPR
V peak
Test, tm = 60 sec,
Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values - Maximum
Values Allowed in the Event of a Failure,
also see Thermal Derating curve
VIOTM
4000
6000
V peak
Case Temperature
Input Current
TS
150
150
600
≥109
175
230
600
≥109
175
400
600
≥109
150
400
700
≥109
°C
IS,INPUT
PS,OUTPUT
RS
mA
mW
Ω
Output Power
Insulation Resistance at TS,
VIO = 500 V
*Refer to the optocoupler section of the Designer's Catalog, under regulatory information (IEC/EN/DIN EN 60747-5-2) for a detailed description of
Method a and Method b partial discharge test profiles.
NOTE: These optocouplers are suitable for "safe electrical isolation" only within the safety limit data. Maintenance of the safety data shall be ensured
by means of protective circuits.
NOTE: Insulation Characteristics are per IEC/EN/DIN EN 60747-5-2.
NOTE: Surface mount classification is Class A in accordance with CECC 00802.
9
Absolute Maximum Ratings
Parameter
Symbol
TS
Device
Min.
-55
-55
Max.
125
100
Units
°C
Note
Storage Temperature
Operating Temperature
TA
HCPL-4504
HCPL-0454
HCPL-J454
°C
HCNW4504
-55
85
25
50
Average Forward Input Current
IF(AVG)
mA
mA
1
2
Peak Forward Input Current
IF(PEAK)
HCPL-4504
HCPL-0454
(50% duty cycle, 1 ms pulse width)
HCPL-J454
HCNW4504
40
1
Peak Transient Input Current
(≤1 μs pulse width, 300 pps)
IF(TRANS)
HCPL-4504
HCPL-0454
A
HCPL-J454
HCNW4504
0.1
5
Reverse LED Input Voltage (Pin 3-2)
Input Power Dissipation
VR
HCPL-4504
HCPL-0454
V
HCPL-J454
HCNW4504
3
PIN
HCPL-4504
HCPL-0454
45
40
mW
3
HCPL-J454
HCNW4504
Average Output Current (Pin 6)
Peak Output Current
IO(AVG)
IO(PEAK)
VCC
8
mA
mA
V
16
30
20
100
260
Supply Voltage (Pin 8-5)
Output Voltage (Pin 6-5)
Output Power Dissipation
-0.5
-0.5
VO
V
PO
mW
°C
4
Lead Solder Temperature
(Through-Hole Parts Only)
TLS
HCPL-4504
HCPL-J454
1.6 mm below seating plane, 10 seconds
Up to seating plane, 10 seconds
Reflow Temperature Profile
HCNW4504
260
TRP
HCPL-0454,
Option 300 ,
Option 500,
Option 400E
& Option 600E.
See Package Outline Drawings
section
10
Electrical Specifications (DC)
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. See note 12.
Parameter
Symbol Device
Min. Typ.*
Max. Units
Test Conditions
Fig.
Note
Current
Transfer
Ratio
CTR
CTR
VOL
HCPL-4504
HCPL-0454
25
21
19
13
23
19
26
22
21
16
25
21
32
34
37
39
29
31
35
37
43
45
33
35
0.2
60
60
%
%
V
TA = 25°C
VO = 0.4 V
VO = 0.5 V
IF = 16 mA,
VCC = 4.5 V
1, 2,
4
5
HCPL-J454
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
VO = 0.4 V
VO = 0.5 V
VO = 0.4 V
VO = 0.5 V
VO = 0.4 V
VO = 0.5 V
VO = 0.4 V
VO = 0.5 V
VO = 0.4 V
VO = 0.5 V
IO = 4.0 mA
IO = 3.3 mA
IO = 3.6 mA
IO = 3.0 mA
IO = 3.6 mA
IO = 3.0 mA
VO = VCC = 5.5 V
VO = VCC = 15 V
HCNW4504
60
63
65
Current
Transfer
Ratio
HCPL-4504
HCPL-0454
IF = 12 mA,
VCC = 4.5 V
1, 2,
4
5
HCPL-J454
65
HCNW4504
65
68
Logic Low
Output
Voltage
HCPL-4504
HCPL-0454
0.4
0.5
0.4
IF = 16 mA,
VCC = 4.5 V
HCPL-J454
0.2
0.5
0.2
0.5
HCNW4504
0.4
Logic High
Output
Current
IOH
0.003 0.5
μA
μA
TA = 25°C
TA = 25°C
IF = 0 mA
5
0.01
1
50
200
Logic Low
Supply
Current
ICCL
HCPL-4504
HCPL-0454
HCNW4504
50
IF = 16 mA, VO = Open, VCC = 15 V
12
HCPL-J454
70
Logic High
Supply Current
ICCH
0.02
1.5
1
μA
V
TA = 25°C
TA = 25°C
TA = 25°C
IR = 10 μA
IR = 100 μA
IF = 0 mA, VO = Open,
12
3
2
VCC = 15 V
IF = 16 mA
Input Forward
Voltage
VF
HCPL-4504
HCPL-0454
1.7
1.8
1.85
1.95
HCPL-J454
HCNW4504
1.45 1.59
IF = 16 mA
1.35
5
Input Reverse
Breakdown
Voltage
BVR
HCPL-4504
HCPL-0454
V
HCPL-J454
HCNW4504
3
Temperature
Coefficient
of Forward
Voltage
∆VF
∆TA
HCPL-4504
HCPL-0454
-1.6
-1.4
60
mV/°C IF = 16 mA
HCPL-J454
HCNW4504
Input
Capacitance
CIN
HCPL-4504
HCPL-0454
pF
f = 1 MHz, VF = 0 V
HCPL-J454
HCNW4504
70
*All typicals at TA = 25°C.
11
AC Switching Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Parameter
Symbol Device Min.
Typ.
0.2
0.2
Max. Units
Test Conditions
Fig.
Note
Propagation Delay tPHL
Time to Logic Low
at Output
0.3
0.5
μs
μs
μs
μs
μs
TA = 25°C
Pulse: f = 20 kHz,
Duty Cycle = 10%,
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
VTHHL = 1.5 V
6,
8, 9
9
tPHL
0.2
0.5
0.7
1.0
TA = 25°C
TA = 25°C
TA = 25°C
Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHHL = 1.5 V
6,
10-14
10
9
HCPL- 0.05
J454
Others 0.1
Propagation Delay tPLH
Time to Logic High
at Output
0.3
0.3
0.5
0.7
Pulse: f = 20 kHz,
Duty Cycle = 10%,
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
6,
8, 9
V
THLH = 1.5 V
tPLH
0.3
0.2
0.8
0.8
1.1
1.4
Pulse: f = 10 kHz,
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
6,
10-14
10
17
V
THLH = 2.0 V
Propagation Delay tPLH
Difference Be-
tween Any 2 Parts
-
-0.4
-0.7
0.3
0.3
0.9
1.3
TA = 25°C Pulse: f = 10 kHz,
Duty Cycle = 50%,
6,
10-14
tPHL
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
VTHHL = 1.5 V, VTHLH = 2.0 V
Common Mode
Transient Immu-
nity at Logic High
|CMH|
|CMH|
|CML|
15
15
15
30
30
30
30
kV/μs TA = 25°C
VCM
1500 VP-P
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 0 mA
7
7
7
7
7, 9
=
kV/μs
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 0 mA
8, 10
7, 9
Level Output
kV/μs TA = 25°C
VCM
1500 VP-P
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 16 mA
Common Mode
Transient Immu-
nity at Logic Low
Level Output
=
|CML| HCPL- 15
J454
kV/μs
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 12 mA
8, 10
Others 10
|CML|
15
30
kV/μs
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 16 mA
7
8, 10
*All typicals at TA = 25°C.
12
Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise specified.
Parameter
Symbol
Device
Min.
Typ.*
Max.
Units
Test Conditions
Figure
Note
Input-Output
Momentary
Withstand
Voltage†
V
ISO
HCPL-4504
HCPL-0454
3750
V rms
RH ≤50%,
t = 1 min.,
TA = 25°C
6, 13,
16
HCPL-J454
3750
5000
5000
6, 14,
16
HCPL-4504
Option 020
6, 11,
15
HCNW4504
6, 15,
16
Input-Output
Resistance
RI-O
HCPL-4504
HCPL-0454
HCPL-J454
1012
Ω
VI-O = 500 Vdc
6
6
HCNW4504
1012
1011
1013
0.6
TA = 25°C
TA = 100°C
f = 1 MHz
Capacitance
(Input-Output)
CI-O
HCPL-4504
HCPL-0454
pF
HCPL-J454
HCNW4504
0.8
0.5
0.6
All typicals at TA = 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Table (if applicable), your
equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on
the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e.,V >2.0 V). Common mode
O
transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal,
VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is the maximum
tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 3.0
V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on the trailing edge of the common mode pulse
signal, VCM, to assure that the output will remain in a Logic Low state (i.e.,VO <1.0V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 μF bypass capacitor connected between Pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (leakage detection
current limit, Ii-o ≤5 μA).
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥4500V rms for 1 second (leakage detection
current limit, Ii-o ≤ 5 μA).
15. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000V rms for 1 second (leakage detection
current limit, Ii-o ≤5 μA).
16. This test is performed before the 100% Production test shown in the VDE 0884 Insulation Related Characteristics Table, if applicable.
17. The difference between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power Inverter Dead
Time and Propagation Delay Specifications section.)
13
HCPL-4504/0454
HCNW4504
HCPL-J454
= 25° C
25
20
15
10
40 mA
35 mA
T
CC
= 25°C
T = 25°C
A
CC
A
T
V
A
10
20
18
16
14
12
10
8
V
= 5.0 V
V
= 5.0 V
= 5.0 V
CC
40 mA
35 mA
40 mA
35 mA
30 mA
25 mA
20 mA
30 mA
25 mA
20 mA
30 mA
25 mA
20 mA
5
15 mA
10 mA
15 mA
10 mA
15 mA
10 mA
6
5
0
4
I
= 5 mA
F
I
= 5 mA
F
2
0
I
= 5 mA
F
0
0
20
0
20
10
– OUTPUT VOLTAGE – V
10
V – OUTPUT VOLTAGE – V
O
0
5
10
15
20
V
– OUTPUT VOLTAGE – V
O
V
O
Figure 1. DC and pulsed transfer characteristics.
HCPL-4504/0454
1.5
HCPL-J454
HCNW4504
NORMALIZED
2.0
1.5
1.0
0.5
0
NORMALIZED
2.0
1.6
1.2
0.8
0.4
0
I
= 16 mA
F
O
I
V
V
= 16 mA
F
V
= 0.4 V
= 5.0 V
= 25°C
= 0.4 V
O
V
T
CC
= 5.0 V
CC
1.0
A
T
= 25° C
A
0.5
0.0
NORMALIZED
= 16 mA
I
F
V
= 0.4 V
O
V
= 5.0 V
CC
T
= 25°C
A
0
2
4
I
6
8 10 12 14 16 18 20 22 24 26
0
5
10
15
20
25
0
5
10
15
20
25
I
– INPUT CURRENT – mA
– INPUT CURRENT – mA
F
I
– INPUT CURRENT – mA
F
F
Figure 2. Current transfer ratio vs. input current.
HCPL-4504/0454
1000
HCPL-J454/HCNW4504
= 25°C
1000
100
10
T
A
100
I
I
F
F
T
A
= 25°C
+
+
10
1.0
V
V
F
F
–
–
1.0
0.1
0.1
0.01
0.001
0.01
0.001
1.1
1.2
1.3
1.4
1.5
1.6
1.6
– FORWARD VOLTAGE – VOLTS
F
1.7
1.2
1.3
1.4
1.5
V
– FORWARD VOLTAGE – VOLTS
V
F
Figure 3. Input current vs. forward voltage.
14
HCPL-4504/0454
HCNW4504
NORMALIZED
HCPL-J454
1.1
1.0
1.05
1.0
1.05
1.0
NORMALIZED
= 16 mA
I
= 16 mA
F
O
I
F
O
CC
A
V
= 0.4 V
V
V
T
= 0.4 V
= 5.0 V
= 25° C
V
= 5.0 V
= 25°C
CC
T
A
0.9
0.8
0.7
0.6
NORMALIZED
= 16 mA
0.95
0.9
0.95
0.9
I
F
V
= 0.4 V
O
V
= 5.0 V
CC
= 25°C
T
A
0.85
0.85
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100 120
T – TEMPERATURE – °C
A
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 4. Current transfer ratio vs. temperature.
4
10
3
10
I
V
= 0 mA
F
= V = 5.0 V
O
CC
2
10
1
0
10
10
-1
10
10
-2
-60 -40 -20
0
20 40 60 80 100 120
T
– TEMPERATURE – °C
A
Figure 5. Logic high output current vs. temperature.
I
F
I
PULSE
GEN.
F
8
7
6
5
1
2
3
4
V
CC
0
Z
t
= 50 Ω
O
r
= 5 ns
R
V
L
CC
V
O
V
O
V
V
THLH
THHL
0.1µF
V
I
MONITOR
F
OL
C
L
R
M
t
t
PHL
PLH
Figure 6. Switching test circuit.
8
7
6
5
V
CC
1
2
3
4
V
CM
90% 90%
I
F
0 V
10%
10%
R
L
t
r
A
t
f
B
V
O
0.1µF
V
V
O
CC
SWITCH AT A: I = 0 mA
F
C
L
V
FF
V
V
+
O
V
CM
OL
–
SWITCH AT B: I = 12 mA, 16 mA
F
PULSE GEN.
Figure 7. Test circuit for transient immunity and typical waveforms.
15
HCPL-4504/0454
= 5.0 V
R = 1.9 kΩ
HCPL-J454/HCNW4504
= 5.0 V
R = 1.9 kΩ
0.50
0.45
0.50
0.45
1.4
1.2
1.0
0.8
V
V
= 5.0 V
= 25° C
= 15 pF
= V
V
CC
CC
CC
T
L
A
L
C = 15 pF
C
V
C = 15 pF
L
L
L
0.40
0.40
V
= V
= 1.5 V
= 1.5 V
THLH
V
= V
= 1.5 V
THLH
THHL
THLH
THHL
THHL
t
t
PLH
PLH
10% DUTY CYCLE
10% DUTY CYCLE
10% DUTY CYCLE
t
0.35
0.30
0.25
0.35
0.30
0.25
PLH
t
PHL
t
0.6
0.4
0.2
0.0
PHL
I
= 10 mA
= 16 mA
F
t
PHL
I
F
0.20
0.20
I
= 10 mA
= 16 mA
I
= 10 mA
= 16 mA
F
F
0.15
0.10
0.15
0.10
I
I
F
F
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100 120
0
2
4
6
8
– LOAD RESISTANCE – kΩ
L
10 12 14 16 18 20
R
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 8. Propagation delay time vs. temperature.
Figure 9. Propagation delay time vs. load resis-
tance.
HCPL-4504/0454
HCPL-J454/HCNW4504
1.1
2.6
2.4
1.1
1.0
V
= 15.0 V
V
= 5.0 V
= 25° C
= 100 pF
I
= 10 mA
I = 16 mA
F
V
R
= 15.0 V
= 20 kΩ
I
= 10 mA
I = 16 mA
F
CC
CC
F
CC
L
F
R
= 20 kΩ
T
1.0
0.9
L
A
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
C = 100 pF
C
C = 100 pF
L
L
L
0.9
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
50% DUTY CYCLE
THHL
THLH
THHL
THLH
THHL
THLH
t
t
PLH
PLH
0.8
0.7
0.6
0.8
0.7
0.6
50% DUTY CYCLE
50% DUTY CYCLE
t
PLH
I
= 10 mA
I = 16 mA
F
F
t
PHL
8
0.5
0.5
t
t
PHL
PHL
0.4
0.3
0.4
0.3
0.2
0.0
-60 -40 -20
0
20 40
-60 -40 -20
0
20 40
60 80 100 120
60 80 100 120
T – TEMPERATURE – °C
A
0
2
4
6
10 12 14 16 18 20
T
– TEMPERATURE – °C
R – LOAD RESISTANCE – kΩ
A
L
Figure 10. Propagation delay time vs. load
resistance.
Figure 11. Propagation delay time vs. temperature.
1.8
3.5
1.2
1.1
1.0
V
= 15.0 V
V
= 15.0 V
= 25° C
T = 25° C
A
L
CC
= 25° C
CC
t
PLH
PHL
1.6
1.4
T
T
R = 20 kΩ
A
A
3.0
2.5
2.0
1.5
1.0
0.5
C = 100 pF
R = 20 kΩ
C = 100 pF
L
L
L
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
THHL
THLH
THHL
THLH
THHL
THLH
0.9
0.8
0.7
1.2
1.0
0.8
0.6
0.4
t
PLH
50% DUTY CYCLE
50% DUTY CYCLE
50% DUTY CYCLE
t
PLH
t
t
0.6
0.5
0.4
0.3
0.2
PHL
t
PHL
I
= 10 mA
= 16 mA
F
I
I
= 10 mA
= 16 mA
F
I
I
= 10 mA
= 16 mA
F
F
I
0.2
0.0
F
F
0.0
0
100 200 300 400 500 600 700 800 9001000
– LOAD CAPACITANCE – pF
10 11 12 13 14 15 16 17 18 19 20
– SUPPLY VOLTAGE – V
0
5
10 15 20 25 30 35 40 45 50
C
R
– LOAD RESISTANCE – kΩ
V
CC
L
L
Figure 12. Propagation delay time vs. load
resistance.
Figure 13. Propagation delay time vs. load
capacitance.
Figure 14. Propagation delay time vs. supply
voltage.
16
HCPL-4504 OPTION 060/HCPL-J454
HCPL-0454 OPTION 060/HCNW4504
1000
800
700
600
500
400
300
P
(mWꢀ for HCNW4504
(mAꢀ for HCNW4504
(mWꢀ for HCPL-0454
S
P
(mWꢀ
S
900
800
700
600
500
400
300
I
P
S
I
(mAꢀ for HCPL-4504
OPTION 060
(mAꢀ for HCPL-J454
S
S
OPTION 060
I
S
I
(mAꢀ for HCPL-0454
S
OPTION 060
(230ꢀ
200
200
(150ꢀ
100
100
0
0
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
0
25
50 75 100 125 150 175
T
T – CASE TEMPERATURE – °C
S
S
Figure 15. Thermal derating curve, dependence of safety limiting valve with case temperature per
IEC/EN/DIN EN 60747-5-2.
+HV
+
HCPL-4504/0454/J454
HCNW4504
8
7
6
2
3
LED 1
BASE/GATE
DRIVE CIRCUIT
Q1
OUT 1
5
+
HCPL-4504/0454/J454
HCNW4504
8
7
6
2
3
LED 2
BASE/GATE
DRIVE CIRCUIT
Q2
OUT 2
5
–HV
Figure 16. Typical power inverter.
17
Figure 17. LED delay and dead time diagram.
Power Inverter Dead Time and Propagation Delay Specifica-
tions
The HCPL-4504/0454/J454 and HCNW4504 include a
specification intended to help designers minimize “dead
time” in their power inverter designs. The new “propaga-
tion delay difference”specification (tPLH-tPHL) is useful for
determining not only how much optocoupler switch-
ing delay is needed to prevent “shoot-through” current,
but also for determining the best achievable worst-case
dead time for a given design.
The amount of turn-on delay needed depends on the
propagation delay characteristics of the optocoupler, as
well as the characteristics of the transistor base/gate drive
circuit. Considering only the delay characteristics of the
optocoupler (the characteristics of the base/gate drive
circuit can be analyzed in the same way), it is important
to know the minimum and maximum turn-on (tPHL) and
turnoff (tPLH) propagation delay specifications, prefer-
ably over the desired operating temperature range. The
importance of these specifications is illustrated in Figure
17. The waveforms labeled “LED1”, “LED2”, “OUT1”, and
“OUT2” are the input and output voltages of the opto-
coupler circuits driving Q1 and Q2 respectively. Most in-
verters are designed such that the power transistor turns
on when the optocoupler LED turns on; this ensures that
both power transistors will be off in the event of a power
loss in the control circuit. Inverters can also be designed
such that the power transistor turns off when the opto-
coupler LED turns on; this type of design, however, re-
quires additional fail-safe circuitry to turn off the power
transistor if an over-current condition is detected. The
timing illustrated in Figure 17 assumes that the power
transistor turns on when the optocoupler LED turns on.
When inverter power transistors switch (Q1 and Q2 in
Figure 17), it is essential that they never conduct at the
same time. Extremely large currents will flow if there is
any overlap in their conduction during switching tran-
sitions, potentially damaging the transistors and even
the surrounding circuitry. This “shoot-through” current is
eliminated by delaying the turn-on of one transistor (Q2)
long enough to ensure that the opposing transistor (Q1)
has completely turned off. This delay introduces a small
amount of “dead time” at the output of the inverter dur-
ing which both transistors are off during switching tran-
sitions. Minimizing this dead time is an important design
goal for an inverter designer.
18
This expression can be rearranged to obtain
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],
The LED signal to turn on Q2 should be delayed enough
so that an optocoupler with the very fastest turn-on
propagation delay (tPHLmin) will never turn on before an
optocoupler with the very slowest turn-off propagation
delay (tPLHmax) turns off. To ensure this, the turn-on of the
optocoupler should be delayed by an amount no less
than (tPLHmax-tPHLmin), which also happens to be the max-
imum data sheet value for the propagation delay differ-
ence specification, (tPLH-tPHL). The HCPL-4504/0454/J454
and HCNW4504 specify a maximum (tPLH-tPHL) of 1.3 μs
over an operating temperature range of0-70°C.
and further rearranged to obtain
[(tPLH-tPHL max-(tPLH-tPHL)min],
)
which is the maximum minus the minimum data sheet
values of (tPLH-tPHL). The difference between the maxi-
mum and minimum values depends directly on the total
spread in propagation delays and sets the limit on how
good the worst-case dead time can be for a given design.
Therefore, optocouplers with tight propagation delay
specifications (and not just shorter delays or lower pulse-
width distortion) can achieve short dead times in power
inverters. The HCPL-4504/0454/J454 and HCNW4504
specify a minimum (tPLH-tPHL) of -0.7 μs over an operat-
ing temperature range of 0-70°C, resulting in a maximum
dead time of 2.0 μs when the LED turn-on delay is equal
Although (tPLH-tPHL max tells the designer how much delay
)
is needed to prevent shoot-through current, it is insuffi-
cient to tell the designer how much dead time a design
will have. Assuming that the optocoupler turn-on delay
is exactly equal to (tPLH - tPHL max, the minimum dead time
)
is zero (i.e., there is zero time between the turnoff of the
very slowest optocoupler and the turn-on of the very
fastest optocoupler).
to (tPLH-tPHL max
It is important to maintain accurate LED turn-on delays
because delays shorter than (tPLH -tPHL max may allow
)
, or 1.3μs.
Calculating the maximum dead time is slightly more
complicated. Assuming that the LED turn-on delay is still
)
shoot-through currents, while longer delays will increase
the worst-case dead time.
exactly equal to (tPLH-tPHL max, it can be seen in Figure 17
)
that the maximum dead time is the sum of the maximum
difference in turn-on delay plus the maximum difference
in turnoff delay,
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0552EN
AV02-0867EN - January 4, 2010
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