HCPL-5630OPTION#200 [AVAGO]
2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, HERMETIC SEALED, DIP-8;
| 型号： | HCPL-5630OPTION#200 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 2 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 10Mbps, HERMETIC SEALED, DIP-8 输出元件 光电 |
| 文件： | 总12页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6N134,* 81028, HCPL-563X, HCPL-663X,
HCPL-565X, 5962-98001, HCPL-268K,
HCPL-665X, 5962-90855, HCPL-560X
Hermetically Sealed, High Speed, High CMR, Logic Gate Optocouplers
Data Sheet
*Seeꢀmatrixꢀforꢀavailableꢀextensions.
Description
Features
Theseꢀunitsꢀareꢀsingle,ꢀdualꢀandꢀquadꢀchannel,ꢀhermeti-
callyꢀsealedꢀoptocouplers.ꢀTheꢀproductsꢀareꢀcapableꢀofꢀ
operationꢀandꢀstorageꢀoverꢀtheꢀfullꢀmilitaryꢀtemperatureꢀ
rangeꢀ andꢀ canꢀ beꢀ purchasedꢀ asꢀ eitherꢀ standardꢀ prod-
uctꢀorꢀwithꢀfullꢀMIL-PRF-38534ꢀClassꢀLevelꢀHꢀorꢀKꢀtestingꢀ
orꢀfromꢀtheꢀappropriateꢀDSCCꢀDrawing.ꢀAllꢀdevicesꢀareꢀ
manufacturedꢀandꢀtestedꢀonꢀaꢀMIL-PRF-38534ꢀcertifiedꢀ
lineꢀandꢀareꢀincludedꢀinꢀtheꢀDSCCꢀQualifiedꢀManufactur-
ersꢀListꢀQML-38534ꢀforꢀHybridꢀMicrocircuits.ꢀQuadꢀchan-
nelꢀdevicesꢀareꢀavailableꢀbyꢀspecialꢀorderꢀinꢀtheꢀ16ꢀpinꢀ
DIPꢀthroughꢀholeꢀpackages.
•ꢀ DualꢀmarkedꢀwithꢀdeviceꢀpartꢀnumberꢀandꢀDSCCꢀ
drawingꢀnumber
•ꢀ ManufacturedꢀandꢀtestedꢀonꢀaꢀMIL-PRF-38534ꢀ
CertifiedꢀLine
•ꢀ QML-38534,ꢀClassꢀHꢀandꢀK
•ꢀ Fiveꢀhermeticallyꢀsealedꢀpackageꢀconfigurations
•ꢀ Performanceꢀguaranteedꢀoverꢀfullꢀmilitaryꢀ
temperatureꢀrange:ꢀ-55°Cꢀtoꢀ+125°Cꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
•ꢀ Highꢀspeed:ꢀ10ꢀMbdꢀtypical
Truth Table (PositiveꢀLogic)
•ꢀ CMR:ꢀ>ꢀ10,000ꢀV/µsꢀtypical
Multichannel Devices
•ꢀ 1500ꢀVdcꢀwithstandꢀtestꢀvoltage
•ꢀ 2500ꢀVdcꢀwithstandꢀtestꢀvoltageꢀforꢀHCPL-565X
•ꢀ Highꢀradiationꢀimmunity
Input
Onꢀ(H)
Offꢀ(L)
Output
L
•ꢀ 6N137,ꢀHCPL-2601,ꢀHCPL-2630/31ꢀfunctionꢀ
H
compatibility
Single Channel DIP
•ꢀ Reliabilityꢀdata
•ꢀ TTLꢀcircuitꢀcompatibility
Applications
•ꢀ Militaryꢀandꢀaerospace
•ꢀ Highꢀreliabilityꢀsystems
•ꢀ Transportation,ꢀmedical,ꢀandꢀlifeꢀcriticalꢀsystems
•ꢀ Lineꢀreceiver
Input
Onꢀ(H)
Offꢀ(L)
Onꢀ(H)
Offꢀ(L)
Enable
Output
H
H
L
L
H
H
H
L
•ꢀ Voltageꢀlevelꢀshifting
Functional Diagram
Multipleꢀchannelꢀdevicesꢀavailable
•ꢀ Isolatedꢀinputꢀlineꢀreceiver
•ꢀ Isolatedꢀoutputꢀlineꢀdriver
•ꢀ Logicꢀgroundꢀisolation
•ꢀ Harshꢀindustrialꢀenvironments
V
CC
V
E
•ꢀ Isolationꢀforꢀcomputer,ꢀcommunication,ꢀandꢀtestꢀ
V
OUT
equipmentꢀsystems
GND
The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Eachꢀ channelꢀ containsꢀ aꢀ GaAsPꢀ lightꢀ emittingꢀ diodeꢀ Becauseꢀtheꢀsameꢀelectricalꢀdieꢀ(emittersꢀandꢀdetectors)ꢀ
whichꢀisꢀopticallyꢀcoupledꢀtoꢀanꢀintegratedꢀhighꢀspeedꢀ areꢀusedꢀforꢀeachꢀchannelꢀofꢀeachꢀdeviceꢀlistedꢀinꢀthisꢀ
photonꢀdetector.ꢀTheꢀoutputꢀofꢀtheꢀdetectorꢀisꢀanꢀopenꢀ dataꢀ sheet,ꢀ absoluteꢀ maximumꢀ ratings,ꢀ recommendedꢀ
collectorꢀ Schottkyꢀ clampedꢀ transistor.ꢀ Internalꢀ shieldsꢀ operatingꢀconditions,ꢀelectricalꢀspecifications,ꢀandꢀper-
provideꢀaꢀguaranteedꢀcommonꢀmodeꢀtransientꢀimmuni- formanceꢀcharacteristicsꢀshownꢀinꢀtheꢀfiguresꢀareꢀiden-
tyꢀspecificationꢀofꢀ1000ꢀV/µs.ꢀForꢀIsolationꢀVoltageꢀappli- ticalꢀ forꢀ allꢀ parts.ꢀ Occasionalꢀ exceptionsꢀ existꢀ dueꢀ toꢀ
cationsꢀrequiringꢀupꢀtoꢀ2500ꢀVdc,ꢀtheꢀHCPL-5650ꢀfamilyꢀisꢀ packageꢀ variationsꢀ andꢀ limitations,ꢀ andꢀ areꢀ asꢀ noted.ꢀ
alsoꢀavailable.ꢀPackageꢀstylesꢀforꢀtheseꢀpartsꢀareꢀ8ꢀandꢀ16ꢀ Additionally,ꢀtheꢀsameꢀpackageꢀassemblyꢀprocessesꢀandꢀ
pinꢀDIPꢀthroughꢀholeꢀ(caseꢀoutlinesꢀPꢀandꢀEꢀrespectively),ꢀ materialsꢀareꢀusedꢀinꢀallꢀdevices.ꢀTheseꢀsimilaritiesꢀgiveꢀ
andꢀ16ꢀpinꢀsurfaceꢀmountꢀDIPꢀflatꢀpackꢀ(caseꢀoutlineꢀF),ꢀ justificationꢀforꢀtheꢀuseꢀofꢀdataꢀobtainedꢀfromꢀoneꢀpartꢀ
leadlessꢀ ceramicꢀ chipꢀ carrierꢀ (caseꢀ outlineꢀ 2).ꢀ Devicesꢀ toꢀrepresentꢀotherꢀparts’ꢀperformanceꢀforꢀreliabilityꢀandꢀ
mayꢀbeꢀpurchasedꢀwithꢀaꢀvarietyꢀofꢀleadꢀbendꢀandꢀplat- certainꢀlimitedꢀradiationꢀtestꢀresults.
ingꢀoptions.ꢀSeeꢀSelectionꢀGuideꢀTableꢀforꢀdetails.ꢀStan-
dardꢀMicrocircuitꢀDrawingꢀ(SMD)ꢀpartsꢀareꢀavailableꢀforꢀ
eachꢀpackageꢀandꢀleadꢀstyle.
Selection Guide–Package Styles and Lead Configuration Options
Package
16 Pin DIP
8 Pin DIP
8 Pin DIP
8 Pin DIP
16 Pin Flat Pack
20 Pad LCCC
LeadꢀStyle
Channels
ThroughꢀHole ThroughꢀHole ThroughꢀHole ThroughꢀHole UnformedꢀLeads SurfaceꢀMount
2
1
2
2
4
2
CommonꢀChannelꢀWiring V ,ꢀGND
None
1500ꢀVdc
VCC,ꢀGND
1500ꢀVdc
VCC,ꢀGND
2500ꢀVdc
VCC,ꢀGND
1500ꢀVdc
None
1500ꢀVdc
CC
WithstandꢀTestꢀVoltage
Avago Part # & Options
Commercial
1500ꢀVdc
6N134[1]
HCPL-5600
HCPL-5601
HCPL-560K
GoldꢀPlate
HCPL-5630
HCPL-5631
HCPL-563K
GoldꢀPlate
HCPL-5650
HCPL-5651
HCPL-6650
HCPL-6651
HCPL-665K
GoldꢀPlate
HCPL-6630
HCPL-6631
HCPL-663K
SolderꢀPads*
MIL-PRF-38534,ꢀClassꢀH
MIL-PRF-38534,ꢀClassꢀK
StandardꢀLeadꢀFinish
SolderꢀDipped*
6N134/883B
HCPL-268K
GoldꢀPlate
Optionꢀ#200
Optionꢀ#100
Optionꢀ#300
GoldꢀPlate
Optionꢀ#200
Optionꢀ#100
Optionꢀ#300
Optionꢀ#200 Optionꢀ#200
Optionꢀ#100
ButtꢀCut/GoldꢀPlate
GullꢀWing/Soldered*
Class H SMD Part #
Optionꢀ#300
Prescriptꢀforꢀallꢀbelow
EitherꢀGoldꢀorꢀSolder
GoldꢀPlate
None
5962-
None
None
None
None
8102801EX
8102801EC
8102801EA
8102801UC
8102801UA
8102801TA
9085501HPX 8102802PX
9085501HPC 8102802PC
9085501HPA 8102802PA
9085501HYC 8102802YC
9085501HYA 8102802YA
9085501HXA 8102802ZA
8102805PX
8102805PC
8102805PA
8102804FX
8102804FC
81028032X
SolderꢀDipped*
81028032A
ButtꢀCut/GoldꢀPlate
ButtꢀCut/Soldered*
GullꢀWing/Soldered*
Class K SMD Part #
Prescriptꢀforꢀallꢀbelow
EitherꢀGoldꢀorꢀSolder
GoldꢀPlate
5962-
5962-
5962-
5962-
5962-
9800101KEX
9800101KEC
9085501KPX 9800102KPX
9085501KPC 9800102KPC
9800104KFX
9800104KFC
9800103K2X
SolderꢀDipped*
9800101KEA 9085501KPA 9800102KPA
9800101KUC 9085501KYC 9800102KYC
9800101KUA 9085501KYA 9800102KYA
9800103K2A
ButtꢀCut/GoldꢀPlate
ButtꢀCut/Soldered*
GullꢀWing/Soldered*
9800101KTA
9085501KXA 9800102KZA
*Solderꢀcontainsꢀlead.
Note:
1.ꢀJEDECꢀregisteredꢀpart.
2
Functional Diagrams
16ꢀPinꢀDIP
8ꢀPinꢀDIP
8ꢀPinꢀDIP
16ꢀPinꢀFlatꢀPack
UnformedꢀLeads
4ꢀChannels
20ꢀPadꢀLCCC
SurfaceꢀMount
2ꢀChannels
ThroughꢀHole
2ꢀChannels
ThroughꢀHole
1ꢀChannel
ThroughꢀHole
2ꢀChannels
15
1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC2
V
1
2
8
7
6
5
1
V
8
CC
CC
V
V
2
3
4
5
6
7
8
CC
CC
19
20
13
12
V
O2
V
V
O1
O2
V
V
V
V
V
E
O1
O2
O3
O1
2
3
4
7
6
5
GND
2
V
OUT
V
CC1
2
3
10
V
3
4
O1
V
O2
V
O4
GND
GND
1
GND
GND
GND
7
8
Note:ꢀAllꢀDIPꢀandꢀflatꢀpackꢀdevicesꢀhaveꢀcommonꢀV ꢀandꢀground.ꢀSingleꢀchannelꢀDIPꢀhasꢀanꢀenableꢀpinꢀ7.ꢀLCCCꢀ(leadlessꢀceramicꢀchipꢀcarrier)ꢀ
CC
packageꢀhasꢀisolatedꢀchannelsꢀwithꢀseparateꢀV ꢀandꢀgroundꢀconnections.ꢀAllꢀdiagramsꢀareꢀ“topꢀview.”
CC
Outline Drawings
16 Pin DIP Through Hole, 2 Channels
20.06 (0.790)
20.83 (0.820)
8.13 (0.320)
MAX.
0.89 (0.035)
1.65 (0.065)
4.45 (0.175)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Leaded Device Marking
Avago LOGO
Avago P/N
A QYYWWZ
COMPLIANCE INDICATOR, [1]
DATE CODE, SUFFIX (IF NEEDED)
XXXXXX
XXXXXXX
XXX XXX
* 50434
DSCC SMD [1]
DSCC SMD [1]
PIN ONE/
COUNTRY OF MFR.
Avago CAGE CODE [1]
ESD IDENT
Leadless Device Marking
Avago LOGO
Avago P/N
PIN ONE/
ESD IDENT
A QYYWWZ
XXXXXX
* XXXX
XXXXXX
XXX 50434
COMPLIANCE INDICATOR, [1]
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD [1]
DSCC SMD [1]
COUNTRY OF MFR.
Avago CAGE CODE [1]
Notes
1.ꢀQualifiedꢀpartsꢀonly
3
Outline Drawings (continued)
8 Pin DIP Through Hole, 1 and 2 Channels
8 Pin DIP Through Hole, 2 Channels
2500 Vdc Withstand Test Voltage
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
5.08 (0.200)
MAX.
3.81 (0.150)
MIN.
0.51 (0.020)
MIN.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
7.36 (0.290)
7.87 (0.310)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
2.29 (0.090)
2.79 (0.110)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
16 Pin Flat Pack, 4 Channels
20 Terminal LCCC Surface Mount, 2 Channels
7.24 (0.285)
6.99 (0.275)
8.70 (0.342)
9.10 (0.358)
2.29 (0.090)
MAX.
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
2.03 (0.080)
1.02 (0.040) (3 PLCS)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
11.13 (0.438)
10.72 (0.422)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
1.27 (0.050)
REF.
METALLIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
0.46 (0.018)
0.36 (0.014)
1.52 (0.060)
2.03 (0.080)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.31 (0.012)
0.23 (0.009)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
5.23
(0.206)
MAX.
0.89 (0.035)
0.69 (0.027)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
4
Hermetic Optocoupler Options
Option
Description
100
Surfaceꢀmountableꢀhermeticꢀoptocouplerꢀwithꢀleadsꢀtrimmedꢀforꢀbuttꢀjointꢀassembly.ꢀThisꢀoptionꢀisꢀavailableꢀ
onꢀcommercialꢀandꢀhi-relꢀproductꢀinꢀ8ꢀandꢀ16ꢀpinꢀDIPꢀ(seeꢀdrawingsꢀbelowꢀforꢀdetails).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Leadꢀfinishꢀisꢀsolderꢀdippedꢀratherꢀthanꢀgoldꢀplated.ꢀThisꢀoptionꢀisꢀavailableꢀonꢀcommercialꢀandꢀhi-relꢀproductꢀ
inꢀ8ꢀandꢀ16ꢀpinꢀDIP.ꢀDSCCꢀDrawingꢀpartꢀnumbersꢀcontainꢀprovisionsꢀforꢀleadꢀfinish.ꢀAllꢀleadlessꢀchipꢀcarrierꢀ
devicesꢀareꢀdeliveredꢀwithꢀsolderꢀdippedꢀterminalsꢀasꢀaꢀstandardꢀfeature.
Surfaceꢀmountableꢀhermeticꢀoptocouplerꢀwithꢀleadsꢀcutꢀandꢀbentꢀforꢀgullꢀwingꢀassembly.ꢀThisꢀoptionꢀisꢀavail-
ableꢀonꢀcommercialꢀandꢀhi-relꢀproductꢀinꢀ8ꢀandꢀ16ꢀpinꢀDIPꢀ(seeꢀdrawingsꢀbelowꢀforꢀdetails).ꢀThisꢀoptionꢀhasꢀ
solderꢀdippedꢀleads.
4.57 (0.180)
MAX.
0.51 (0.020)
1.40 (0.055)
MIN.
1.65 (0.065)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Solderꢀcontainsꢀlead.
5
Absolute Maximum Ratings
Noꢀderatingꢀrequiredꢀupꢀtoꢀ+125°C.
Parameter
Symbol
Min.
-65
-55
Max.
Units
°C
StorageꢀTemperature
OperatingꢀTemperature
CaseꢀTemperature
TS
TA
TC
TJ
+150
+125
°C
+170
°C
JunctionꢀTemperature
LeadꢀSolderꢀTemperature
+175
°C
260ꢀforꢀ10ꢀsec
40
°C
PeakꢀForwardꢀInputꢀCurrent
(eachꢀchannel,ꢀ≤1ꢀmsꢀduration)
IF(PEAK)
IF(AVG)
mA
AverageꢀInputꢀForwardꢀCurrentꢀ(eachꢀchannel)
InputꢀPowerꢀDissipationꢀ(eachꢀchannel)
ReverseꢀInputꢀVoltageꢀ(eachꢀchannel
SupplyꢀVoltageꢀ(1ꢀminuteꢀmaximum)
OutputꢀCurrentꢀ(eachꢀchannel)
20
35
5
mA
mW
V
VR
VCC
IO
7.0
25
7*
V
mA
V
OutputꢀVoltageꢀ(eachꢀchannel)
VO
PO
PD
OutputꢀPowerꢀDissipationꢀ(eachꢀchannel)
PackageꢀPowerꢀDissipationꢀ(eachꢀchannel)
40
200
mW
mW
*Selectionꢀforꢀhigherꢀoutputꢀvoltagesꢀupꢀtoꢀ20ꢀVꢀisꢀavailableꢀ
Single Channel Product Only
EnableꢀInputꢀVoltage
VE
5.5
V
8 Pin Ceramic DIP Single Channel Schematic
Noteꢀenableꢀpinꢀ7.ꢀAnꢀexternalꢀ0.01ꢀµFꢀtoꢀ0.1ꢀµFꢀbypassꢀcapacitorꢀmustꢀ
beꢀconnectedꢀbetweenꢀV ꢀandꢀgroundꢀforꢀeachꢀpackageꢀtype.
CC
ESD Classification
(MIL-STD-883,ꢀMethodꢀ3015)
HCPL-5600/01/0K
(D),ꢀClassꢀ1
6N134,ꢀ6N134/883B,ꢀHCPL-5630/31/3K,ꢀHCPL-5650/51,ꢀHCPL-6630/31/3KꢀandꢀHCPL-6650/51/5K
(Dot),ꢀClassꢀ3
Recommended Operating Conditions
Parameter
Symbol
IFL
Min.
0
Max.
250
20
Units
InputꢀCurrent,ꢀLowꢀLevel,ꢀEachꢀChannel
InputꢀCurrent,ꢀHighꢀLevel,ꢀEachꢀChannel*
SupplyꢀVoltage,ꢀOutput
µA
mA
V
IFH
10
4.5
VCC
N
5.5
6
FanꢀOutꢀ(TTLꢀLoad)ꢀEachꢀChannel
*MeetsꢀorꢀexceedsꢀDSCCꢀSMDꢀandꢀJEDECꢀrequirements.
6
Recommended Operating Conditions (cont’d.)
SingleꢀChannelꢀProductꢀOnly[10]
Parameter
Symbol
VEH
Min.
2.0
0
Max.
VCC
Units
HighꢀLevelꢀEnableꢀVoltage
LowꢀLevelꢀEnableꢀVoltage
V
V
VEL
0.8
Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified)
Group
A[13]
Limits
Sub-
groups
Parameter
Symbol Test Conditions
Min. Typ.** Max.
Units
Fig.
Note
HighꢀLevel
OutputꢀCurrent
IOH*
VCCꢀ=ꢀ5.5ꢀV,ꢀVOꢀ=ꢀ5.5ꢀV,
IFꢀ=ꢀ250ꢀµA
1,ꢀ2,ꢀ3
20
250
µA
1
1
LowꢀLevel
OutputꢀVoltage
VOL*
VCCꢀ=ꢀ5.5ꢀV,ꢀIFꢀ=ꢀ10ꢀmA,
IOLꢀ(Sinking)ꢀ=ꢀ10ꢀmA
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
0.3
0.6
V
2
1,ꢀ9
1
CurrentꢀTransfer
Ratio
hFꢀCTR
VOꢀ=ꢀ0.6ꢀV,ꢀIFꢀ=ꢀ10ꢀmA,
VCCꢀ=ꢀ5.5ꢀV
100
%
Logicꢀ
Highꢀ
Supplyꢀ
Current
Single
Channel
ICCH*
VCCꢀ=ꢀ5.5ꢀV,ꢀIFꢀ=ꢀ0ꢀmA
9
14
28
42
18
36
50
mA
mA
mA
mA
mA
mA
1
Dual
Channel
VCCꢀ=ꢀ5.5ꢀV,
IF1ꢀ=ꢀIF2ꢀ=ꢀ0ꢀmA
18
25
13
26
33
6
Quad
ꢀChannel
VCCꢀ=ꢀ5.5ꢀV,ꢀIF1ꢀ=ꢀIF2ꢀ=
IF3ꢀ=ꢀIF4ꢀ=ꢀ0ꢀmA
Logicꢀ
low
Supplyꢀ
Current
Single
Channel
ICCL*
VCCꢀ=ꢀ5.5ꢀV,
IFꢀ=ꢀ20ꢀmA
1,ꢀ2,ꢀ3
1
6
Dual
Channel
VCCꢀ=ꢀ5.5ꢀV,
IF1ꢀ=ꢀIF2ꢀꢀ=ꢀ20ꢀmA
Quad
ꢀChannel
VCCꢀ=ꢀ5.5ꢀV,ꢀIF1ꢀ=ꢀIF2ꢀ=
IF3ꢀ=ꢀIF4ꢀꢀ=ꢀ20ꢀmA
InputꢀForward
Voltage
VF*
IFꢀ=ꢀ20ꢀmA
1,ꢀ2,ꢀ3
1,ꢀ2
1.5
1.9
V
V
3
3
1,ꢀ15
1,ꢀ16
1.55
1.75
1.85
3
InputꢀReverse
BreakdownꢀVoltage
BVR*
II-O*
IRꢀ=ꢀ10ꢀµA
1,ꢀ2,ꢀ3
5
V
1
Input-Output
LeakageꢀCurrent
RHꢀ≤ꢀ65% V ꢀ=ꢀ1500ꢀ
TAꢀ=ꢀ25°C
tꢀ=ꢀ5ꢀsꢀ
1
1
4
1.0
1.0
4.0
µA
µA
pF
2,ꢀ8,ꢀ17
18
I-O
Vdc
V ꢀ=ꢀ2500ꢀ
I-O
Vdc
CapacitanceꢀBetweenꢀ CI-O
Input/ꢀOutput
fꢀ=ꢀ1ꢀMHz,ꢀTCꢀ=ꢀ25°C
1.0
1,ꢀ3,
14
*IdentifiedꢀtestꢀparametersꢀforꢀJEDECꢀregisteredꢀparts.
**AllꢀtypicalꢀvaluesꢀareꢀatꢀVCCꢀ=ꢀ5ꢀV,ꢀTAꢀ=ꢀ25°C.
7
Electrical Characteristics, (cont’d) TA = -55°C to +125°C unless otherwise specified
Group A[13]
Limits
Typ.**
60
Parameter
Symbol Test Conditions
Subgroups
Min.
Max.
100
140
Units
Fig.
Note
PropagationꢀDelayꢀ
TimeꢀtoꢀHighꢀOutputꢀ
Level
tPLH*
V ꢀ=ꢀ5ꢀV,ꢀRLꢀ=ꢀ510ꢀΩ,ꢀ
CLꢀ=ꢀ50ꢀpF,
IFꢀ=ꢀ13ꢀmA
9
ns
4,ꢀ5,ꢀ6
1,ꢀ5
CC
10,ꢀ11
PropagationꢀDelayꢀ
TimeꢀtoꢀLowꢀOutputꢀ
Level
tPHL*
9
55
100
120
ns
10,ꢀ11
OutputꢀRiseꢀTime
OutputꢀFallꢀTime
tLH
tHL
RLꢀ=ꢀ510ꢀΩ,ꢀCLꢀ=ꢀ50ꢀ
pF,ꢀIFꢀ=ꢀ13ꢀmA
9,ꢀ10,ꢀ11
9,ꢀ10,ꢀ11
35
35
90
40
ns
1
CommonꢀModeꢀ
Transient
Immunityꢀatꢀ
HighꢀOutput
Level
|CMH|
VCMꢀ=ꢀ50ꢀVꢀ(PEAK),
VCCꢀ=ꢀ5ꢀV,ꢀ
VOꢀ(min.)ꢀ=ꢀ2ꢀV,
RLꢀ=ꢀ510ꢀΩ,
1000
1000
>10000
V/µs
7
7
1,ꢀ7,
14
IFꢀ=ꢀ0ꢀmA
CommonꢀMode
Transient
ImmunityꢀatꢀLowꢀ
OutputꢀLevel
|CML|
VCMꢀ=ꢀ50ꢀVꢀ(PEAK),
VCCꢀ=ꢀ5ꢀV,ꢀVOꢀ(max.)ꢀ=ꢀ
0.8ꢀV,ꢀRLꢀ=ꢀ510ꢀΩ,ꢀIFꢀ=ꢀ
10ꢀmA
9,ꢀ10,ꢀ11
>10000
-1.45
V/µs
1,ꢀ7,
14
Single Channel Product Only
LowꢀLevel
EnableꢀCurrent
IEL
VCCꢀ=ꢀ5.5ꢀV,
VEꢀ=ꢀ0.5ꢀV
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
1,ꢀ2,ꢀ3
-2.0
2.0
mA
V
HighꢀLevel
EnableꢀVoltage
VEH
VEL
10
LowꢀLevel
0.8
V
EnableꢀVoltage
*IdentifiedꢀtestꢀparametersꢀforꢀJEDECꢀregisteredꢀpart.
**AllꢀtypicalꢀvaluesꢀareꢀatꢀVCCꢀ=ꢀ5ꢀV,ꢀTAꢀ=ꢀ25°C.
Typical Characteristics, T = 25°C, V = 5 V
A
CC
Parameter
Sym.
CIN
Typ.
60
Units
Test Conditions
Fig.
Note
InputꢀCapacitance
pF
VFꢀ=ꢀ0ꢀV,ꢀfꢀ=ꢀ1ꢀMHz
IFꢀ=ꢀ20ꢀmA
1
1
InputꢀDiodeꢀTemperature
Coefficient
∆VF
-1.5
mV/°C
∆T
A
Resistanceꢀ(Input-Output)
RI-O
1012
Ω
V ꢀ=ꢀ500ꢀV
2
I-O
Single Channel Product Only
PropagationꢀDelayꢀTimeꢀof
EnableꢀfromꢀVEHꢀtoꢀVEL
tELH
tEHL
35
35
ns
ns
RLꢀ=ꢀ510ꢀΩ,ꢀCLꢀ=ꢀ50ꢀpF
IFꢀ=ꢀ13ꢀmA,ꢀVEHꢀ=ꢀ3ꢀV,
VELꢀ=ꢀ0V
8,ꢀ9
1,ꢀ11
1,ꢀ12
PropagationꢀDelayꢀTimeꢀof
EnableꢀfromꢀVELꢀtoꢀVEH
Dual and Quad Channel Product Only
Input-Input
LeakageꢀCurrent
II-I
0.5
nA
RelativeꢀHumidityꢀ≤ꢀ65%
4
V ꢀ=ꢀ500ꢀV,ꢀtꢀ=ꢀ5ꢀs
I-I
Resistanceꢀ(Input-Input)
Capacitanceꢀ(Input-Input)
RI-I
CI-I
1012
0.55
Ω
VI-Iꢀ=ꢀ500ꢀV
fꢀ=ꢀ1ꢀMHz
4
4
pF
8
Notes:
ꢀ 1.ꢀ Eachꢀchannel.
ꢀ 2.ꢀ Allꢀ devicesꢀ areꢀ consideredꢀ two-terminalꢀ devices;ꢀ II-Oꢀ isꢀ measuredꢀ betweenꢀ allꢀ inputꢀ leadsꢀ orꢀ terminalsꢀ shortedꢀ togetherꢀ andꢀ allꢀ outputꢀ
leadsꢀorꢀterminalsꢀshortedꢀtogether.
ꢀ 3.ꢀ Measuredꢀbetweenꢀeachꢀinputꢀpairꢀshortedꢀtogetherꢀandꢀallꢀoutputꢀconnectionsꢀforꢀthatꢀchannelꢀshortedꢀtogether.
ꢀ 4.ꢀ Measuredꢀbetweenꢀadjacentꢀinputꢀpairsꢀshortedꢀtogetherꢀforꢀeachꢀmultichannelꢀdevice.
ꢀ 5.ꢀ tPHLꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ50%ꢀpointꢀonꢀtheꢀleadingꢀedgeꢀofꢀtheꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀonꢀtheꢀleadingꢀedgeꢀofꢀ
theꢀoutputꢀpulse.ꢀTheꢀtPLHꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ50%ꢀpointꢀonꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀ
onꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀoutputꢀpulse.
ꢀ 6.ꢀ TheꢀHCPL-6630,ꢀHCPL-6631,ꢀandꢀHCPL-663Kꢀdualꢀchannelꢀpartsꢀfunctionꢀasꢀtwoꢀindependentꢀsingleꢀchannelꢀunits.ꢀUseꢀtheꢀsingleꢀchannelꢀ
parameterꢀlimitsꢀforꢀeachꢀchannel.
ꢀ 7.ꢀ CMLꢀ isꢀ theꢀ maximumꢀ rateꢀ ofꢀ riseꢀ ofꢀ theꢀ commonꢀ modeꢀ voltageꢀ thatꢀ canꢀ beꢀ sustainedꢀ withꢀ theꢀ outputꢀ voltageꢀ inꢀ theꢀ logicꢀ lowꢀ stateꢀ
(VOꢀ<ꢀ0.8ꢀV).ꢀ CMHꢀ isꢀ theꢀ maximumꢀ rateꢀ ofꢀ fallꢀ ofꢀ theꢀ commonꢀ modeꢀ voltageꢀ thatꢀ canꢀ beꢀ sustainedꢀ withꢀ theꢀ outputꢀ voltageꢀ inꢀ theꢀ logicꢀ
highꢀstateꢀ(VOꢀ>ꢀ2.0ꢀV).
ꢀ 8.ꢀ Thisꢀisꢀaꢀmomentaryꢀwithstandꢀtest,ꢀnotꢀanꢀoperatingꢀcondition.
ꢀ 9.ꢀ Itꢀisꢀessentialꢀthatꢀaꢀbypassꢀcapacitorꢀ(0.01ꢀtoꢀ0.1ꢀµF,ꢀceramic)ꢀbeꢀconnectedꢀfromꢀVCCꢀtoꢀground.ꢀTotalꢀleadꢀlengthꢀbetweenꢀbothꢀendsꢀofꢀ
thisꢀexternalꢀcapacitorꢀandꢀtheꢀisolatorꢀconnectionsꢀshouldꢀnotꢀexceedꢀ20ꢀmm.
10.ꢀ Noꢀexternalꢀpullꢀupꢀisꢀrequiredꢀforꢀaꢀhighꢀlogicꢀstateꢀonꢀtheꢀenableꢀinput.
11.ꢀ TheꢀtELHꢀenableꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ1.5ꢀVꢀpointꢀonꢀtheꢀtrailingꢀedgeꢀofꢀtheꢀenableꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀonꢀ
theꢀtrailingꢀedgeꢀofꢀtheꢀoutputꢀpulse.
12.ꢀ TheꢀtEHLꢀenableꢀpropagationꢀdelayꢀisꢀmeasuredꢀfromꢀtheꢀ1.5ꢀVꢀpointꢀonꢀtheꢀleadingꢀedgeꢀofꢀtheꢀenableꢀinputꢀpulseꢀtoꢀtheꢀ1.5ꢀVꢀpointꢀonꢀ
theꢀleadingꢀedgeꢀofꢀtheꢀoutputꢀpulse.
13.ꢀ Standardꢀpartsꢀreceiveꢀ100%ꢀtestingꢀatꢀ25°Cꢀ(Subgroupsꢀ1ꢀandꢀ9).ꢀSMDꢀandꢀ883Bꢀpartsꢀreceiveꢀ100%ꢀtestingꢀatꢀ25,ꢀ125,ꢀandꢀ-55°Cꢀ(Sub-
groupsꢀ1ꢀandꢀ9,ꢀ2ꢀandꢀ10,ꢀ3ꢀandꢀ11,ꢀrespectively).
14.ꢀ Parametersꢀareꢀtestedꢀasꢀpartꢀofꢀdeviceꢀinitialꢀcharacterizationꢀandꢀafterꢀdesignꢀandꢀprocessꢀchanges.ꢀParametersꢀareꢀguaranteedꢀtoꢀlimitsꢀ
specifiedꢀforꢀallꢀlotsꢀnotꢀspecificallyꢀtested.
15.ꢀ Notꢀrequiredꢀforꢀ6N134,ꢀ6N134/883B,ꢀ8102801,ꢀHCPL-268Kꢀandꢀ5962-9800101ꢀtypes.
16.ꢀ Requiredꢀforꢀ6N134,ꢀ6N134/883B,ꢀ8102801,ꢀHCPL-268Kꢀandꢀ5962-9800101ꢀtypes.
17.ꢀ NotꢀrequiredꢀforꢀHCPL-5650,ꢀHCPL-5651ꢀandꢀ8102805ꢀtypes.
18.ꢀ RequiredꢀforꢀHCPL-5650,ꢀHCPL-5651ꢀandꢀ8102805ꢀtypesꢀonly.
Figure 1. High Level Output Current vs. Tempera- Figure 2. Input-Output Characteristics.
ture.
Figure 3. Input Diode Forward Characteristics.
9
D.U.T.
5 V
V
CC
PULSE
GENERATOR
R
L
I
F
V
O
Z
t
= 50Ω
= 5 ns
O
H
0.01 µF
BYPASS
V
O
C *
L
INPUT
MONITORING
NODE
GND
Rm
* C INCLUDES PROBE AND STRAY WIRING CAPACITANCE.
L
Figure 5. Propagation Delay, tPHL and tPLH vs. Pulse Input
Current, IFH.
Figure 4. Test Circuit for tPHL and tPLH.*
D.U.T.
+5 V
B
V
CC
510
Ω
I
I
A
OUTPUT V
O
MONITORING
NODE
0.01 µF
BYPASS
GND
-
V
FF
V
CM
+
PULSE GEN.
Figure 6. Propagation Delay vs. Temperature.
Figure 7. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
10
PULSE
GENERATOR
OUTPUT V
MONITORING
NODE
E
Z
= 50 Ω
= 5 ns
O
r
t
+5 V
D.U.T.
V
CC
R
L
V
E
I
= 13 mA
F
V
OUT
OUTPUT V
MONITORING
NODE
O
0.01 µF
BYPASS
C *
L
GND
* C INCLUDES PROBE AND
L
STRAY WIRING CAPACITANCE.
Figure 9. Enable Propagation Delay vs. Temperature.
Figure 8. Test Circuit for tEHL and tELH.
V
CC
+5.5 V
V
D.U.T.*
OC
+5.5 V
V
CC
(EACH INPUT)
0.01 µF
+
-
V
200
Ω
200
Ω
IN
5.3 V
(EACH OUTPUT)
(EACH OUTPUT)
GND
CONDITIONS: I = 20 mA
F
I
= 25 mA
O
T
= +125 o
C
A
* ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 10. Operating Circuit for Burn-In and Steady State Life Tests.
11
MIL-PRF-38534 Class H, Class K, and
DSCC SMD Test Program
Avago’sꢀ Hi-Relꢀ Optocouplersꢀ areꢀ inꢀ complianceꢀ withꢀ
MIL-PRF-38534ꢀ Classesꢀ Hꢀ andꢀ K.ꢀ Classꢀ Hꢀ andꢀ Classꢀ Kꢀ
devicesꢀ areꢀ alsoꢀ inꢀ complianceꢀ withꢀ DSCCꢀ drawingsꢀ
81028,ꢀ5962-90855ꢀandꢀ5962-98001.
Testingꢀconsistsꢀofꢀ100%ꢀscreeningꢀandꢀqualityꢀconfor-
manceꢀinspectionꢀtoꢀMIL-PRF-38534.
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes 5968-9407E
AV02-1336EN - June 10, 2008
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