HFBR-5208XXXZ [AVAGO]
1 x 9 Fiber Optic Transceivers for 622 Mb/s ATM/SONET/SDH Applications;
| 型号： | HFBR-5208XXXZ |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 1 x 9 Fiber Optic Transceivers for 622 Mb/s ATM/SONET/SDH Applications ATM 异步传输模式 |
| 文件： | 总17页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFBR-5208xxxZ
1 x 9 Fiber Optic Transceivers for 622 Mb/s
ATM/SONET/SDH Applications
Data Sheet
Description
General
Features
Links of 500 m with 62.5/125 μm multimode fiber
(MMF) from 155-622 Mb/s
The HFBR-5208xxxZ (multimode transceiver) from Avago
allow the system designer to implement a range of solu-
tions for ATM/SONET STS-12/SDH STM-4 applications.
RoHS compliant
Compliant with ATM forum 622.08 Mb/s physical layer
specification (AF-PHY-0046.000)
The overall Avago transceiver consists of three sections:
the transmitter and receiver optical subassemblies, an
electrical subassembly and the mezzanine package
housing which incorporates a duplex SC connector
receptacle.
Compliant with ANSI broadband ISDN - physical layer
specification T1.646-1995 and T1.646a-1997
HFBR-5208xxxZ is compliant with ANSI network to
customer installation interfaces - synchronous optical
NETwork (SONET) physical media dependent specifi-
cation: multimode fiber T1.416.01-1998
Transmitter Section
Industry-standard multi-sourced 1 x 9 mezzanine
The transmitter section of the HFBR-5208xxxZ consists
of a 1300 nm LED in an optical subassembly (OSA) which
mates to the multimode fiber cable. The OSA’s are driven
by a custom, silicon bipolar IC which converts differential
PECL logic signals (ECL referenced to a +5 V supply) into
an analog LED drive current.
package style
Single +5 V power supply operation and PECL logic
interfaces
Wave solder and aqueous wash process compatible
Applications
Receiver Section
General purpose low-cost MMF links at 155 to 650
Mb/s
The receiver contains an InGaAs PIN photodiode mounted
together with a custom, silicon bipolar transimpedance
preamplifier IC in an OSA. This OSA is mated to a custom,
silicon bipolar circuit providing post amplification and
quantization and optical signal detection.
ATM 622 Mb/s MMF links from switch-to-switch or
switch-to-server in the end-user premise
Private MMF interconnections at 622 Mb/s SONET
STS-12/SDH STM-4 rate
The custom, silicon bipolar circuit includes a Signal Detect
circuit which provides a PECL logic high state output
upon detection of a usable input optical signal level. This
single-ended PECL output is designed to drive a standard
PECL input through normal 50 W PECL load.
Applications Information
Typical BER Performance of HFBR-5208xxxZ Receiver versus Input Optical Power Level
The HFBR-5208xxxZ transceiver can be operated at Bit- Relative Input Optical Power amount (dB) is referenced to
Error-Ratio conditions other than the required BER = 1
x 10 of the 622 MBd ATM Forum 622.08 Mb/s Physical
Layer Standard and the ANSI T1.646a. The typical trade-
off of BER versus Relative Input Optical Power is shown
in Figure 1. The Relative Input Optical Power in dB is
the absolute level (dBm avg.) given in the Receiver Optical
Characteristics table. The 0 ns sampling time position
for this Figure 2 refers to the center of the Baud interval
for the particular signaling rate. The Baud interval is the
reciprocal of the signaling rate in MBd. For example, at
-10
referenced to the Input Optical Power parameter value 622 MBd the Baud interval is 1.61 ns, at 155 MBd the Baud
in the Receiver Optical Characteristics table. For better
BER condition than 1 x 10 , more input signal is needed
interval is 6.45 ns. Test conditions for this tub diagram are
listed in Figure 2.
-10
(+dB). For example, to operate the HFBR-5208xxxZ at a
BER of 1 x 10 , the receiver will require an input signal
The HFBR-5208xxxZ receiver input optical power require-
ments vary slightly over the signaling rate range of 20
MBd to 700 MBd for a constant bit-error-ratio (BER) of
-12
approximately 0.6 dB higher than the -26 dBm level re-
-10
quired for 1 x 10 operation, i.e. -25.4 dBm.
-10
10 condition. Figure 3 illustrates the typical receiver
relative input optical power varies by <0.7 dB over this
full range. This small sensitivity variation allows the
optical budget to remain nearly constant for designs that
make use of the broad signaling rate range of the HFBR-
5208xxxZ. The curve has been normalized to the input
optical power level (dBm avg.) of the receiver for 622 MBd
10 -2
LINEAR EXTRAPOLATION OF
-4
-7
10 THROUGH 10
DATA
10 -3
10 -4
ACTUAL DATA
10 -5
10 -6
10 -7
-10
at center of the Baud interval with a BER of 10 . The data
patterns that can be used at these signaling rates should
be, on average, balanced duty factor of 50%. Momentary
excursions of less or more data duty factor than 50% can
occur, but the overall data pattern must remain balanced.
Unbalanced data duty factor will cause excessive pulse-
width distortion, or worse, bit errors. The test conditions
are listed in Figure 3.
10 -8
10 -9
10 -10
10 -11
10 -12
10 -13
10 -14
10 -15
-5
-1
-4 -3 -2
0
1
3
2
Recommended Circuit Schematic
Figure 1. Relative Input Optical Power - dBm Average.
When designing the HFBR-5208xxxZ circuit interface, there
are a few fundamental guidelines to follow. For example, in
the Recommended Circuit Schematic, Figure 4, the differential
data lines should be treated as 50 ohm Microstrip or stripline
transmission lines. This will help to minimize the parasitic
inductance and capacitance effects. Proper termination of
the differential data signal will prevent reflections and ringing
which would compromise the signal fidelity and generate
unwanted electrical noise. Locate termination at the received
signal end of the transmission line. The length of these lines
should be kept short and of equal length to prevent pulse-
width distortion from occurring. For the high-speed signal
lines, differential signals should be used, not single-ended
signals. These differential signals need to be loaded symmetri-
cally to prevent unbalanced currents from flowing which will
cause distortion in the signal.
An informative graph of a typical, short fiber transceiver
link per-formance can be seen in Figure 2. This figure is
useful for designing short reach links with time-based
jitter requirements. This figure indicates Relative Input
Optical Power versus Sampling Time Position within the
receiver output data eye-opening. The given curves are
-10
at a constant bit-error-ratio (BER) of 10 for four differ-
ent signaling rates, 155 MBd, 311 MBd, 622 MBd and 650
MBd. These curves, called “tub” diagrams for their shape,
show the amount of data eye-opening time-width for
various receiver input optical power levels. A wider data
eye-opening provides more time for the clock recovery
circuit to operate within without creating errors. The
deeper the tub is indicates less input optical power is
needed to operate the receiver at the same BER condition.
Generally, the wider and deeper the tub is the better. The
2
3
2.5
2
155.52 M B d
311.04 M B d
622.08 M B d
650.00 M B d
1.5
1
0.5
0
-0 .5
-1
-3.5
-2 .5
-1 .5
-0 .5
0.5
1.5
2.5
3.5
Clock to Data Offset Delay in nsec (0 = Data Eye Center)
Figure 2. HFBR-5208xxMZ Relative Input Optical Power as a function of sampling time position. Normalized to center of Baud interval at 622 MBd. Test
Conditions +25°C, 5.25 V, PRBS 223-1, optical r/f = 0.9 ns with 3 m of 62.5 μm MMF.
2.5
HFBR-5208xxMZ
2
1.5
1
0.5
0
-0.5
-1
-1.5
20
105
190
275
360
445
530
615
700
Module Data StreamSerial Data Rate in MBd
Figure 3. Relative Input Optical Power as a function of data rate normalized to center of Baud interval at 622 MBd.
Test Conditions +25°C, 5.25 V, PRBS 223-1, optical r/f = 0.9 ns with 3 m of MMF or SMF.
3
Maintain a solid, low inductance ground plane for returning
signal currents to the power supply. Multilayer plane printed
and high, self-resonating frequency are recommended. All
power supply components need to be placed physically
circuit board is best for distribution of V , returning ground
next to the V pins of the receiver and transmitter. Use a
CC
CC
currents, forming transmission lines and shielding. Also, it
is important to suppress noise from influencing the fiber-
optic transceiver per-formance, especially the receiver
good, uniform ground plane with a minimum number of
holes to provide a low-inductance ground current return
path for the signal and power supply currents.
circuit. Proper power supply filtering of V for this trans-
ceiver is accomplished by using the recommended sepa-
rate filter circuits shown in Figure 4. These filter circuits
CC
Although the front mounting posts make contact with the
metallized housing, these posts should not be relied upon to
provide adequate electrical connection to the plated housing.
It is recommended to either connect these front posts to
chassis ground or allow them to remain unconnected. These
front posts should not be connected to signal ground.
suppress V noise of 100 mV peak-to-peak or less over
CC
a broad frequency range. This prevents receiver sensitiv-
ity degradation . It is recommended that surface-mount
components be used. Use tantalum capacitors for the 10
μF capacitors and monolithic, ceramic bypass capacitors
for the 0.1 μF capacitors. Also, it is recommended that a
surface-mount coil inductor of 1 μH be used. Ferrite beads
can be used to replace the coil inductors when using
Figure 5 shows the recommended board layout pattern.
In addition to these recommendations, AvagoTechnologies
Application Engineering staff is available for consulting
on best layout practices with various vendors’ serializer/
deserializer, clock recovery/generation integrated circuits.
quieter V supplies, but a coil inductor is recommended
CC
over a ferrite bead to provide low-frequency noise filtering
as well. Coils with a low, series dc resistance (<0.7 ohms)
NOTES:
MOUNTING POST
MOUNTING POST
NO INTERNAL CONNECTION
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS
NEED TO BE LOCATED AT THE INPUT OF DEVICES
RECEIVING THOSE PECL SIGNALS. RECOMMEND
MULTI-LAYER PRINTED CIRCUIT BOARD WITH 50 OHM
MICROSTRIP OR STRIPLINE SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = R10 = 130 OHMS.
R2 = R3 = R5 = R7 = R9 = 82 OHMS.
C1 = C2 = C3 = C5 = C6 = 0.1 F.
NO INTERNAL CONNECTION
HFBR-5208xxxZ
TOP VIEW
C4 = C7 = 10 F.
L1 = L2 = 1 H COIL OR FERRITE INDUCTOR
(see text comments).
Rx
V EER
1
Rx
V CCR
5
Tx
VCCT
6
Tx
V EET
9
RD
2
RD
3
SD
4
TD
7
TD
8
C1
C2
VCC
R2
R3
C5
L1
L2
C4
C7
TERMINATION
AT PHY
R1
R4
DEVICE
VCC
C3
INPUTS
V CC FILTER
R5
R7
AT V PINS
CC
TRANSCEIVER
R9
TERMINATION
AT TRANSCEIVER
INPUTS
C6
R6
R8
R10
RD
RD
SD
VCC
TD
TD
Figure 4. Recommended Circuit Schematic for dc Coupling (at +5 V) between Optical Transceiver and Physical Layer IC
4
Reference Design
Operation in -5.2 V Designs
Avago has developed a reference design for multimode
ATM-SONET/SDH applications shown in Figure 6. This ref-
erence design uses aVitesse Semiconductor Inc.’sVSC8117
clock recovery/clock generation/serializer/deserializer
integrated circuit and a PMC-Sierra Inc. PM5355 framer
IC. Application Note 1178 documents the design, layout,
testing and performance of this reference design. Gerber
files, schematic and application note are available from
the Avago Fiber-Optics Components’web site at the URL
of http://www.avagotech.com.
For applications that require -5.2 V dc power supply level
for true ECL logic circuits, the HFBR-5208xxxZ transceiver
can be operated with a V = 0 V dc and a V = -5.2 V dc.
CC
EE
This transceiver is not specified with an operating, nega-
tive power supply voltage. The potential compromises
that can occur with use of -5.2 V dc power are that the
absolute voltage states for V and V will be changed
OH
OL
slightly due to the 0.2 V difference in supply levels. Also,
noise immunity may be compromised for the HFBR-
5208xxxZ trans-ceiver because the ground plane is now
the V supply point. The suggested power supply filter
CC
circuit shown in the Recommended Circuit Schematic
figure should be located in theV paths at the transceiver
EE
supply pins. Direct coupling of the differential data signal
can be done between the HFBR-5208xxxZ transceiver
and the standard ECL circuits. For guaranteed -5.2 V dc
operation, contact your local Avago Component Field
Sales Engineer for assistance.
2 x Ø 1.9 0.1
(0.075 0.004)
20.32
(0.800)
9 x Ø 0.8 0.1
(0.032 0.004)
20.32
(0.800)
2.54
(0.100)
TOP VIEW
DIM EN S IO N S A RE IN M ILLIM ETERS (IN C HES )
Figure 5. Recommended Board Layout Pattern
Figure 6. 622.08 Mb/s OC-12 ATM-SONET/SDH Reference Design Board
5
Electromagnetic Interference (EMI)
providing the designer with a means to achieve good
EMI performance. The EMI performance of an enclosure
using these transceivers is dependent on the chassis
design. Avago encourages using standard RF suppression
practices and avoiding poorly EMI-sealed enclosures. In
addition, Avago advises that for the best EMI performance,
the metalized case must be connected to chassis ground
using one of the shield options.
One of a circuit board designer’s foremost concerns is
the control of electromagnetic emissions from electronic
equipment. Success in controlling generated Electromag-
netic Interference (EMI) enables the designer to pass a
governmental agency’s EMI regulatory standard; and more
importantly, it reduces the possibility of interference to
neighboring equipment. There are three options available
for the HFBR-5208xxxZ with regard to EMI shielding for
XXXX-XXXX
KEY:
YYWW = DATE CODE
N.B. For shielded
module the label
is mounted on
XXXX-XXXX = HFBR-5208MZ
COUNTRY OF ORIGIN YYWW
RX
ZZZZ = 1300 nm
TX
the end as
shown.
39.6
(1.56)
12.7
(0.50)
MAX.
4.7
(0.185)
AREA
RESERVED
FOR
PROCESS
PLUG
25.4
(1.00)
12.7
(0.50)
MAX.
2.0 0.1
(0.079 0.004)
SLOT WIDTH
2.5
(0.10)
SLOT DEPTH
+0.1
-0.05
0.25
+0.004
-0.002
(
0.010
)
9.8
(0.386)
MAX.
0.51
(0.020)
3.3 0.38
(0.130 0.015)
20.32
(0.800)
15.8 0.15
(0.622 0.006)
+0.25
-0.05
0.46
+0.25
-0.05
+0.010
-0.002
9X Ø
+0.010
-0.002
1.27
(
0.018
)
2X Ø
(
0.050
)
8X
20.32
(0.800)
23.8
(0.937)
2.54
(0.100)
20.32
(0.800)
14.5
(0.57)
1.3
(0.051)
2X Ø
Masked insulator material (no metalization)
Figure 7a. Package Outline Drawing for HFBR-5208xxxZ
6
39.12
(1.540)
12.70
(0.500)
6.35
(0.250)
MAX.
AREA
RESERVED
FOR
PROCESS
PLUG
25.40
(1.000)
12.70
(0.500)
MAX.
KEY:
YYW W = DA TE CODE
HFBR-5208MZ
COUNTRY OF ORIGIN
YYWW
5.93 0.1
(0.233 0.004)
TX
RX
+ 0.08
0.75
- 0.05
3.30 0.38
(0.130 0.015)
+ 0.003
10.35
(0.407)
)
(0.030
MAX.
- 0.002
2.92
(0.115)
18.52
(0.729)
+ 0.25
- 0.05
1.27
0.46
(0.018)
NOTE 1
+ 0.010
- 0.002
4.14
(0.163)
)
¿
(9x)
(0.050
NOTE 1
23.55
(0.927)
20.32
(0.800)
16.70
(0.657)
17.32
20.32
23.32
[8x(2.54/.100)]
(0.682) (0.800) (0.918)
0.87
(0.034)
23.24
(0.915)
15.88
(0.625)
NOTE 1: PHOSPHOR BRONZE IS THE BASE MATERIAL FOR THE POSTS & PINS.
FOR LEAD-FREE SOLDERING, THE SOLDER POSTS HAVE TIN COPPER OVER
NICKEL PLATING, AND THE ELECTRICAL PINS HAVE PURE TIN OVER NICKEL PLATING.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 7b. Package Outline Drawing for HFBR-5208MZ
7
An un-shielded option, shown in Figure 7a is available for
the HFBR-5208xxxZ fiber optic transceiver. This unit is
intended for applications where EMI is either not an issue
for the designer, or the unit resides in a highly-shielded
enclosure.
Recommended Solder and Wash Process
The HFBR-5208xxxZ is compatible with industry-standard
wave or hand solder processes.
HFBR-5000 Process Plug
The first shielded option, option EM, is for applications
where the position of the transceiver module will extend
outside the equipment enclosure. The metallized plastic
package and integral external metal shield of the trans-
ceiver helps locally to terminate EM fields to the chassis to
prevent their emissions outside the enclosure. This metal
shield contacts the panel or enclosure on the inside of
the aperture on all but the bottom side of the shield and
provides a good RF connection to the panel. This option
can accommodate various panel or enclosure thicknesses,
i.e. 1.02 mm (.04 in) min to 2.54 mm (0.1 in) max. The refer-
ence plane for this panel thickness variation is from the
front surface of the panel or enclosure. The recommended
length for protruding the HFBR-5208EMZ transceiver
beyond the front surface of the panel or enclosure is
6.35 mm (0.25 in) . With this option, there is flexibility of
positioning the module to fit the specific need of the en-
closure design. (See Figure 8 for the mechanical drawing
dimensions of this shield.)
The HFBR-5208xxxZ transceiver is supplied with a process
plug, the HFBR-5000, for protection of the optical ports
with the Duplex SC connector receptacle. This process
plug prevents contamination during wave solder and
aqueous rinse as well as during handling, shipping or
storage. It is made of high-temperature, molded, sealing
material that will withstand +85°C and a rinse pressure
2
of 110 lb/in .
Recommended Solder Fluxes and Cleaning/Degreasing
Chemicals
Solder fluxes used with the HFBR-5208xxxZ fiber-optic
transceiver should be water-soluble, organic solder fluxes.
Some recommended solder fluxes are Lonco 3355-11 from
London Chemical West, Inc. of Burbank, CA, and 100 Flux
from Alpha-metals of Jersey City, NJ or equivalent fluxes
from other companies.
Recommended cleaning and degreasing chemicals for
the HFBR-5208xxxZ are alcohols (methyl, isopropyl, iso-
butyl), aliphatics (hexane, heptane) and other chemicals,
such as soap solution or naphtha. Do not use partially
halogenated hydrocarbons for cleaning/degreasing.
Examples of chemicals to avoid are 1,1.1 trichloroethane,
ketones (such as MEK), acetone, chloroform, ethyl acetate,
methylene dichloride, phenol, methylene chloride or N
methylpyrolldone.
The second shielded option, option FM, is for applications
that are designed to have a flush mounting of the module
with respect to the front of the panel or enclosure. The
flush-mount design accommodates a large variety of
panel thickness, i.e. 1.02 mm (.04 in) min to 2.54 mm (0.1
in) max. Note the reference plane for the flush-mount
design is the interior side of the panel or enclosure. The
recommended distance from the centerline of the trans-
ceiver front solder posts to the inside wall of the panel is
13.82 mm (0.544 in) . This option contacts the inside panel
or enclosure wall on all four sides of this metal shield.
(See Figure 10 for the mechanical drawing dimensions
of this shield.)
Regulatory Compliance
These transceiver products are intended to enable com-
mercial system designers to develop equipment that com-
plies with the various regulations governing certification
of Information Technology Equipment. See the Regulatory
Compliance Table for details. Additional information is
available from your Avago sales representative.
Both shielded design options connect only to the equip-
ment chassis and not to the signal or logic ground of the
circuit board within the equipment closure. The front
panel aperture dimensions are recommended in Figures
9 and 11. When layout of the printed circuit board is done
to incorporate these metal-shielded transceivers, keep
the area on the printed circuit board directly under the
external metal shield free of any components and circuit
board traces. For additional EMI performance advantage,
use duplex SC fiber-optic connectors that have low metal
content inside the connector. This lowers the ability of the
metal fiber-optic connectors to couple EMI out through
the aperture of the panel or enclosure.
8
Electrostatic Discharge (ESD)
Immunity
There are two design cases in which immunity to ESD damage
is important.
Equipment utilizing these transceivers will be subject to
radio-frequency electromagnetic fields in some environ-
ments. These transceivers, with their integral shields,
have been characterized without the benefit of a normal
equipment chassis enclosure and the results are reported
below. Performance of a system containing these trans-
ceivers within a well- designed chassis is expected to be
better than the results of these tests without a chassis
enclosure.
The first case is during handling of the transceiver prior to
mounting it on the circuit board. It is important to use normal
ESD handling precautions for ESD sensitive devices. These pre-
cautions include using grounded wrist straps, work benches,
and floor mats in ESD controlled areas, etc.
The second case to consider is static discharges to the exterior
of the equipment chassis containing the transceiver parts. To
the extent that the duplex SC connector receptacle is exposed
to the outside of the equipment chassis, it may be subject to
whatever ESD system level test criteria that the equipment is
intended to meet.
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high-speed transceiv-
ers from Avago will be required to meet the requirements
of FCC in the United States, CENELEC EN55022 (CISPR 22)
in Europe and VCCI in Japan.
The HFBR-5208xxxZ EMI has been characterized with a
chassis enclosure to demonstrate the robustness of the
parts. Performance of a system containing these transceiv-
ers will vary depending on the individual chassis design.
Regulatory Compliance - Targeted Specifications
Feature
Test Method
Performance
Electrostatic Discharge (ESD) MIL-STD-883F
Method 3015.7
Class 1 (>1000 V) - Human Body Model
RADIEC-61000-4-2
Products of this design typically withstand 25 kV
without damage.
Electromagnetic Interference FCC Class B
Margins are dependant on customer board and
chassis design.
(EMI)
CENELEC EN55022
Class B (CISPR 22B) VCCI Class 2
Immunity
Variation of IEC 61000-4-3
Typically show no measurable effect from a 10
V/m field swept from 26 to 1000 MHz applied to
the transceiver when mounted to a circuit card
without a chassis enclosure.
Eye Safety
IEC 825-1 Class 1
LED Class 1
Component Recognition
Underwriters Laboratories and Canadian
Standards Association Joint Component
Recognition for Information Technology Equip-
ment including Electrical Business Equipment
UL File#: E173874
The HFBR-5208xxxZ LED are classified as IEC 825-1 Accessible Emission Limit (AEL) Class 1. AEL Class 1 are considered eye safe.
9
1 = V EER
2 = RD
3 = RD
4 = SD
N/C
TOP VIEW
N/C
N/C = NO INTERNAL CONNECTION
(MOUNTING POSTS) - CONNECT
TO CHASSIS GROUND OR LEAVE
FLOATING, DO NOT CONNECT TO
SIGNAL GROUND.
5 = V CCR
6 = V CCT
7 = TD
8 = TD
9 = V EET
Table 1. Pinout Table
Pin
Symbol
Functional Description
Mounting Studs
The mounting studs are provided for transceiver mechanical attachment to the circuit boards, they are
embedded in the metalized plastic housing and are not connected to the transceiver internal circuit. They
should be soldered into plated-through holes on the printed circuit board and not connected to signal
ground.
1
2
VEER
RD+
Receiver Signal GroundDirectly connect this pin to receiver signal ground plane. Receiver VEER and trans-
mitter VEET can connect to a common circuit board ground plane.
Receiver Data Out
Terminate this high-speed, differential, PECL output with standard PECL techniques at the follow-on
device input pin.
3
4
RD-
SD
Receiver Data Out Bar
Terminate this high-speed, differential, PECL output with standard PECL techniques at the follow-on
device input pin.
Signal Detect
Normal input optical signal levels to the receiver result in a logic “1”output (VOH).Low input optical signal
levels to the receiver result in a fault condition indication shown by a logic “0”output (VOL).If Signal Detect
output is not used, leave it open-circuited.This Signal Detect output can be used to drive a PECL input on
an upstream circuit, such as, Signal Detect input or Loss of Signal-bar.
5
6
7
VCCR
VCCT
TD-
Receiver Power Supply
Provide +5 V dc via the recommended receiver VCCR power supply filter circuit.Locate the power supply
filter circuit as close as possible to the VCCR pin.
Transmitter Power Supply
Provide +5 V dc via the recommended transmitter VCCT power supply filter circuit.Locate the power supply
filter circuit as close as possible to the VCCT pin.
Transmitter Data In Bar
Terminate this high-speed, differential, Transmitter Data input with standard PECL techniques at the
transmitter input pin.
8
9
TD+
VEET
Transmitter Data InTerminate this high-speed, differential, Transmitter Data input with standard PECL
techniques at the transmitter input pin.
Transmitter Signal GroundDirectly connect this pin to the transmitter signal ground plane. Transmitter
V
EET and receiver VEER can connect to a common circuit board ground plane.
10
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each
parameter in isolation, all other parameters having values within the recommended operating conditions. It should
not be assumed that limiting values of more than one parameter can be applied to the product at the same time.
Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter
Symbol
TS
Minimum
Typical
Maximum
+85
+260
10
Unit
°C
Notes
Storage Temperature
Lead Soldering Temperature
Lead Soldering Time
Supply Voltage
-40
TSOLD
tSOLD
VCC
VI
°C
sec.
V
-0.5
-0.5
6.0
Data Input Voltage
Transmitter Differential Input Voltage
Output Current
VCC
V
VD
1.6
V
1
ID
50
mA
%
Relative Humidity
RH
0
95
Recommended Operating Conditions
Parameter
Symbol
TA
Minimum
0
Typical
Maximum
+70
Unit
Notes
Ambient Operating Temperature
Ambient Operating Temperature
Supply Voltage
°C
TA
-40
+85
°C
VCC
4.75
5.25
V
Power Supply Rejection
PSR
100
mV p-p
2
3
3
Transmitter Data Input Voltage - Low
Transmitter Data Input Voltage - High
Transmitter Differential Input Voltage
Data Output Load
VIL-VCC
VIH-VCC
VD
-1.810
-1.165
0.3
-1.475
-0.880
1.6
V
V
V
RDL
50
50
W
W
4
4
Signal Detect Output Load
RSDL
Notes:
1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs without damaging the ESD protection circuit.
2. Tested with a 100 mV p-p sinusoidal signal in the frequency range from 500 Hz to 1 MHz imposed on the V supply with the recommended
CC
power supply filter in place, see Figure 4. Typically less than a 0.5 dB change in sensitivity is experienced.
3. Compatible with 10K, 10KH and 100K ECL and PECL output signals.
4. The outputs are terminated to V - 2 V.
CC
11
HFBR-5208xxxZ Family, 1300 nm LED
Transmitter Electrical Characteristics
(T = 0°C to +70°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V)
A
CC
(T = -40°C to +85°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V for A specification part)
A
CC
Parameter
Symbol
ICCT
PDIST
IIL
Minimum
Typical
155
Maximum
200
Unit
mA
W
Notes
Supply Current
Power Dissipation
1
0.75
1.05
Data Input Current - Low
Data Input Current -High
-350
μA
μA
IIH
350
Receiver Electrical Characteristics
(T = 0°C to +70°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V)
A
CC
(T = -40°C to +85°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V for A specification part)
A
CC
Parameter
Symbol
ICCR
Minimum
Typical
112
Maximum
177
Unit
mA
W
V
Notes
Supply Current
Power Dissipation
PDISR
0.37
-1.82
-0.94
0.3
0.77
2
3
3
4
4
3
3
5
6
Data Output Voltage - Low
VOL - VCC -1.950
VOH - VCC -1.045
-1.620
-0.740
0.51
Data Output Voltage - High
V
Data Output Rise Time
tR
tF
0.2
0.2
ns
ns
V
Data Output Fall Time
0.3
0.51
Signal Detect Output Voltage - Low
Signal Detect Output Voltage - High
Signal Detect Assert Reaction Time(Off to On)
Signal Detect Deassert Reaction Time (On to Off)
VOL - VCC -1.950
VOH - VCC -1.045
tSDA
-1.82
-0.94
35
-1.620
-0.740
100
V
μs
μs
tSDD
60
350
Notes:
1. The I value is held nearly constant to minimize unwanted electrical noise from being generated and conducted or emitted to
CC
neighboring circuitry.
2. Power dissipation value is the power dissipated in the receiver itself. It is calculated as the sum of the products of V and I minus the sum
CC
CC
of the products of the output voltages and load currents.
3. These outputs are compatible with 10K, 10KH and 100K ECL and PECL inputs.
4. These are 20% - 80% values.
5. The Signal Detect output will change from logic “V ” to “V ”within 100 μs of a step transition in input optical power from no light to -26 dBm.
OL
OH
6. The Signal Detect output will change from logic“V ” to “V ”within 350 μs of a step transition in input optical power from -26 dBm to no light.
OH
OL
12
HFBR-5208xxxZ Family, 1300 nm LED
Transmitter Optical Characteristics
(T = 0°C to +70°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V)
A
CC
(T = -40°C to +85°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V for A specification part)
A
CC
Parameter
Symbol
Minimum
Typical Maximum
Unit
Notes
Output Optical Power
62.5/125 μm. NA = 0.275 fiber
PO (BOL)
-19.5
-20
-17
-14
-14
dBm avg.
P
O (EOL)
PO (BOL)
O (EOL)
Output Optical Power
50/125 μm. NA = 0.20 fiber
-21.5
-22
-14
-14
dBm avg.
7
P
Output Optical Power at Logic “0”State
Optical Extinction Ratio
PO (“0”)
-60
46
dBm avg.
dB
ER
lc
s
10
Center Wavelength
1270
1330
136
0.7
0.9
0
1380
200
1.25
1.25
25
nm
Spectral Width - FWHM
nm
8
9
9
Optical Rise Time
tR
tF
ns
Optical Fall Time
ns
Overshoot
%
Systematic Jitter Contributed by the Transmitter
Random Jitter Contributed by the Transmitter
SJ
RJ
0.04
0.0
0.23
0.10
ns p-p
ns p-p
Notes:
7. The Output Optical Power is measured with the following conditions:
•
•
•
1 meter of fiber with cladding modes removed.
The input electrical signal is a 12.5 MHz square wave.
The Beginning of Life (BOL) to End of Life (EOL) degradation is less than 0.5 dB.
8. The relationship between FWHM and RMS values for spectral width can be derived from the assumption of a Gaussian-shaped spectrum which
results in RMS = FWHM/2.35.
9. These are 10-90% values.
13
HFBR-5208xxxZ Family, 1300 nm LED
Receiver Optical Characteristics
(T = 0°C to +70°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V)
A
CC
(T = -40°C to +85°C, V = 4.75 to 5.25 V. Typical @+25°C, 5 V for A specification part)
A
CC
Parameter
Symbol
Minimum
Typical Maximum
Unit
Notes
Minimum Input Optical Power at window edge
PIN MIN
(W)
-29.0
-30.5
-11
-26
dBm avg. 10
Fig 2
dBm avg. 10
Fig 2,3
Minimum Input Optical Power at eye center
PIN MIN (C)
Input Optical Power Maximum
Input Operating Wavelength
P
l
IN MAX
-14
dBm avg. 10
nm
1270
1380
0.30
0.48
-28
Systematic Jitter Contributed by the Receiver
Random Jitter Contributed by the Receiver
Signal Detect - Asserted
SJ
0.1
ns p-p
RJ
0.25
ns p-p
PA
PD +1.0 dB -30.5
dBm avg.
dBm avg.
dB
Signal Detect - Deasserted
PD
-45
1.0
-33.7
3.2
Signal Detect - Hysteresis
PA - PD
5
Notes:
10. This specification is intended to indicate the performance of the receiver section of the transceiver when the input power ranges from the
minimum level (with a window time-width) to the maximum level. Over this range the receiver is guaranteed to provide output data with a
-10
Bit Error Ratio (BER) better than or equal to 1 x 10
•
•
•
At the Beginning of Life (BOL)
Over the specified operating temperature and voltage ranges
23
Input is at 622.08 Mbd, 2 -1 PRBS data pattern with 72 “1”s and 72 “0”s inserted per the CCITT (now ITU-T) recommendation G.958 Appendix
1.
•
Receiver worst-case output data eye-opening (window time-width) is measured by applying worst-case input system-
atic (SJ) and randomjitter (RJ). The worst-case maximum input SJ = 0.5 ns peak-to-peak and the RJ = 0.15 ns peak-to-
peak per ANSI T1.646a standard. Since the input (transmitter) random jitter contribution is very small and difficult to
produce exactly, only the maximum systematic jitter is produced and used for testing the receiver. The corresponding re-
ceiver test window time-width must meet the requirement of 0.31 ns or larger. This worst-case test window time-width
results from the following jitter equation: Minimum Test Window Time-Width = Baud Interval - Tx SJ max. - Rx SJ max. - Rx RJ max.
espectively, Minimum Test Window Time-Width = 1.608 ns - 0.50 ns - 0.30 ns - 0.48 ns = 0.328 ns.
This is a test method that is within practical test error of the worst-case 0.31 ns limit.
•
•
Input optical rise and fall times (10% - 90%) are 0.7 ns and 0.9 ns respectively.
Transmitter operating with a 622.08 MBd, 311.04 MHz square wave input signal to simulate any cross talk present between the transmitter and
receiver sections of the transceiver.
14
KEY:
XXXX-XXXX
YYWW = DATE CODE
FOR MULTIMODE MODULES:
XXXX-XXXX = HFBR-5208EMZ
COUNTRY OF ORIGIN YYWW
TX
RX
29.6
(1.16)
UNCOMPRESSED
39.6
(1.56)
12.7
(0.50)
4.7
(0.185)
MAX.
AREA
RESERVED
FOR
25.4 MAX.
12.7
PROCESS
PLUG
(1.00)
(0.50)
18.1
(0.711)
2.0 0.1
(0.079 0.004)
SLOT WIDTH
20.5
(0.805)
3.3
+0.1
-0.05
+0.004
-0.002
(0.13)
2.09
(0.08)
0.25
10.2
(0.40)
UNCOMPRESSED
MAX.
(
0.010
)
9.8 MAX.
(0.386)
1.3
(0.05)
3.3 0.38
(0.130 0.015)
5.9
(0.23)
20.32
(0.800)
15.8 0.15
(0.622 0.006)
+0.25
-0.05
+0.010
0.018
-0.002
+0.25
-0.05
+0.010
0.050
-0.002
0.46
9X Ø
1.27
)
(
2X Ø
(
)
8X
20.32
(0.800)
23.8
(0.937)
2.54
(0.100)
20.32
(0.800)
14.5
(0.57)
13.6
(0.54)
1.3
(0.051)
2X Ø
Masked insulator material (no metalization)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
TOLERANCES:
X.XX
X.X
0.025 mm
0.05 mm
UNLESS OTHERWISE SPECIFIED.
Figure 8. Package Outline for HFBR-5208EMZ
15
0.8
(0.032)
2X
0.8
(0.032)
2X
+0.5
-0.25
+0.02
-0.01
10.9
)
0.43
)
9.4
(0.37)
27.4 0.50
(1.08 0.02)
6.35
(0.25)
MODULE
PROTRUSION
3.5
PCB BOTTOM VIEW
(0.14)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
TOLERANCES:
X.XX
X.X
0.025 mm
0.05 mm
UNLESS OTHERWISE SPECIFIED.
Figure 9. Suggested Module Positioning and Panel Cut-out for HFBR-5208EMZ
16
Ordering Information
1300 nm LED (temperature range 0°C to +70°C)
HFBR-5208MZ
HFBR-5208EMZ
No shield, metallized housing.
Extended/protruding shield, metallized housing.
1300 nm LED (temperature range -40°C to +85°C)
HFBR-5208AMZ
HFBR-5208AEMZ
No shield, metallized housing.
Extended/protruding shield, metallized housing.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-4726EN
AV02-2549EN - February 9, 2012
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