HFBR-5803T [AVAGO]
DATACOM, ETHERNET TRANSCEIVER, XFO9, LOW PROFILE, SIP-9;
| 型号： | HFBR-5803T |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | DATACOM, ETHERNET TRANSCEIVER, XFO9, LOW PROFILE, SIP-9 以太网：16GBASE-T 光纤 |
| 文件： | 总15页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFBR-5803/5803T/5803A/5803AT
FDDI, 100 Mb/s ATM, and Fast Ethernet Transceivers in
Low Cost 1 x 9 Package Style
Data Sheet
Features
Description
•
Full ompliane with the optial performane
requirements of the FDDI PMD standard
The HFBR-5800 family of transeivers from Avago Teh-
nologies provide the system designer with produts
to implement a range of Fast Ethernet, FDDI and ATM
(Asynhronous Transfer Mode) designs at the 100 Mb/s-
125 MBd rate.
•
•
Full ompliane with the FDDI LCF-PMD standard
Full ompliane with the optial performane
requirements of the ATM 100 Mb/s physial layer
Full ompliane with the optial performane
requirements of 100 Base-FX version of IEEE802.3u
Multisoured 1 x 9 pakage style with hoie of
duplex SC or duplex ST* reeptale
•
•
The transeivers are all supplied in the industry standard
1 x 9 SIP pakage style with either a duplex SC or a duplex
ST* onnetor interfae.
FDDI PMD, ATM and Fast Ethernet 2 km Backbone
Links
The HFBR-5803/5803 Tare 1300nm produts with
optial performane ompliant with the FDDI PMD
standard. The FDDI PMD standard is ISO/IEC 9314-3:
1990 and ANSI X3.166 - 1990.
•
•
•
Wave solder and aqueous wash proess ompatible
Manufatured in an ISO 9002 ertified faility
Single +3.3 V or +5 V power supply
Applications
•
•
•
Multimode fiber bakbone links
Multimode fiber wiring loset to desktop links
Very low ost multimode fiber
links from wiring loset to desktop
Multimode fiber media onverters
Thesetranseiversfor2kmmultimodefiberbakbonesare
supplied in the small 1 x 9 duplex SC or ST pakage style.
•
The HFBR-5803/-5803T is useful for both ATM 100 Mb/s
interfaes and Fast Ethernet 100 Base-FX interfaes. The
ATMForumUser-NetworkInterfae(UNI)Standard,Version
3.0, defines the Physial Layer for 100 Mb/s Multimode
Fiber Interfae for ATM in Setion 2.3 to be the FDDI PMD
Standard. Likewise, the Fast Ethernet Alliane defines the
Physial Layer for 100 Base-FX for Fast Ethernet to be the
FDDI PMD Standard.
*ST is a registered trademark of AT&T Lightguide Cable Connetors.
Note: The “T”in the produt numbers
indiates a transeiver with a duplex ST onnetor reeptale.
Produt numbers without a “T”indiate transeivers with a duplex SC
onnetor reeptale.
Ordering Information
ATM appliations for physial layers other than 100 Mb/s
Multimode Fiber Interfae are supported by Avago Teh-
nologies. Produts are available for both the single mode
and the multimode fiber SONET OC-3 (STS-3) ATM in-
terfaes and the 155 Mb/s-194 MBd multimode fiber ATM
interfae as speified in the ATM Forum UNI.
The HFBR-5803/5803T/5803A/5803AT 1300 nm produts
are available for prodution orders through the Avago
Tehnologies Component Field Sales Offies and Autho-
rized Distributors world wide.
0 °C to +70 °C
HFBR-5803/5803T
Contat your Avago Tehnologies sales representative
for information on these alternative Fast Ethernet, FDDI
and ATM produts.
-10 °C TO +85 °C
HFBR-5803A/5803AT
Transmitter Sections
The optial subassemblies utilize a high volume assembly
The transmitter setion of the HFBR-5803 and HFBR-5805 proess together with low ost lens elements whih result
seriesutilize1300nmSurfaeEmittingInGaAsPLEDs.These in a ost effetive building blok.
LEDs are pakaged in the optial subassembly portion
The eletrial subassembly onsists of a high volume
of the transmitter setion. They are driven by a ustom
multilayer printed iruit board on whih the IC hips
silion IC whih onverts differential PECL logi signals,
and various surfae-mounted passive iruit elements
ECL referened (shifted) to a +3.3 V or +5 V supply, into
are attahed.
an analog LED drive urrent.
The pakage inludes internal shields for the eletrial
and optial subassemblies to ensure low EMI emissions
and high immunity to external EMI fields.
Receiver Sections
The reeiver setions of the HFBR-5803 and HFBR-5805
seriesutilizeInGaAsPINphotodiodesoupledtoaustom
silion transimpedane preamplifier IC. These are pak-
aged in the optial subassembly portion of the reeiver.
reeptale or the duplex ST ports is molded of filled non-
The outer housing inluding the duplex SC onnetor
ondutive plasti to provide mehanial strength and
These PIN/preamplifier ombinations are oupled to a
eletrial isolation. The solder posts of the Agilent design
ustom quantizer IC whih provides the final pulse shap-
are isolated from the iruit design of the transeiver
ing for the logi output and the Signal Detet funtion.
and do not require onnetion to a ground plane on the
The data output is differential. The signal detet output
iruit board.
is single-ended. Both data and signal detet outputs are
PECL ompatible, ECL referened (shifted) to a +3.3 V or
+5 V power supply.
The transeiver is attahed to a printed iruit board with
the nine signal pins and the two solder posts whih exit
the bottom of the housing. The two solder posts provide
the primary mehanial strength to withstand the loads
Package
The overall pakage onept for the Avago Tehnologies
imposed on the transeiver by mating with duplex or
transeivers onsists of the following basi elements; two
simplex SC or ST onnetored fiber ables.
optial subassemblies, an eletrial subassembly and the
housing as illustrated in Figure1 and Figure 1a.
The pakage outline drawings and pin out are shown in
Figures 2, 2a and 3.The details of this pakage outline and
pin out are ompliant with the multisoure definition of
the 1 x 9 SIP. The low profile of the Avago Tehnologies
transeiver design omplies with the maximum height al-
lowed for the duplex SC onnetor over the entire length
of the pakage.
ELECTRICAL SUBASSEMBLY
DUPLEX SC
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
DATA IN
LED
DRIVER IC
TOP VIEW
Figure 1. SC Connector Block Diagram.
ꢀ
ELECTRICAL SUBASSEMBLY
DUPLEX ST
RECEPTACLE
DIFFERENTIAL
DATA OUT
PIN PHOTODIODE
SINGLE-ENDED
SIGNAL
DETECT OUT
QUANTIZER IC
PREAMP IC
OPTICAL
SUBASSEMBLIES
DIFFERENTIAL
DATA IN
LED
DRIVER IC
TOP VIEW
Figure 1a. ST Connector Block Diagram.
Case Temperature
Measurement Point
39.12
(1.540)
12.70
(0.500)
MAX.
6.35
(0.250)
AREA
RESERVED
FOR
PROCESS
PLUG
25.40
MAX.
12.70
(0.500)
(1.000)
HFBR-5ꢀ03
DATE CODE (YYWW)
SINGAPORE
AGILENT
5.93 0.1
(0.233 0.004)
+ 0.0ꢀ
0.75
– 0.05
3.30 0.3ꢀ
(0.130 0.015)
3.30 0.3ꢀ
(0.130 0.015)
+ 0.003
10.35
(0.407)
)
(0.030
MAX.
– 0.002
2.92
(0.115)
+ 0.25
– 0.05
1ꢀ.52
(0.729)
1.27
+ 0.010
– 0.002
0.46
(0.01ꢀ)
NOTE 1
4.14
(0.163
(0.050
)
Ø
(9x)
NOTE 1
23.55
(0.927)
20.32
(0.ꢀ00)
16.70
(0.657)
17.32 20.32
(0.6ꢀ2 (0.ꢀ00) (0.91ꢀ)
23.32
[ꢀx(2.54/.100)]
0.ꢀ7
23.24
(0.915)
15.ꢀꢀ
(0.625)
(0.034)
NOTE 1: THE SOLDER POSTS AND ELECTRICAL PINS ARE PHOSPHOR BRONZE WITH TIN LEAD OVER NICKEL PLATING.
DIMENSIONS ARE IN MILLIMETERS (INCHES).
Figure 2. SC Connector Package Outline Drawing with standard height.
ꢁ
42
(1.654)
MAX.
5.99
(0.236)
24.ꢀ
(0.976)
12.7
(0.500)
25.4
(1.000)
MAX.
HFBR-5ꢀ03T
DATE CODE (YYWW)
SINGAPORE
Case Temperature
Measurement Point
+ 0.0ꢀ
- 0.05
+ 0.003
0.5
(0.020)
(
- 0.002
(
12.0
(0.471)
MAX.
2.6 0.4
(0.102 0.016)
3.3 0.3ꢀ
(0.130 0.015)
0.3ꢀ
0.015)
20.32
(
0.46
Ø
(0.01ꢀ)
NOTE 1
2.6
Ø
+ 0.25
- 0.05
1.27
(0.102)
(0.050)
(
+ 0.010
- 0.002
)
20.32
(0.ꢀ00)
17.4
(0.6ꢀ5)
[(ꢀx (2.54/0.100)]
20.32
(0.ꢀ00)
22.ꢀ6
21.4
(0.ꢀ43)
(0.900)
3.6
(0.142)
1.3
(0.051)
23.3ꢀ
1ꢀ.62
(0.921)
(0.733)
NOTE 1: PHOSPHOR BRONZE IS THE BASE MATERIAL FOR THE POSTS & PINS WITH TIN LEAD OVER NICKEL PLATING.
DIMENSIONS IN MILLIMETERS (INCHES).
Figure 2a. ST Connector Package Outline Drawing with standard height.
1 = VEE
N/C
2 = RD
Rx
Tx
3 = RD
4 = SD
5 = VCC
6 = VCC
7 = TD
ꢀ = TD
9 = VEE
N/C
TOP VIEW
Figure 3. Pin Out Diagram.
ꢂ
Application Information
The Appliations Engineering group in the Avago Teh-
nologies Fiber Optis Communiation Division is avail-
able to assist you with the tehnial understanding and
design trade-offs assoiated with these transeivers. You
an ontat them through your AvagoTehnologies sales
representative.
Figure 4 was generated with a Avago Tehnologies fiber
opti link model ontaining the urrent industry onven-
tions for fiber able speifiations and the FDDI PMD
and LCF-PMD optial parameters. These parameters are
refletedintheguaranteedperformaneofthetranseiver
speifiationsinthisdatasheet.Thissamemodelhasbeen
usedextensivelyintheANSIandIEEEommittees,inluding
theANSIX3T9.5ommittee,toestablishtheoptialperfor-
mane requirements for various fiber opti interfae stan-
dards. The able parameters used ome from the ISO/IEC
JTC1/SC25/WG3GeneriCablingforCustomerPremisesper
DIS 11801 doument and the EIA/TIA-568-A Commerial
Building Teleommuniations Cabling Standard per SP-
2840.
The following information is provided to answer some
of the most ommon questions about the use of these
parts.
Transceiver Optical Power Budget versus Link
Length
Optial Power Budget (OPB) is the available optial power
forafiberoptilinktoaommodatefiberablelossesplus
losses due to in-line onnetors, splies, optial swithes,
andtoprovidemarginforlinkagingandunplannedlosses
due to able plant reonfiguration or repair.
Transceiver Signaling Operating Rate Range and BER
Performance
For purposes of definition, the symbol (Baud) rate, also
alled signaling rate, is the reiproal of the shortest
symbol time. Data rate (bits/se) is the symbol rate di-
vided by the enoding fator used to enode the data
(symbols/bit).
Figure 4 illustrates the predited OPB assoiated with the
transeiver series speified in this data sheet at the Begin-
ning of Life (BOL). These urves represent the attenuation
and hromati plus modal dispersion losses assoiated
with the 62.5/125 µm and 50/125 µm fiber ables only.
The area under the urves represents the remaining OPB
at any link length, whih is available for overoming non-
fiber able related losses.
When used in Fast Ethernet, FDDI and ATM 100 Mb/s
appliations the performane of the 1300 nm transeiv-
ers is guaranteed over the signaling rate of 10 MBd to
125 MBd to the full onditions listed in individual produt
speifiation tables.
Avago Tehnologies LED tehnology has produed 1300
nm LED devies with lower aging harateristis than nor-
mally assoiated with these tehnologies in the industry.
The industry onvention is 1.5 dB aging for 1300 nm LEDs.
TheAvagoTehnologies1300nmLEDswillexperieneless
than 1dB of aging over normal ommerial equipment
mission life periods. Contat your Avago Tehnologies
sales representative for additional details.
2.5
2.0
1.5
1.0
0.5
0
12
HFBR-5ꢀ03, 62.5/125 µm
10
0.5
0
25 50
75 100 125 150 175 200
SIGNAL RATE (MBd)
ꢀ
CONDITIONS:
1. PRBS 27-1
2. DATA SAMPLED AT CENTER OF DATA SYMBOL.
3. BER = 10-6
HFBR-5ꢀ03
50/125 µm
6
4. TA = +25˚ C
5. VCC = 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
4
2
Figure 5. Transceiver Relative Optical Power Budget at Constant
BER vs. Signaling Rate.
1.
0
0
0.3 0.5
1.5
2.0
2.5
The transeivers may be used for other appliations at
signalingratesoutsideofthe10MBdto125MBdrangewith
some penalty in the link optial power budget primarily
aused by a redution of reeiver sensitivity. Figure 5 gives
an indiation of the typial performane of these 1300 nm
produts at different rates.
FIBER OPTIC CABLE LENGTH (km)
Figure 4. Optical Power Budget at BOL versus Fiber Optic Cable
Length.
These transeivers an also be used for appliations whih
require different Bit Error Rate (BER) performane. Figure 6
illustrates the typial trade-off between link BER and the
reeivers input optial power level.
ꢃ
1 x 10-2
1 x 10-3
1 x 10-4
Rx
Tx
HFBR-5ꢀ03 SERIES
1 x 10-5
1 x 10-6
1 x 10-7
NO INTERNAL CONNECTION
NO INTERNAL CONNECTION
CENTER OF SYMBOL
1 x 10-ꢀ
1 x 10-9
1 x 10-10
1 x 10-11
1 x 10-12
HFBR-5ꢀ03
TOP VIEW
-6
-4
-2
0
2
4
Rx
VEE
1
Rx
Tx
Tx
RELATIVE INPUT OPTICAL POWER - dB
RD
2
RD
3
SD
4
VCC
VCC
TD
7
TD
ꢀ
VEE
5
6
9
CONDITIONS:
1. 155 MBd
2. PRBS 27-1
3. CENTER OF SYMBOL SAMPLING
4. TA = +25˚C
C1
C2
5. VCC = 3.3 V to 5 V dc
6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.
VCC
R2
R3
L1
L2
C4
Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.
TERMINATION
AT PHY
DEVICE
INPUTS
R1
R4
VCC
C3
C5
Transceiver Jitter Performance
VCC FILTER
AT VCC PINS
R5
R7
The Avago Tehnologies 1300 nm transeivers are de-
signed to operate per the system jitter alloations stated
in Tables E1 of Annexes E of the FDDI PMD and LCF-PMD
standards.
TRANSCEIVER
R9
TERMINATION
AT TRANSCEIVER
INPUTS
C6
R6
Rꢀ
R10
RD
RD
SD
VCC
TD
TD
TheAvagoTehnologies1300nmtransmitterswilltolerate
theworstaseinputeletrialjitterallowedinthesetables
withoutviolatingtheworstaseoutputjitterrequirements
of Setions 8.1 Ative Output Interfae of the FDDI PMD
and LCF-PMD standards.
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT
OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT
BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = Rꢀ = R10 = 130 OHMS FOR +5.0 V OPERATION, ꢀ2 OHMS FOR +3.3 V OPERATION.
R2 = R3 = R5 = R7 = R9 = ꢀ2 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.
C1 = C2 = C3 = C5 = C6 = 0.1 µF.
C4 = 10 µF.
L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.
TheAvagoTehnologies1300nmreeiverswilltoleratethe
worstaseinputoptialjitterallowedinSetions8.2Ative
Input Interfae of the FDDI PMD and LCF-PMD standards
without violating the worst ase output eletrial jitter
allowed in the Tables E1 of the Annexes E.
Figure 7. Recommended Decoupling and Termination Circuits
The jitter speifiations stated in the following 1300 nm
transeiverspeifiationtablesarederivedfromthevalues
in Tables E1 of Annexes E. They represent the worst ase
jitterontributionthatthetranseiversareallowedtomake
to the overall system jitter without violating the Annex E
alloation example. In pratie the typial ontribution of
the Avago Tehnologies transeivers is well below these
maximum allowed amounts.
Recommended Handling Precautions
Avago Tehnologies reommends that normal stati pre-
autions be taken in the handling and assembly of these
transeivers to prevent damage whih may be indued
by eletrostati disharge (ESD). The HFBR-5800 series of
transeivers meet MIL-STD-883C Method 3015.4 Class 2
produts.
Care should be used to avoid shorting the reeiver data or
signal detet outputs diretly to ground without proper
urrent limiting impedane.
ꢄ
Solder and Wash Process Compatibility
Board Layout - Hole Pattern
The transeivers are delivered with protetive proess The Avago Tehnologies transeiver omplies with the
plugs inserted into the duplex SC or duplex ST onnetor iruitboard“CommonTranseiverFootprint”holepattern
reeptale. This proess plug protets the optial subas- definedinthe originalmultisoureannounementwhih
sembliesduringwavesolderandaqueouswashproessing definedthe1x9pakagestyle.Thisdrawingisreprodued
and ats as a dust over during shipping.
in Figure 8 with the addition of ANSI Y14.5M ompliant
dimensioning to be used as a guide in the mehanial
layout of your iruit board.
These transeivers are ompatible with either industry
standard wave or hand solder proesses.
Board Layout - Art Work
Shipping Container
The Appliations Engineering group has developed
Gerber file artwork for a multilayer printed iruit board
layout inorporating the reommendations above. Con-
tat your loal Avago Tehnologies sales representative
for details.
The transeiver is pakaged in a shipping ontainer de-
signed to protet it from mehanial and ESD damage
during shipment or storage.
Board Layout - Decoupling Circuit and Ground
Planes
Board Layout - Mechanical
Itisimportanttotakeareinthelayoutofyouriruitboard
toahieveoptimumperformanefromthesetranseivers.
Figure 7 provides a good example of a shemati for a
powersupplydeouplingiruitthatworkswellwiththese
parts.Itisfurtherreommendedthataontiguous ground
plane be provided in the iruit board diretly under the
ForappliationsprovidingahoieofeitheraduplexSCor
a duplex ST onnetor interfae, while utilizing the same
pinout on the printed iruit board, the ST port needs to
protrude from the hassis panel a minimum of 9.53 mm
for suffiient learane to install the ST onnetor.
transeiver to provide a low indutane ground for signal Please refer to Figure 8a for a mehanial layout detailing
return urrent. This reommendation is in keeping with the reommended loation of the duplex SC and duplex
good high frequeny board layout praties.
ST transeiver pakages in relation to the hassis panel.
2 x Ø 1.9 0.1
(0.075 0.004)
20.32
(0.ꢀ00)
9 x Ø 0.ꢀ 0.1
(0.032 0.004)
20.32
(0.ꢀ00)
2.54
(0.100)
TOP VIEW
DIMENSIONS ARE IN MILLIMETERS (INCHES)
Figure 8. Recommended Board Layout Hole Pattern
ꢅ
42.0
24.ꢀ
9.53
12.0
(NOTE 1)
0.51
12.09
25.4
39.12
11.1
6.79
0.75
25.4
NOTE 1: MINIMUM DISTANCE FROM FRONT
OF CONNECTOR TO THE PANEL FACE.
Figure 8a. Recommended Common Mechanical Layout for SC and ST 1 x 9 Connectored Transceivers.
Electrostatic Discharge (ESD)
Regulatory Compliance
There are two design ases in whih immunity to ESD
damage is important.
These transeiver produts are intended to enable om-
merialsystemdesignerstodevelopequipmentthatom-
plies with the various international regulations governing
ertifiation of Information Tehnology Equipment. See
the Regulatory Compliane Table for details. Additional
information is available from your Avago Tehnologies
sales representative.
The first ase is during handling of the transeiver prior
to mounting it on the iruit board. It is important to use
normalESDhandlingpreautionsforESDsensitivedevies.
These preautions inlude using grounded wrist straps,
work benhes, and floor mats in ESD ontrolled areas.
The seond ase to onsider is stati disharges to the
exterior of the equipment hassis ontaining the trans-
eiver parts. To the extent that the duplex SC onnetor
is exposed to the outside of the equipment hassis it may
be subjet to whatever ESD system level test riteria that
the equipment is intended to meet.
ꢆ
Regulatory Compliance Table
Feature
Test Method
Performance
Eletrostati Disharge (ESD) to MIL-STD-883C
Meets Class 1 (<1999 Volts)
the Eletrial Pins
Method 3015.4
Withstand up to 1500 V applied between eletrial pins.
Eletrostati Disharge (ESD) to Variation of
the Duplex SC Reeptale IEC 801-2
Typially withstand at least 25 kV without damage when the Duplex SC
Connetor Reeptale is ontated by a Human Body Model probe.
Eletromagneti Interferene FCC Class B
Typially provide a 13 dB margin (with duplex SC pakage) or a 9 dB margin
(with duplex ST pakage) to the noted standard limits when tested at a
ertified test range with the transeiver mounted to a iruit ard without a
hassis enlosure.
(EMI)
CENELEC CEN55022
Class B (CISPR 22B)
VCCI Class 2
Immunity
Variation of
IEC 801-3
Typially show no measurable effet from a 10 V/m field swept from 10 to
450 MHz applied to the transeiver when mounted to a iruit ard without a
hassis enlosure.
Electromagnetic Interference (EMI)
Immunity
Most equipment designs utilizing these highspeed trans- Equipment utilizing these transeivers will be subjet to
eivers from AvagoTehnologies will be required to meet radio-frequeny eletromagneti fields in some environ-
the requirements of FCC in the United States, CENELEC ments. These transeivers have a high immunity to suh
EN55022 (CISPR 22) in Europe and VCCI in Japan.
fields.
In all well-designed hassis, two 0.5”holes for ST onne- ForadditionalinformationregardingEMI,suseptibility,ESD
tors to protrude through will provide 4.6dB more shield- andondutednoisetestingproeduresandresultsonthe
ing than one 1.2” duplex SC retangular utout. Thus, in 1 x 9 Transeiver family, please refer to Appliations Note
a well-designed hassis, the duplex ST 1 x 9 transeiver 1075, Testing and Measuring Eletromagneti Compat-
emissions will be idential to the duplex SC 1 x 9 trans- ibility Performane of the HFBR-510X/520X Fiber Opti
eiver emissions.
Transeivers.
200
Transceiver Reliability and Performance Qualification
Data
The 1 x 9 transeivers have passed Avago Tehnologies’
reliability and performane qualifiation testing and are
undergoingongoingqualitymonitoring.Detailsareavail-
able from your Avago Tehnologies sales representative.
3.0
3.5
1ꢀ0
1.5
160
2.0
140
120
100
2.5
These transeivers are manufatured at the Avago Teh-
nologiesSingaporeloationwhihisanISO9002ertified
faility.
3.0
3.5
t
– TRANSMITTER
r/f
OUTPUT OPTICAL
RISE/FALL TIMES – ns
1200 1300 1320 1340 1360 13ꢀ0
Applications Support Materials
λ
– TRANSMITTER OUTPUT OPTICAL
CENTER WAVELENGTH –nm
C
Contat your loal Avago Tehnologies Component Field
Sales Offie for information on how to obtain PCB layouts,
test boards and demo boards for the 1 x 9 transeivers.
HFBR-5103 FDDI TRANSMITTER TEST RESULTS
OF λ , ∆λ AND t ARE CORRELATED AND
C
r/f
COMPLY WITH THE ALLOWED SPECTRAL WIDTH
AS A FUNCTION OF CENTER WAVELENGTH FOR
VARIOUS RISE AND FALL TIMES.
Accessory Duplex SC Connectored Cable Assemblies
Avago Tehnologies reommends for optimal oupling
the use of flexible-body duplex SC onnetored able.
Figure 9. Transmitter Output Optical Spectral Width (FWHM)
vs. Transmitter Output Optical Center Wavelength and Rise/Fall
Times.
Accessory Duplex ST Connectored Cable Assemblies
AvagoTehnologiesreommendstheuseofDuplexPush-
Pull onnetored able for the most repeatable optial
power oupling performane.
ꢇ
ꢂꢈꢂ0
1ꢈꢇꢅꢃ
1ꢈꢀꢃ
ꢂꢈꢆꢃ0
1ꢈꢃꢀꢃ
0ꢈꢃꢀꢃ
10ꢈ0
ꢃꢈꢄ
1ꢈ0ꢀꢃ
1ꢈ00
0ꢈꢇꢅꢃ
0ꢈ0ꢅꢃ
0ꢈꢇ0
100% TIME
INTERVAL
ꢂ0 0ꢈꢅ
0ꢈꢃ0
0ꢈ10
0ꢈꢅꢀꢃ
0ꢈꢅꢀꢃ
0% TIME
INTERVAL
0ꢈ0ꢀꢃ
0ꢈ0
0ꢈ0ꢅꢃ
-0ꢈ0ꢀꢃ
-0ꢈ0ꢃ
1ꢈꢃꢀꢃ
0ꢈꢃꢀꢃ
ꢃꢈꢄ
1ꢈꢇꢅꢃ
ꢂꢈꢂ0
10ꢈ0
ꢂꢈꢆꢃ0
ꢆ0 ꢃ00 ꢉꢉp
TIME – ns
THE HFBR-ꢃ10ꢁ OUTPUT OPTICAL PULSE SHAPE SHALL FIT WITHIN THE BOUNDARIES
OF THE PULSE ENVELOPE FOR RISE AND FALL TIME MEASUREMENTSꢈ
Figure 10. Output Optical Pulse Envelope.
ꢃ
HFBR-ꢃ10ꢁ/-ꢃ10ꢂ/-ꢃ10ꢃ
SERIES
ꢂ
ꢁ
-10
ꢀꢈꢃ x 10 BER
ꢀ
-1ꢀ
1ꢈ0 x 10 BER
1
0
-ꢂ -ꢁ -ꢀ -1
0
1
ꢀ
ꢁ
ꢂ
EYE SAMPLING TIME POSITION (ns)
CONDITIONS:
1ꢈTA = ꢀꢃ C
ꢀꢈ VCC = ꢃ Vdc
ꢁꢈ INPUT OPTICAL RISE/FALL TIMES = 1ꢈ0/ꢀꢈ1 nsꢈ
ꢂꢈ INPUT OPTICAL POWER IS NORMALIZED TO
CENTER OF DATA SYMBOLꢈ
ꢃꢈ NOTE ꢀ0 AND ꢀ1 APPLYꢈ
Figure 11. Relative Input Optical Power vs. Eye Sampling Time Position.
10
-ꢁ1ꢈ0 dBp
MIN (PO + ꢂꢈ0 dB OR -ꢁ1ꢈ0 dBp)
PO = MAX (PS OR -ꢂꢃꢈ0 dBp)
PA(PO + 1ꢈꢃ dB
< PA < -ꢁ1ꢈ0 dBp)
ꢀ
(PS = INPUT POWER FOR BER < 10 )
INPUT OPTICAL POWER
( 1ꢈꢃ dB STEP INCREASE)
INPUT OPTICAL POWER
>
( ꢂꢈ0 dB STEP DECREASE)
>
-ꢂꢃꢈ0 dBp
ANS MAX
–
AS MAX
–
SIGNAL DETECT
–
(ON)
SIGNAL DETECT
–
(OFF)
TIME
AS MAX — MAXIMUM ACQUISITION TIME (SIGNAL)ꢈ
–
AS MAX IS THE MAXIMUM SIGNAL DETECT ASSERTION TIME FOR THE STATIONꢈ
–
–
AS MAX SHALL NOT EXCEED 100ꢈ0 µsꢈ THE DEFAULT VALUE OF AS MAX IS 100ꢈ0 µsꢈ
–
–
ANS MAX — MAXIMUM ACQUISITION TIME (NO SIGNAL)ꢈ
–
ANS MAX IS THE MAXIMUM SIGNAL DETECT DEASSERTION TIME FOR THE STATIONꢈ
–
–
ANS MAX SHALL NOT EXCEED ꢁꢃ0 µsꢈ THE DEFAULT VALUE OF AS MAX IS ꢁꢃ0 µsꢈ
–
–
Figure 12. Signal Detect Thresholds and Timing.
11
Absolute Maximum Ratings
Stresses in exess of the absolute maximum ratings an ause atastrophi damage to the devie. Limits apply to eah parame-
ter in isolation, all other parameters having values within the reommended operating onditions. It should not be assumed that
limiting values of more than one parameter an be applied to the produt at the same time. Exposure to the absolute maximum
ratings for extended periods an adversely affet devie reliability.
Parameter
Symbol
Min.
Typ.
Max.
+100
+260
10
Unit
°C
Reference
Storage Temperature
Lead Soldering Temperature
Lead Soldering Time
Supply Voltage
T
S
-40
T
°C
SOLD
SOLD
t
se.
V
V
V
V
-0.5
-0.5
7.0
CC
I
Data Input Voltage
Differential Input Voltage
V
V
CC
1.4
50
V
Note 1
D
Output Current
I
mA
O
Recommended Operating Conditions
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Ambient Operating Temperature
HFBR-5803/5803T
HFBR-5803A/5803AT
TA
TA
0
-10
+70
+85
°C
°C
Note A
Note B
Supply Voltage
VCC
VCC
3.135
4.75
3.5
5.25
V
V
Data Input Voltage - Low
Data Input Voltage - High
VIL - VCC
VIH - VCC
RL
-1.810
-1.165
-1.475
-0.880
V
V
Data and Signal Detet Output Load
50
W
Note 2
Notes:
A. Ambient Operating Temperature orresponds to transeiver ase temperature of 0°C mininum to +85 °C maximum with neessary airflow
applied. Reommended ase temperature measurement point an be found in Figure 2.
B. Ambient Operating Temperature orresponds to transeiver ase temperature of -10 °C mininum to +100 °C maximum with neessary air-
flow applied. Reommended ase temperature measurement point an be found in Figure 2.
Transmitter Electrical Characteristics
(HFBR-5803/5803T: T = 0°C to +70°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
(HFBR-5803A/HFBR-5803AT: T = -10°C to +85°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
Symbol
ICC
Parameter
Min.
Typ.
Max.
Unit
Reference
Supply Current
133
175
mA
Note 3
Power Dissipation
at VCC = 3.3 V
at VCC = 5.0 V
PDISS
PDISS
IIL
0.45
0.76
0.6
W
W
0.97
Data Input Current - Low
Data Input Current - High
-350
-2
µA
µA
18
350
IIH
1ꢀ
Receiver Electrical Characteristics
(HFBR-5803/5803T: T = 0°C to +70°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
(HFBR-5803A/HFBR-5803AT: T = -10°C to +85°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
Parameter
Symbol
Min.
Typ.
87
Max.
120
Unit
mA
W
Reference
Note 4
Supply Current
Power Dissipation
I
CC
at V = 3.3 V
P
P
V
V
0.15
0.3
0.25
Note 5
CC
DISS
at V = 5.0 V
0.5
W
Note 5
CC
DISS
Data Output Voltage - Low
Data Output Voltage - High
Data Output Rise Time
Data Output Fall Time
- V
-1.840
-1.045
0.35
-1.620
-0.880
2.2
V
Note 6
OL
CC
- V
V
Note 6
OH
CC
t
t
ns
Note 7
r
0.35
2.2
ns
Note 7
f
Signal Detet Output Voltage - Low
Signal Detet Output Voltage - High
Signal Detet Output Rise Time
Signal Detet Output Fall Time
V
V
- V
-1.840
-1.045
0.35
-1.620
-0.880
2.2
V
Note 6
Note 6
Note 7
Note 7
OL
CC
- V
V
OH
CC
t
t
ns
ns
r
0.35
2.2
f
Transmitter Optical Characteristics
(HFBR-5803/5803T: T = 0°C to +70°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
(HFBR-5803A/HFBR-5803AT: T = -10°C to +85°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Output Optial Power
BOL
EOL
P
-19
-20
-14
dBm avg.
Note 11
O
O
62.5/125 µm, NA = 0.275 Fiber
Output Optial Power
BOL
EOL
P
-22.5
-23.5
-14
dBm avg.
Note 11
50/125 µm, NA = 0.20 Fiber
Optial Extintion Ratio
0.05
0.2
%
Note 12
Note 13
Note 14
Output Optial Power at Logi “0”State
Center Wavelength
P
(“0”)
-45
dBm avg.
nm
O
l
C
1270
1308
1380
Spetral Width - FWHM
Spetral Width - nm RMS
Dl
147
63
nm
Note 14
Figure 9
Optial Rise Time
t
t
0.6
0.6
1.9
3.0
3.0
ns
ns
Note 14, 15
Figure 9, 10
r
f
Optial Fall Time
1.6
Note 14, 15
Figure 9, 10
Duty Cyle Distortion Contributed by the Transmitter
DCD
0.6
ns p-p
ns p-p
ns p-p
Note 16
Note 17
Note 18
Data Dependent Jitter Contributed by the Transmitter DDJ
0.6
Random Jitter Contributed by the Transmitter
RJ
0.69
1ꢁ
Receiver Optical and Electrical Characteristics
(HFBR-5803/5803T: T = 0°C to +70°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
(HFBR-5803A/HFBR-5803AT: T = -10°C to +85°C, V = 3.135 V to 3.5 V or 4.75 V to 5.25 V)
A
CC
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Input Optial Power Minimum at Window Edge
P
(W)
-33.9
-31
dBm avg.
Note 19
IN Min.
IN Min.
IN Max.
Figure 11
Input Optial Power Minimum at Eye Center
P
(C)
-35.2
-31.8
dBm avg.
Note 20
Figure 11
Input Optial Power Maximum
P
l
-14
dBm avg.
nm
Note 19
Operating Wavelength
1270
1380
0.4
Duty Cyle Distortion Contributed by the Reeiver
DCD
DDJ
RJ
ns p-p
Note 8
Note 9
Note 10
Data Dependent Jitter Contributed by the Reeiver
1.0
ns p-p
Random Jitter Contributed by the Reeiver
Signal Detet - Asserted
2.14
-33
ns p-p
P
A
P
D
+ 1.5 dB
dBm avg.
Note 21, 22
Figure 12
Signal Detet - Deasserted
P
-45
dBm avg.
Note 23, 24
Figure 12
D
Signal Detet - Hysteresis
P
- P
1.5
0
dB
µs
Figure 12
A
D
Signal Detet Assert Time (off to on)
AS_Max
2
8
100
350
Note 21, 22
Figure 12
Signal Detet Deassert Time (on to off)
ANS_Max
0
µs
Note 23, 24
Figure 12
Notes:
1. This is the maximum voltage that an be applied aross the
DifferentialTransmitterDataInputstopreventdamagetothe
input ESD protetion iruit.
10.Random Jitter ontributed by the reeiver is speified with
an IDLE Line State,125 MBd (62.5 MHz square-wave), input
signal. The input optial power level is at maximum “PIN Min.
(W)”. See Appliation Information - Transeiver Jitter Setion
for further information.
2. The outputs are terminated with 50W onneted to VCC -2
V.
3. Thepowersupplyurrentneededtooperatethetransmitteris
providedtodifferentialECLiruitry.Thisiruitrymaintainsa
nearlyonstanturrentflowfromthepowersupply. Constant
urrent operation helps to prevent unwanted eletrial noise
frombeinggeneratedandondutedoremittedtoneighbor-
ing iruitry.
4. This value is measured with the outputs terminated into 50
W onneted to VCC - 2 V and an Input Optial Power level of
-14 dBm average.
5. The power dissipation value is the power dissipated in the
reeiver itself. Power dissipation is alulated as the sum of
the produts of supply voltage and urrents, minus the sum
of the produts of the output voltages and urrents.
6. This value is measured with respet to VCC with the output
terminated into 50 W onneted to VCC - 2 V.
7. Theoutputriseandfalltimesaremeasuredbetween20%and
80% levels with the output onneted to VCC -2 V through 50
W.
8. DutyCyleDistortionontributedbythereeiverismeasured
at the 50% threshold using an IDLE Line State, 125 MBd
(62.5MHzsquare-wave),inputsignal.Theinputoptialpower
level is -20 dBm average. See Appliation Information -Trans-
eiver Jitter Setion for further information.
9. DataDependentJitterontributedbythereeiverisspeified
with the FDDI DDJ test pattern desribed in the FDDI PMD
Annex A.5. The input optial power level is -20 dBm average.
See Appliation Information - Transeiver Jitter Setion for
further information.
11.These optial power values are measured with the following
onditions:
•
The Beginning of Life (BOL) to the End of Life (EOL) optial
power degradation is typially 1.5 dB per the industry on-
vention for long wavelength LEDs. The atual degradation
observed in AvagoTehnologies’1300 nm LED produts is
< 1 dB, as speified in this data sheet.
Over the speified operating voltage and temperature
ranges.
With HALT Line State, (12.5 MHz square-wave), input sig-
nal.
Attheendofonemeterofnotedoptialfiberwithladding
modes removed.
•
•
•
The average power value an be onverted to a peak power
value by adding 3 dB. Higher output optial power transmit-
ters are available on speial request.
12.The Extintion Ratio is a measure of the modulation depth
of the optial signal. The data “0” output optial power is
ompared to the data “1” peak output optial power and
expressed as a perentage. With the transmitter driven by a
HALT Line State (12.5 MHz square-wave) signal, the average
optial power is measured. The data “1” peak power is then
alulated by adding 3 dB to the measured average optial
power. The data “0” output optial power is found by mea-
suring the optial power when the transmitter is driven by a
logi “0” input. The extintion ratio is the ratio of the optial
power at the “0” level ompared to the optial power at the
“1”level expressed as a perentage or in deibels.
1ꢂ
13.The transmitter provides ompliane with the need forTrans-
mit_DisableommandsfromtheFDDISMTlayerbyproviding
anOutputOptialPowerlevelof<-45dBmaverageinresponse
toalogi“0”input.Thisspeifiationappliestoeither62.5/125
µm or 50/125 µm fiber ables.
14.This parameter omplies with the FDDI PMD requirements
forthetrade-offsbetweenenterwavelength,spetralwidth,
and rise/fall times shown in Figure 9.
15.Thisparameteromplieswiththeoptialpulseenvelopefrom
the FDDI PMD shown in Figure 10. The optial rise and fall
times are measured from 10% to 90% when the transmitter
is driven by the FDDI HALT Line State (12.5 MHz square-wave)
input signal.
16.Duty Cyle Distortion ontributed by the transmitter is mea-
sured at a 50% threshold using an IDLE Line State, 125 MBd
(62.5 MHz square-wave), input signal. See Appliation Infor-
mation - Transeiver Jitter Performane Setion of this data
sheet for further details.
jitteromponentsthatisdiffiulttoimplementwithprodu-
tion test equipment.The reeiver an be equivalently tested
to the worst ase FDDI PMD input jitter onditions and meet
theminimumoutputdatawindowtime-widthof2.13ns.This
is aomplished by using a nearly ideal input optial signal
(noDCD, insignifiantDDJandRJ)andmeasuringforawider
windowtime-widthof4.6ns.Thisispossibleduetotheumula-
tive effet of jitter omponents through their superposition
(DCD and DDJ are diretly additive and RJ omponents are
rms additive). Speifially, when a nearly ideal input optial
test signal is used and the maximum reeiver peak-to-peak
jitter ontributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14
ns) exist, the minimum window time-width beomes 8.0 ns
-0.4 ns - 1.0 ns - 2.14 ns = 4.46 ns, or onservatively 4.6ns.
This wider window time-width of 4.6 ns guarantees the FDDI
PMDAnnexEminimumwindowtime-widthof2.13nsunder
worst ase input jitter onditions to the A reeiver.
•
Transmitter operating with an IDLE Line State pattern, 125
MBd (62.5 MHz square-wave), input signal to simulate any
ross-talk present between the transmitter and reeiver
setions of the transeiver.
17.Data Dependent Jitter ontributed by the transmitter is
speified with the FDDI test pattern desribed in FDDI PMD
Annex A.5. See Appliation Information - Transeiver Jitter
Performane Setion of this data sheet for further details.
18.Random Jitter ontributed by the transmitter is speified
with an IDLE Line State, 125 MBd (62.5 MHz square-wave),
20.AllonditionsofNote19applyexeptthatthemeasurement
is made at the enter of the symbol with no window time-
width.
input signal. See Appliation Information - Transeiver Jitter 21.Thisvalueismeasuredduringthetransitionfromlowtohigh
Performane Setion of this data sheet for further details.
levels of input optial power.
19.This speifiation is intended to indiate the performane 22.The Signal Detet output shall be asserted within 100
of the reeiver setion of the transeiver when Input Optial
Power signal harateristis are present per the following
definitions. The Input Optial Power dynami range from the
minimum level (with a window time-width) to the maximum
level is the range over whih the reeiver is guaranteed to
provide output data with a Bit Error Ratio (BER) better than
µs after a step inrease of the Input Optial Power.
The step will be from a low Input Optial Power, -45
dBm, into the range between greater than PA, and
-14 dBm.The BER of the reeiver output will be 10-2 or better
during the time, LS_Max (15 µs) after Signal Detet has been
asserted. See Figure 12 for more information.
or equal to 2.5 x 10-10
.
23.Thisvalueismeasuredduringthetransitionfromhightolow
levels of input optial power. The maximum value will our
when the input optial power is either -45 dBm average or
when the input optial power yields a BER of 10-2 or larger,
whihever power is higher.
•
•
At the Beginning of Life (BOL)
Over the speified operating temperature and voltage
ranges
•
Input symbol pattern is the FDDI test pattern defined in
FDDI PMD Annex A.5 with 4B/5B NRZI enoded data that 24.Signal detet output shall be de-asserted within 350 µs after
ontains a duty yle base-line wander effet of 50kHz.
This sequene auses a near worst ase ondition for inter-
symbol interferene.
a step derease in the Input Optial Power from a level whih
is the lower of; -31 dBm or PD + 4 dB (PD is the power level
at whih signal detet was de-asserted), to a power level of
-45 dBm or less. This step derease will have ourred in less
than 8 ns. The reeiver output will have a BER of 10-2 or bet-
ter for a period of 12 µs or until signal detet is de-asserted.
The input data stream is the Quiet Line State. Also, signal
detet will be de-asserted within a maximum of 350µs after
the BER of the reeiver output degrades above 10-2 for an
input optial data stream that deays with a negative ramp
funtion instead of a step funtion. See Figure 12 for more
information.
•
Reeiver data window time-width is 2.13 ns or greater and
enteredatmid-symbol.Thisworstasewindowtime-width
istheminimumallowedeye-openingpresentedtotheFDDI
PHYPM._Dataindiationinput(PHYinput)pertheexample
inFDDIPMDAnnexE.Thisminimumwindowtime-widthof
2.13nsisbasedupontheworstaseFDDIPMDAtiveInput
Interfae optial onditions for peak-to-peak DCD (1.0 ns),
DDJ (1.2 ns) and RJ (0.76 ns) presented to the reeiver.
To test a reeiver with the worst ase FDDI PMD Ative Input
jitteronditionrequiresexatingontroloverDCD,DDJandRJ
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
5989-3434EN - April 7, 2006
1ꢃ
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