HFBR-5984LZ [AVAGO]
FIBER OPTIC TRANSCEIVER, 1280-1380nm, 200Mbps(Tx), 200Mbps(Rx), BOARD/PANEL MOUNT, LC CONNECTOR, ROHS COMPLIANT PACKAGE-10;
| 型号： | HFBR-5984LZ |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | FIBER OPTIC TRANSCEIVER, 1280-1380nm, 200Mbps(Tx), 200Mbps(Rx), BOARD/PANEL MOUNT, LC CONNECTOR, ROHS COMPLIANT PACKAGE-10 放大器 光纤 |
| 文件： | 总12页 (文件大小：976K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFBR-5984LZ
RoHS Compliant, 200 MBd Low-Cost SBCON Transceivers in
2 x 5 SFF Package Style
Data Sheet
Description
Features
•
•
Fully RoHS Compliant
Multisourced 2 x 5 SFF package style with LC
receptacle
Single +3.3 V power supply
Wave solder and aqueous wash process
compatibility
The HFBR-5984LZ transceiver from Avago
Technologies provides the system designer with
a product to implement the SBCON specification
and to be compatible with IBM ESCON
architecture.
•
•
This transceiver is supplied in the industry
standard 2 x 5 SFF with an LC fiber connector
interface.
•
•
Manufactured in an ISO 9001 certified facility
SBCON 200 MBd specification
Transmitter Sections
Applications
®
•
Interconnection with IBM compatible processors,
The transmitter section of the HFBR-5984LZ
utilizes a 1300 nm InGaAsP LED. This LED is
packaged in the optical subassembly portion of
the transmitter section. It is driven by a custom
silicon IC which converts differential PECL
logic signals, ECL referenced (shifted) to a +3.3
V supply, into an analog LED drive current.
directors and channel attachment units
– Disk and tape drives
– Communication controllers
Data communication equipment
– Local area networks
•
– Point-to-point communication
Receiver Sections
The receiver section of the HFBR-5984LZ
utilizes an InGaAs PIN photodiode coupled to
a custom silicon transimpedance preamplifier
IC. It is packaged in the optical subassembly
portion of the receiver.
This PIN/preamplifier combination is coupled
to a custom quantizer IC which provides the
final pulse shaping for the logic output and the
Signal Detect function. The Data output is
differential. The Signal Detect output is single-
ended. Both Data and Signal Detect outputs are
PECL compatible, ECL referenced (shifted) to a
+3.3 V power supply. The receiver outputs, Data
Out and Data Out Bar, are squelched at Signal
Detect Deassert.
Package
The overall package concept for the Avago The electrical subassembly consists of a high
Technologies transceiver consists of three basic volume multilayer printed circuit board on
elements; the two optical subassemblies, an which the ICs and various surface-mounted
electrical subassembly, and the housing as passive circuit elements are attached.
illustrated in the block diagram in Figure 1.
Both the receiver and transmitter sections
The package outline drawing and pin out are include an internal shield for the electrical and
shown in Figures 2 and 5. The details of this optical subassemblies to ensure high immunity
package outline and pin out are compliant with to external EMI fields.
the multisource definition of the 2 x 5 SFF. The
The solder posts of the Avago Technologies
lowprofileoftheAvagoTechnologies transceiver
design are isolated from the internal circuit of
design complies with the maximum height
the transceiver.
allowed for the LC connector over the entire
length of the package.
The transceiver is attached to a printed circuit
board with the ten signal pins and the two
solder posts which exit the bottom of the
housing. The two solder posts provide the
primary mechanical strength to withstand the
loads imposed on the transceiver by mating
with the LC connectored fiber cables.
The optical subassemblies utilize a high-volume
assembly process together with low-cost lens
elementswhichresultinacost-effectivebuilding
block.
RX SUPPLY
DATA OUT
QUANTIZER IC
DATA OUT
PIN PHOTODIODE
PRE-AMPLIFIER
SUBASSEMBLY
RX GROUND
SIGNAL
DETECT
LC
RECEPTACLE
T GROUND
X
LED
DATA IN
OPTICAL
SUBASSEMBLY
LED DRIVER IC
DATA IN
T SUPPLY
X
Figure 1. Block Diagram.
2
RX
TX
Mounting
Studs/Solder
Posts
Top
View
o
o
o
o
o
RECEIVER SIGNAL GROUND
RECEIVER POWER SUPPLY
SIGNAL DETECT
RECEIVER DATA OUT BAR
RECEIVER DATA OUT
o
o
o
o
o
1
2
3
4
5
10
9
8
7
6
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY)
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Figure 2. Pin Out Diagram.
Pin Descriptions:
Pin 6 Transmitter Power Supply
V
TX:
CC
Pin 1 Receiver Signal Ground V RX:
EE
Provide +3.3 V dc via the recommended
transmitter power supply filter circuit. Locate
the power supply filter circuit as close as
Directly connect this pin to the receiver ground
plane.
possible to the V
TX pin.
CC
Pin 2 Receiver Power Supply V RX:
CC
Pin 7 Transmitter Signal Ground
TX:
Provide +3.3 V dc via the recommended receiver
power supply filter circuit. Locate the power
supply filter circuit as close as possible to the
V
EE
Directly connect this pin to the transmitter
ground plane.
V
RX pin.
CC
Pin 3 Signal Detect SD:
Pin 8 Transmitter Disable T
:
DIS
Normal optical input levels to the receiver
result in a logic “1” output.
No internal connection. Optional feature for
laser based products only.
Low optical input levels to the receiver result
in a fault condition indicated by a logic “0”
output.
Pin 9 Transmitter Data In TD+:
No internal terminations are provided. See
recommended circuit schematic.
This Signal Detect output can be used to drive
a PECL input on an upstream circuit, such as
Signal Detect input or Loss of Signal-bar.
Pin 10 Transmitter Data In Bar TD-:
No internal terminations are provided. See
recommended circuit schematic.
Pin 4 Receiver Data Out Bar RD-:
No internal terminations are provided. See
recommended circuit schematic.
Mounting Studs/Solder Posts
The mounting studs are provided for transceiver
mechanical attachment to the circuit board. It
is recommended that the holes in the circuit
board be connected to chassis ground.
Pin 5 Receiver Data Out RD+:
No internal terminations are provided. See
recommended circuit schematic.
3
Application Information
these technologies in the industry. The industry
convention is 1.5 dB aging for 1300 nm LEDs.
The Applications Engineering group is available
to assist you with the technical understanding The 1300 nm Avago Technologies LEDs are
and design trade-offs associated with these specified to experience less than 1 dB of aging
transceivers. You can contact them through over normal commercial equipment mission life
your Avago Technologies sales representative. periods. Contact your Avago Technologies sales
representative for additional details.
The following information is provided to answer
some of the most common questions about the
use of these parts.
Recommended Handling Precautions
Avago Technologies recommends that normal
static precautions be taken in the handling and
assembly of these transceivers to prevent
damage which may be induced by electrostatic
discharge (ESD). The HFBR-5984LZ series of
transceivers meet MIL-STD-883C Method 3015.4
Class 2 products.
Transceiver Optical Power Budget versus Link Length
Optical Power Budget (OPB) is the available
optical power for a fiber optic link to
accommodate fiber cable losses plus losses due
to in-line connectors, splices, optical switches,
and to provide margin for link aging and
unplanned losses due to cable plant
reconfiguration or repair.
Care should be used to avoid shorting the
receiver data or signal detect outputs directly
to ground without proper current limiting
impedance.
AvagoTechnologiesLEDtechnologyhasproduced
1300 nm LED devices with lower aging
characteristics than normally associated with
PHY DEVICE
VCC (+3.3 V)
TERMINATE AT
TRANSCEIVER INPUTS
Z = 50 Ω
Z = 50 Ω
TD-
LVPECL
100 Ω
TD+
130 Ω
130 Ω
10
9
8
7
6
VCC (+3.3 V)
1 µH
10 µF
TX
C2
C3
VCC (+3.3 V)
RX
1 µH
C1
RD+
RD-
1
2
3
4
5
Z = 50 Ω
100 Ω
LVPECL
Z = 50 Ω
Z = 50 Ω
V
CC (+3.3 V)
130 Ω
130 Ω
130 Ω
82 Ω
SD
TERMINATE AT
DEVICE INPUTS
Note: C1 = C2 = C3 = 10 nF or 100 nF
Figure 3. Recommended Decoupling and Termination Circuits
4
Solder and Wash Process Compatibility
Board Layout - Decoupling Circuit, Ground Planes
and Termination Circuits
The transceivers are delivered with protective
process plugs inserted into the LC receptacle. It is important to take care in the layout of your
This process plug protects the optical circuit board to achieve optimum performance
subassemblies during wave solder and aqueous from these transceivers. Figure 4 provides a
wash processing and acts as a dust cover during good example of a schematic for a power supply
shipping.
decoupling circuit that works well with these
parts.Itisfurtherrecommendedthatacontiguous
ground plane be provided in the circuit board
directly under the transceiver to provide a low
inductance ground for signal return current.
This recommendation is in keeping with good
high frequency board layout practices. Figures
3 and 4 show two recommended termination
schemes.
These transceivers are compatible with either
industrystandardwaveorhandsolderprocesses.
Shipping Container
The transceiver is packaged in a shipping
containerdesignedtoprotectitfrommechanical
and ESD damage during shipment or storage.
TERMINATE AT
TRANSCEIVER INPUTS
PHY DEVICE
VCC (+3.3 V)
VCC (+3.3 V)
10 nF
130 Ω
130 Ω
Z = 50 Ω
TD-
LVPECL
Z = 50 Ω
TD+
82 Ω
82 Ω
10
9
8
7
6
VCC (+3.3 V)
VCC (+3.3 V)
1 µH
C2
TX
V
CC (+3.3 V)
10 nF
10 µF
C3
RX
130 Ω
130 Ω
RD+
RD-
1 µH
C1
1
2
3
4
5
LVPECL
Z = 50 Ω
VCC (+3.3 V)
10 nF
Z = 50 Ω
Z = 50 Ω
82 Ω
82 Ω
130 Ω
SD
82 Ω
TERMINATE AT DEVICE INPUTS
Note: C1 = C2 = C3 = 10 nF or 100 nF
Figure 4. Alternative Termination Circuits
5
Board Layout - Hole Pattern
Board Layout - Art Work
The Avago Technologies transceiver complies The Applications Engineering group has
with the circuit board “Common Transceiver developed a Gerber file artwork for a multilayer
Footprint” hole pattern defined in the original printed circuit board layout incorporating the
multisource announcement which defined the 2 recommendations above. Contact your local
x 5 SFF package style. This drawing is repro- Avago Technologies sales representative for
duced in Figure 6 with the addition of ANSI details.
Y14.5M compliant dimensioning to be used as
a guide in the mechanical layout of your circuit
board. Figure 6 illustrates the recommended
panel opening and the position of the circuit
board with respect to this panel.
Figure 5. Package Outline Drawing
6
Figure 6. Recommended Board Layout Hole Pattern and Panel Opening
Electrostatic Discharge (ESD)
There are two design cases in which immunity The second case to consider is static discharges
to ESD damage is important.
to the exterior of the equipment chassis con-
taining the transceiver parts. To the extent that
the LC connector is exposed to the outside of
the equipment chassis it may be subject to
whatever ESD system level test criteria that the
equipment is intended to meet.
Thefirstcaseisduringhandlingofthetransceiver
prior to mounting it on the circuit board. It is
important to use normal ESD handling
precautions for ESD sensitive devices. These
pre-cautions include using grounded wrist
straps, work benches, and floor mats in ESD
controlled areas.
7
Regulatory Compliance
Transceiver Reliability and Performance
Qualification Data
These transceiver products are intended to
enable commercial system designers to develop The 2 x 5 SFF transceivers have passed Avago
equipment that complies with the various Technologies reliability and performance
international regulations governing certifica- qualification testing and are undergoing ongoing
tion of Information Technology Equipment. See quality and reliability monitoring. Details are
the Regulatory Compliance Table for details. available from your Avago Technologies sales
Additional information is available from your representative.
Avago Technologies sales representative.
These transceivers are manufactured at the
Avago Technologies Singapore location which is
an ISO 9001 certified facility.
Electromagnetic Interference (EMI)
Most equipment designs utilizing this high
Ordering Information
speed transceiver from Avago Technologies will
be required to meet the requirements of FCC in
the United States, CENELEC EN55022 (CISPR
22) in Europe and VCCI in Japan.
The HFBR-5984LZ 1300 nm product is available
for production orders through the Avago
Technologies Component There are two design
cases in which immunity to Field Sales Offices
and Authorized Distributors world wide.
This product is suitable for use in designs
ranging from a desktop computer with a single
transceiver to a concentrator or switch product
with a large number of transceivers.
Fortechnicalinformationregardingthisproduct,
please visit Avago Technologies website at
www.avagotech.com.Usethequicksearchfeature
to search for this part number. You may also
contact Avago Technologies Customer Response
Center.
Immunity
Equipment utilizing these transceivers will be
subjecttoradio-frequencyelectromagneticfields
in some environments. These transceivers have
a high immunity to such fields.
Applications Support Materials
Contact your local Avago Technologies
Component Field Sales Office for information
on how to obtain PCB layouts and evaluation
boards for the 2 x 5 SFF transceivers.
For additional information regarding EMI,
susceptibility, ESD and conducted noise testing
procedures and results. Refer to Application
Note 1166 Minimizing Radiated Emissions of
High-Speed Data Communications Systems.
Regulatory Compliance Table
Feature
Test Method
Performance
Electrostatic Discharge
JEDEC/EIA
Meets Class 2 (2000 to 3999 Volts).
(ESD) to the Electrical Pins
JESD22-A114-A and
MIL-STD-883 Method 3015
(Human Body Model)
Variation of
Withstand up to 3000 V applied between electrical pins.
Electrostatic Discharge
(ESD) to the LC Receptacle
Typically withstand at least 25 kV without damage when the LC Connector
Receptacle is contacted by a Human Body Model probe.
IEC 61000-4-2
Electromagnetic
Interference (EMI)
FCC Class B
CENELEC CEN55022 VCCI
Class 2
Transceivers typically provide a 10 dB margin to the noted standard limits
when tested at a certified test range with the transceiver mounted to a
circuit card without a chassis enclosure.
Immunity
Variation of
IEC 61000-4-3
Typically show no measurable effect from a 10 V/m field swept from 80 to
450 MHz applied to the transceiver when mounted to a circuit card without
a chassis enclosure.
Eye Safety
AEL Class 1
EN60825-1 (+A11)
Compliant per Avago Technologies testing under single fault conditions.
TUV Certification #: E9771332-13
UL File #: E173874
8
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to
each parameter in isolation, all other parameters having values within the recommended operating conditions. It
should not be assumed that limiting values of more than one parameter can be applied to the product at the same time.
Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Storage Temperature
TS
-40
+100
+260
10
°C
°C
Sec.
V
Lead Soldering Temperature
Lead Soldering Time
Supply Voltage
TSOLD
tSOLD
VCC
VI
-0.5
-0.5
3.6
Data Input Voltage
Differential Input Voltage
Output Current
VCC
V
VD
2.0
V
Note 1
IO
50
mA
Recommended Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Case Operating Temperature
TC
-20
+85
°C
Supply Voltage
VCC
2.97
3.63
V
Data Input Voltage - Low
Data Input Voltage - High
Data and Signal Detect Output Load
VIL - VCC
VIH - VCC
RL
-1.81
-1.165
-1.475
-0.880
V
V
W
50
Note 2
PCB Assembly Process Compatibility
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Hand Lead Soldering
Temperature
Time
tsolder
ttime
+260
10
°C
sec
Wave Soldering and Aqueous Wash
Temperature
Time
tsolder
ttime
+260
10
110
°C
sec
psi
1
1
Aqueous Wash Pressure
Transmitter Electrical Characteristics
(T = -20°C to +85°C, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Supply Current
ICC
133
175
mA
Note 3
Power Dissipation
PDISS
IIL
0.45
-2
0.64
W
Note 4
Data Input Current - Low
Data Input Current - High
-350
µA
µA
IIH
18
350
9
Receiver Electrical Characteristics
(T = -20°C to +85°C, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Supply Current
ICC
65
125
mA
W
V
Note 5
Power Dissipation
PDISS
0.25
0.46
-1.62
-0.86
1.3
Note 4
Note 6
Note 6
Note 7
Note 7
Note 6
Note 6
Note 7
Note 7
Data Output Voltage - Low
Data Output Voltage - High
Data Output Rise Time
Data Output Fall Time
VOL - VCC
-1.86
-1.10
0.35
0.35
-1.86
-1.10
0.35
0.35
VOH - VCC
V
tr
ns
ns
V
tf
1.3
Signal Detect Output Voltage - Low
Signal Detect Output Voltage - High
Signal Detect Output Rise Time
Signal Detect Output Fall Time
VOL - VCC
-1.62
-0.86
2.2
VOH - VCC
V
tr
tf
ns
ns
2.2
Transmitter Optical Characteristics
(T = -20°C to +85°C, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Output Optical Power
62.5/125 µm, NA = 0.275 Fiber EOL
BOL
PO
-19.5
-20.5
-16.0
-16.0
-14.0
-14.0
dBm avg.
Note 8
Optical Extinction Ratio
Center Wavelength
8
dB
nm
nm
Note 9
lc
1280
1380
175
Figure 7
Spectral Width - FWHM
Dl
147
1
Note 10
Figure 7
Note 11, 12
Figure 7
Note 11, 12
Figure 7
Optical Rise Time
Optical Fall Time
Total Jitter
tr
1.7
1.7
0.8
ns
ns
ns
tf
1.2
0.2
Tj
Note 13
Receiver Optical Characteristics
(T = -20°C to +85°C, V = 2.97 V to 3.63 V)
C
CC
Parameter
Symbol
Minimum
Typical
Maximum Unit
Reference
Input Optical Power
Minimum at Window Edge
PIN Min. (W)
Pin Min (C)
+1 dB
dBm avg.
Note 14
Figure 8
Input Optical Power
Minimum at Eye Center
PIN Min. (C)
-29
dBm avg.
Note 15
Figure 8
Input Optical Power Maximum
Operating Wavelength
Systematic Jitter
PIN Max.
-14
dBm avg.
nm
Note 14
l
1280
1380
1.0
SJ
0.2
ns
Note 16
Note 17
Note 18
Note 19
Eyewidth
tew
1.4
-44.5
-45
0.5
0
ns
Signal Detect - Asserted
Signal Detect - Deasserted
Signal Detect - Hysteresis
PA
-35.5
-36
dBm avg.
dBm avg.
dB
PD
PA - PD
tA
4.0
Signal Detect Assert Time
(off to on)
500
µs
Note 20
Note 21
Signal Detect Deassert Time
(on to off)
tD
0
500
µs
10
Notes:
1. This is the maximum voltage that can be applied across the Differential
Transmitter Data Inputs to prevent damage to the input ESD protection
circuit.
14. Thisspecificationisintendedtoindicatetheperformanceofthereceiver
sectionofthetransceiverwhenInputOpticalPowersignalcharacteristics
arepresentperthefollowingconditions.TheInputOpticalPowerdynamic
rangefromtheminimumlevel(withawindowtime-width)tothemaximum
2. The outputs are terminated with 50 W connected to V –2 V.
CC
3. The power supply current needed to operate the transmitter is provided
to differential ECL circuitry. This circuitry maintains a nearly constant
current flow from the power supply. Constant current operation helps
to prevent unwanted electrical noise from being generated and
conducted or emitted to neighboring circuitry.
levelistherangeoverwhichthereceiverisguaranteedtoprovideoutput
–12
data with a Bit Error Ratio (BER) better than or equal to 10
.
•
•
•
At the Beginning of Life (BOL).
Over the specified operating temperature and voltage ranges.
Receiver data window time-width is 1.4 ns or greater and centered at
4. The power dissipation value is the power dissipated in the receiver
itself. Power dissipation is calculated as the sum of the products of
supply voltage and currents, minus the sum of the products of the
output voltages and currents.
mid-symbol.
Input signal is 200 MBd, Pseudo Random-Bit-Stream 2 –1 data
pattern.
7
•
•
Transmitter cross-talk effects have been included in Receiver
5. Thisvalueismeasuredwiththeoutputsterminatedinto50Wconnected
sensitivity. Transmitter should be running at 50% duty cycle (nominal)
between 8 - 200 Mb/s, while Receiver sensitivity
is measured.
to V –2 V and an Input Optical Power Level of –14.5 dBm average.
CC
6. This value is measured with respect to V with the output terminated
CC
into 50 W connected to V –2 V.
15. All conditions of note 14 apply except that the measurement is made at
CC
7. The output rise time and fall times are measured between 20% and 80%
the center of the symbol with no window time-width and with a BER
-15
levels with the output connected to V – 2 V through 50 W.
better than or equal to 10
.
CC
8. These optical power values are measured with the following conditions:
16. The receiver systematic jitter specification applies to optical powers
between –14.5 dBm avg. to –27.0 dBm avg. at the receiver. Receiver
Systematic Jitter is equal to the sum of Duty Cycle Distortion (DCD) and
DataDependentJitter(DDJ).DCDisequivalenttoPulse-WidthDistortion
(PWD). Systematic Jitter is measured at the 50% signal level with 200
•
The Beginning of Life (BOL) to the End of Life (EOL) optical power
degradation is assumed to be 1.5 dB per the industry convention for
long wavelength LEDs. The actual degradation observed in normal
commercial environments will be <1.0 dB with Avago Technologies
1300 nm LED products.
7
MBd, PRBS 2 –1 electrical output data pattern.
•
•
Over the specified operating voltage and temperature ranges.
Input Signal: 1010 data pattern, 200 Mb/s NRZ code.
17. Eye-width specified defines the minimum clock time-position range,
centered around the center of the 5 ns baud interval, at which the BER
–12
7
must be 10 or better. Test data pattern is PRBS 2 –1. The typical
change in input optical power to open the eye to 1.4 nsec from a closed
eye is less than 1.0 dB.
200
3.0
180
18. Status Flag switching thresholds:
HFBR-5930 TRANSMITTER
TEST RESULTS
OF λC, ∆λ AND tr/f ARE
1.0
1.5
Direction of decreasing optical power:
If Power >–36.0 dBm avg., then SF = 1 (high)
If Power <–45.0 dBm avg., then SF = 0 (low)
Direction of increasing optical power:
If Power <–45.5 dBm avg., then SF = 0 (low)
If Power >–35.5 dBm avg., then SF = 1 (high)
160
140
120
100
CORRELATED AND
COMPLY WITH THE
ALLOWED SPECTRAL
WIDTH AS A FUNCTION
OF CENTER WAVELENGTH
FOR VARIOUS RISE AND
FALL TIMES.
2.0
tr/f – TRANSMITTER
OUTPUT OPTICAL
RISE/FALL TIMES –
2.5
3.0
ns
19. Status Flag Hysteresis is the difference in low-to-high and high-to-low
switching thresholds. Thresholds must lie within optical power limits
specified. TheHysteresisisdesiredtoavoidStatusFlagchatterwhenthe
optical input is near the threshold.
1260
1280
1300
1320
1340
1360
λ
C – TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES – ns
20. The Status Flag output shall be asserted within 500 µs after a step
increase of the Input Optical Power. The step will be from a low Input
Optical Power <–45.5 dBm avg., to >–35.5 dBm avg.
21. Status Flag output shall be de-asserted within 500 µs after a step
decrease in the Input Optical Power. The Step will be
from a high Input Optical Power >–36.0 dBm avg. to <–45.0 dBm avg.
Figure 7. Transmitter Output Optical Spectral Width (FWHM) vs.
Transmitter Output Optical Center Wavelength and Rise/Fall Times.
9. The Extinction Ratio is a measure of the modulation depth of the optical
signal. The data “0” output optical power is compared to the data “1”
peak output optical and expressed in decibels. With the transmitter
driven by a HALT Line State (12.5 Mhz square-wave) signal, the average
opticalpowerismeasured. Thedata“1”peakpoweristhencalculatedby
adding 3 dB to the measured average optical power. The data “0” output
optical power is found by measuring the optical power when the
transmitter is driven by a logic “0” input. The Extinction Ratio is the ratio
of the optical power at the “0” level compared to the optical power at the
“1” level expressed in decibels.
6
CONDITIONS:
1. T = +25 C
A
5
2. V
= 3.3 V dc
CC
3. INPUT OPTICAL RISE
/FALL TIMES = 1.0/1.2 ns.
4. INPUT OPTICAL POWER
IS NORMALIZED TO
4
3
2
1
0
CENTER OF DATA SYMBOL.
5. NOTE 15 AND 16 APPLY.
10. From an assumed Gaussian-shaped wavelength distribution, the
relationship between FWHM and RMS values for Spectral Width is 2.35
x RMS = FWHM.
11. Inputconditions:100MHz, squarewavesignal, inputvoltagesareinthe
range specified for V and V
IL
IH .
-3
-2
-1
0
1
2
3
12. Measured with electrical input signal rise and fall time of 0.35 to 1.3 ns
(20-80%) at the transmitter input pins. Optical output rise and fall times
are measured between 20% and 80% levels.
EYE SAMPLING TIME POSITION (ns)
Figure 8. Relative Input Optical Power vs. Eye Sampling Time Position.
13. TransmitterSystematicJitterisequaltothesumofDutyCycleDistortion
(DCD) and Data Dependent Jitter (DDJ). DCD is equivalent to Pulse-
WidthDistortion(PWD). SystematicJitterismeasuredatthe50%signal
7
level with 200 MBd, PRBS 2 –1 electrical input data pattern.
11
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
5989-4732EN - February 1, 2006
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