HFBR-707X2DEM [AVAGO]
10 Gb Ethernet, 1310 nm, 10GBASE-LRM, X2 Transceiver; 10 Gb以太网， 1310纳米， 10GBASE- LRM ， X2收发器
| 型号： | HFBR-707X2DEM |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 10 Gb Ethernet, 1310 nm, 10GBASE-LRM, X2 Transceiver |
| 文件： | 总28页 (文件大小：602K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFBR-707X2DEM
10 Gb Ethernet, 1310 nm, 10GBASE-LRM, X2 Transceiver
Data Sheet
Description
Features
• Compliant with IEEE LRM Standard
The X2 LRM fiber optic transceiver is an“intelligent”optical
module which incorporates the complete physical layer
functionality of 10GbE on multi mode fiber with data rate
of 10.3Gbps. The X2 LRM module includes a transmitter
that incorporates an uncooled, directly modulated 1.3 µm
Fabry-Perot laser. The receiver subassembly includes a PIN
photodiode and a linear/AGC trans-impedance amplifier.
To cope with the effect of modal dispersion of multi mode
fibers at 10 Gbps over the distances specified in the IEEE
TM
- Draft P802.3aq /D4.0 for Type 10GBASE-LRM
• Compliant with X2 MSA Issue 2.0b
• Standard SC Duplex fiber optic connector
• Standard 70 pin electrical connector
• Four wide XAUI Electrical interface
• MDIO Management Interface
• Front Panel hot pluggable
802.3aq LRM standard, an electronic dispersion compensa- • Digital Optical Monitoring (DOM) provides Tx/Rx power,
tion circuit is used. The MUX/DEMUX, XAUI interface and
MDIO management functions are all integrated into the
module, as is a precision oscillator. The module is compli-
ant to the X2 Multi Source Agreement specifications.
laser bias current, and module temperature
Specifications
• 220m reach on OM1, 0M2 and OM3 Multimode Fiber
Cables
Applications
• Total Power Dissipation less than 4W
• Ethernet switching systems
• Ethernet peripheral interface
• Computer system I/O
General Specifications
Optics
PIN
TIA
Rx
Tx
EDC
ROSA
802.3ae
SerDes
Optics
Laser
LD
I2C MDIO
TOSA
System
Control
Micro
Other Signals
Figure 1. High level block diagram
General Optical Specifications
General Electrical Specifications
Environmental Specifications
Optical Connector:
SC Duplex
Connector:
70-pin, mates to Tyco/AMP Part No.
1367337-1 or equivalent
Operating temperature:
0 °C to +70 °C case
Optical Line rate:
Power consumption:
10.3125 Gb/s
Supply Voltages:
+5 V, +3.3 V and APS
4.0 W maximum
Link Length:
220m, with 62.5um MMF/
160/500MHz*km
E->O Coding (Transmit Direction):
8B/10B coding removed, 64B/66B
added
220m, with 50um MMF/
500/500MHz*km
O->E Coding (Receive Direction):
64B/66B removed, 8B/10B coding
added
220m, with 50um MMF/
1500/500MHz*km
XAUI interface:
Laser:
1310nm FP Laser
100 W Differential, AC- coupled
I/O on Tx and Rx, per IEEE 802.3ae
Clause 47
Detector:
PIN diode
Control interface:
MDIO, 1.2 V, per IEEE 802.3ae Clause
45.3
Non Volatile memory:
48 byte user space
2
Technical Specifications
1
Absolute Maximum Ratings
Parameter
Minimum
Typical
Maximum
Units
°C
°C
V
Notes
Storage Temperature
Operating Temperature
Supply Voltage (5 V)
Supply Voltage (3.3 V)
Supply Voltage (APS)
Voltage on any XAUI pin
Voltage on any LVCMOS pin
Received Average Power
-40
0
85
70
Case temperature
5.5
3.6
2.0
2.5
4.0
1.5
V
V
V
-0.7
V
dBm
2
Recommended Operating Conditions
Parameter
Minimum
Typical
0.5
Maximum
5
Units
sec
V
Notes
Initialization Time
Supply Voltage (5 V)
Supply Voltage (3.3 V)
4.75
3.14
5
5.25
3.47
3.3
V
Supply Voltage (APS)
Supply Current (5 V)
Supply Current (3.3 V)
Supply Current (APS)
V
3
1
3.0
0.9
0.8
mA
A
0.74
0.66
A
Power Consumption
Supply Current Ramp Rate
Inrush current (per power supply)
Notes:
4
W
50
mA/ms
A
4
150% steady state rating
1. Absolute maximum ratings are those values beyond which functional performance is not intended, device reliability is not implied, and damage
to the device may occur.
2. Typical operating conditions are those values for which functional performance and device reliability is implied.
3. X2 MSA compliant.
4. Not applicable to inrush current due to small transceiver capacitive load presented to the host during hot plug which limits the total in rush
charge.
3
Transmitter Path Summary
Receiver Path Summary
Figure 2 shows a block diagram of the transmit path, from
Figure 3 shows a block diagram of the receiver path, from
the four XAUI differential inputs to the optical output. The the incoming 10.3 Gb/s, 64B/66B encoded optical interface
incoming XAUI differential 8B/10B encoded electrical in- to the four 3.125 Gb/s differential 8B/10B encoded XAUI
puts, are reformatted and transmitted onto the outgoing
fiber optic interface using 64B/66B encoding.
electrical output interface. The XAUI output drivers pro-
vide low-swing differential output with 100 W differential
output impedance and are ac coupled.
Tx
XTAL
PLL
64B/66B 1:0 Block sync
XAUI
LANE 0
CDR
Tx
Opto
PLL
XAUI LANE 1
XAUI LANE 2
XAUI LANE 3
Figure 2. Transmit Path High Level Overview
XAUI LANE 0
Driver
Rx
Opto
XAUI LANE 1
EDC
XTAL
PLL
XAUI LANE 2
XAUI LANE 3
Clock for Rx 10G path
Figure 3. Receive Path High Level Overview
4
Optical Specifications
Parameter
Transmitter
Minimum
Typical
Maximum Units
Notes
Signaling Speed - nominal
GBd
10.3125
Signaling Speed variation from nominal
Center Wavelength
ppm
-100
1260
+100
nm
1355
RMS Spectral Width at 1260 nm
nm
1
2.4
RMS Spectral Width between 1260 nm and 1300
nm
1, See Figure 4a
RMS Spectral Width between 1300 nm and 1355
nm
nm
1
4
Launch Power (OMA)
dBm
2, See Figure 4b
2, See Figure 4b
-4.5
-6.5
1.5
Average Launch Power
dBm
0.5
Average Launch Power of OFF transmitter
Extinction Ratio
dBm
-30
dB
3.5
Peak Launch Power
dBm
2, 3
3
RIN20OMA
dB/Hz
-128
Eye Mask parameters {X1, X2, X3, Y1, Y2, Y3}
See Figure 4c
{0.25, 0.40, 0.45, 0.25, 0.28, 0.80}
4.7
Transmitter Waveform and Dispersion Penalty
(TWDP)
dB
Uncorrelated Jitter (rms)
UI
%
0.033
Encircled Flux within 5µm radius
4
4
30
81
20
Encircled Flux within 11µm radius
Optical Return Loss Tolerance
Receiver
%
dB
Signaling Speed - nominal
GBd
10.3125
Signaling Speed variation from nominal
Center Wavelength
ppm
nm
-100
1260
+100
1355
-6.5
-6
Stressed Sensitivity (OMA)
dBm
dBm
dBm
5
6
Stressed Sensitivity (OMA) for symmetrical test
Overload (OMA)
1.5
Receiver Reflectance
dB
-12
-7
Signal Detect On (OMA)
dBm
7
Notes:
1. RMS spectral width is the standard deviations of the spectrum.
2. The OMA, average launch power and peak launch power specifications apply at TP2. This is after each type of patch cord. For information: Patch
cord losses, between MDI and TP2, differ. The range of losses must be accounted for to ensure compliance to TP2.
3. Peak optical power can be determined as the maximum value from the waveform capture from the TWDP test, or equivalent method.
4. This encircled flux specification, measured per IEC 61280-1-4, defines the near field light distribution at TP2 when the MDI is coupled directly into
the appropriate patch cord.
TM
5. This value will be met for several different independent test conditions defined in Section 68 of the IEEE 802.3aq /D4.0: 1. Comprehensive stressed
receiver test (two separate conditions; Pre-Cursor and Post-Cursor tap weights); 2. Simple stressed receiver test; 3. Jitter tolerance (two separate
frequency/p-p amplitude conditions)
TM
6. This value will be met for test conditions defined in Section 68 of the IEEE 802.3aq /D4.0 for comprehensive stressed receiver test symmetrical
tap weights.
7. With ER ≤ 10dB.
5
4
3
2
1
0
1+Y3
1
1–Y1
1–Y2
Maximum allowed
rms spectral width
0.5
Y2
Y1
1300
1320
1340
1360
1260
1280
Wavelength (nm)
0
Figure 4a. 10GBASE-LRM Transmitter spectral limits
–Y3
X1
X3 1–X3 1–X2 1-X1
1
0
X2
Normalized Time (Unit Interval)
Note: where X1, X2, X3, Y1, Y2, Y3 = 0.25, 0.40, 0.45,
0.25, 0.28, 0.80 respectively
Figure 4c. Transmitter Eye Mask Definition
1
Maximum: 0.5 dBm
Extinction ratio, minimum
(3.5 dB)
0
-1
-2
-3
Extinction ration of 10 dB
(example)
-4
Extinction ratio
infinite
-5
-6
Minimum: -6.5 dBm
-7
-8
-5
-4
-3
-2
-1
0
1
2
Launch power in OMA (dBm)
Minimum:
-4.5 dBm
Maximum
1.5 dBm
Figure 4b. Graphical representation of approximate region of transmitter compliance
6
Electrical Control and Sense I/O Parameters
Table 1. CMOS DC Parameters (MDC, PRTAD<4:0>, LASI)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Vol
Output low voltage
0.15
V
ext. Rpullup = 10 kW to 1.2 V
Voh
Vih
Output high voltage
Input high voltage
Input low voltage
Input pad pulldown current
Rise time
1.0
1.5
V
ext. Rpullup = 10 kW to 1.2V
0.84
1.25
0.36
120
30
V
Vil
V
Ipd
Trise
Tfall
20
40
25
µA
ns
ns
Vin = 1.2 V
Cload = 300 pF
Cload = 300 pF
Fall time
50
Electrical MDIO Parameters
Table 2. MDIO 1.2 V dc parameters
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Vol
Iol
Output high voltage
Output low voltage
Output low current
Input high voltage
Input low voltage
Input capacitance
1.0
1.5
0.2
V
Ioh = -100 uA
Iol = +100 uA
Vin = 0.3
-0.3
-4
V
mA
V
Vih
Vil
0.84
-0.3
1.5
0.36
10
V
Cin
pF
Table 3. MDIO AC Parameters
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Thold
MDIO data hold time
10
ns
Tsetup
Tdelay
MDIO data setup time
10
0
ns
ns
Delay from MDC rising edge to
MDIO data change
300
2.5
Fmax
Maximum MDC clock rate
MHz
7
Electrical High Speed I/O Parameters
Table 4. XAUI Input Interface
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
BAUD rate for 10Gb E
3.125
Gb/s
BAUD rate tolerance
-100
200
100
2500
-10
ppm
mVpp
dB
Differential input amplitude
Differential return loss
Note 1
100 MHz to 2.5 GHz ref to
100W impedance
Common mode return loss
Input Differential Skew
-6
dB
100 MHz to 2.5 GHz ref to 25W
at crossing point, Note 2
75
ps P-P
UIpp
Jitter amplitude tolerancedeter-
ministic + random jitter +Sj jitter
0.55 + Sj
See Figure 5a for SJ jitter graph
Table 5. XAUI Driver Characteristics
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
BAUD rate for 10Gb E
3.125
Gb/s
BAUD rate variation
-100
800
60
100
ppm
mVpp
ps
Differential amplitude
Transition times (20-80%)
Total output jitter
1600
130
90
Note 2
0.175
0.085
15
UI
no pre-equalization
no pre-equalization
at crossing point
Output deterministic jitter
Output differential skew
Differential output return loss
UI
ps
dB
312.5 MHz to 625 MHz: -10
dB625 MHz to 3.125 GHz: as
per equation 47-1 IEEE 802.3ae
Electrical eye mask
See Figure 5b
Note:
1. Maximum amplitude of 2500 mVpp is the combined effect of the driver maximum output signal of 1600 mVpp and the receiver input impedance
mismatch.
2. For information only.
Figure 5a. Single-tone sinusoidal jitter mask
8
Electrical Eye Mask
800
400
0
-400
-800
0
X1 = 0.175
1-X1 = 0.825
1
X2 = 0.390 1-X2 = 0.610
TIME IN UI
Figure 5b. XAUI Driver Near End Template
General Connector Considerations
1. Ground connections are common for Tx and Rx.
2. V contacts are each rated at 0.5 A nominal.
CC
3. See Figure 6 for location of Pin 1.
Table 6. DOM Accuracy
Parameter
Accuracy Specification (typ)
1.5 dBm
Accuracy Specification (max)
Rx Power Range
Output Power Range
Temperature Range
Ibias Range
2 dBm
3 dBm
5 °C
2 dBm
3 °C (-5 °C to +75 °C)
5% (2 mA to 80 mA)
10%
9
EEPROM and NVR Content
X2 Module contains Non-Volatile (NVR) and Volatile memory in accordance with the Xenpak MSA rev 3.0, the IEEE 802.3ae
Standard and applicable end-user specifications.
Table 7. Customer specific NVR Content – Device 1 PMA/PMD Registers: 0x8012 – 0x805C
Data Address
(Hex)
Field Size
(Bytes)
Name of Field
Value (Hex)
Remark
0x8012
0x8013
0x8014
0x8015
0x8017
0x8018
0x8022
0x8024
0x8026
0x803A
1
Tcvr Type
02
Transceiver Type (X2=02)
1
Connector
Encoding
Bit Rate
01
Optical Connector Type (SC=01)
Bit Encoding (NRZ=01)
Bit rate: in multiples of 1 MB/s
Protocol Type (10GbE=01)
“Unspecified”: 10GbE code 0
“220m for MMF”
1
01
2
28 48
01
1
Protocol
1
Compliance
Range
00
2
00 16
01
1
Fiber Type
Wavelength
Vendor Name
“MM, generic”
3
01 FF B8
Center Wavelength : 1310nm
AVAGO
16
41 56 41 47 4F 20 20 2020 20 20
20 20 20 20 20
0x804A
0x805C
16
16
Vendor PN
Vendor SN
48 46 42 52 2D 37 30 3758 32 44
45 4D 20 20 20
HFBR-707X2DEM
AGAyywwXnnn 20 20 20 20 20
yy: year; ww: work week;
nnn:rolling serial number from 000 to ZZZ
10
Table 8. General I/O Pin Summary
Signal Type
Power Supply Pins
Ground
Pins
Direction
Function
1:3, 33:37, 40, 43, 46, 49 52:54,
57, 60, 63, 66, 69:70
Electrical ground
3.3 V
5:6, 30:31
4, 32
I
I
I
I
I
3.3 V power supply
5.0 V
5.0 V power supply
Adaptive power supply
Adaptive power supply set
Adaptive power supply sense
Control & Sense I/O Pins
LASI
7:8, 28:29
25
Adaptive power supply (0.9 - 1.8 V)
APS set connection
27
APS sense connection
9
O
I
1.2 V CMOS pull up on host
1.2 V CMOS pull up on module
1.2 V CMOS pull up on module
1.2 V CMOS pull up on module
Reset
10
Transmitter ON/OFF
Port address 4:0
MDIO Pins
12
I
19:23
I
MOD DETECT
14
17
18
O
I/O
I
1 kW pull down to ground on module
1.2 V per IEEE802.3ae clause 45.3
1.2 V per IEEE802.3ae clause 45.3
Management data IO
Management data clock
High Speed I/O Pins
Receiver lane 0:3 +
Receiver lane 0:3 -
Transmitter lane 0:3 +
41, 44, 47, 50
42, 45, 48, 51
55, 58, 61, 64
O
O
I
XAUI per IEEE802.3ae clause 47
XAUI per IEEE802.3ae clause 47
XAUI per IEEE802.3ae clause 47
Transmitter lane 0:3 -
Non connected pins
Not connected
56, 59, 62, 65
I
XAUI per IEEE802.3ae clause 47
NC on module
13, 26, 38:39, 67:68
Do not connect pins
Do not connect
11, 15:16, 24
Avago Specific
11
Electrical Pin Out
Top of PCB
Bottom of PCB
(as viewed from top of PCB)
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
GND
GND
GND
1
2
GND
NOT CONNECTED
NOT CONNECTED
GND
GND
3
5.0V
4
3.3V
5
TX LANE3-
TX LANE3+
GND
3.3V
6
APS
7
APS
8
TX LANE2-
TX LANE2+
GND
LASI
9
10
RESET
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DO NOT CONNECT
TX ON/OFF
TX LANE1-
TX LANE1+
GND
NOT CONNECTED
MOD DETECT
DO NOT CONNECT
DO NOT CONNECT
MDIO
TX LANE0-
TX LANE0+
GND
GND
MDC
GND
PRTAD4
RX LANE3-
RX LANE3+
GND
PRTAD3
PRTAD2
49
48
47
46
45
44
43
42
41
40
39
38
37
36
PRTAD1
RX LANE2-
RX LANE2+
GND
PRTAD0
DO NOT CONNECT
APS SET
NOT CONNECTED
APS SENSE
APS
RX LANE1-
RX LANE1+
GND
RX LANE0-
RX LANE0+
GND
APS
3.3V
3.3V
NOT CONNECTED
NOT CONNECTED
GND
5.0V
GND
GND
GND
GND
Figure 6. Electrical Pin Out
12
Electrical Pin Out Definitions
Table 9. Pin Function Definitions (Lower Row)
Pin No
Name
Direction
Function
Note
1
GND
Electrical ground
2
GND
Electrical ground
3
GND
Electrical ground
4
5 V
I
5.0 V power supply
5
3.3 V
I
3.3 V power supply
6
3.3 V
I
3.3 V power supply
7
APS
I
Adaptive power supply (0.9 - 1.8 V)
Adaptive power supply (0.9 - 1.8 V)
Logic high: normal operationLogic low: LASI asserted
Logic high: normal operationLogic low: reset
Avago specific; do not connect
8
APS
I
9
LASI
O
I
See Table 13
10
11
12
RESET
DO NOT CONNECT
TX ON/OFF
I
Pulled up inside module via 10 kW Logic high: transmitter
onLogic low: transmitter off
13
NOT CONNECTED
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
MOD DETECT
DO NOT CONNECT
DO NOT CONNECT
MDIO
O
Pulled low inside module through 1 kW to GND
Avago specific; do not connect
Avago specific; do not connect
Management data IO
I/O
MDC
I
I
I
I
I
I
Management data clock
Port address bit 4
PRTAD4
PRTAD3
PRTAD2
PRTAD1
PRTAD0
DO NOT CONNECT
APS SET
NOT CONNECTED
APS SENSE
APS
Port address bit 3
Port address bit 2
Port address bit 1
Port address bit 0
Avago specific; do not connect
APS set connection
I
I
I
I
I
I
I
APS sense connection
Adaptive Power Supply (0.9 - 1.8 V)
Adaptive Power Supply (0.9 - 1.8 V)
Power
APS
3.3 V
3.3 V
Power
5 V
5.0 V Power Supply
Electrical Ground
GND
GND
Electrical Ground
GND
Electrical Ground
13
Table 10. Pin Function Definitions (Upper Row)
Pin No
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Name
GND
Direction
Function
Electrical Ground
Note
GND
Electrical Ground
NOT CONNECTED
NOT CONNECTED
GND
Electrical Ground
RX LANE 0+
RX LANE 0-
GND
O
O
Module XAUI Output Lane 0+
Module XAUI Output Lane 0-
Electrical Ground
RX LANE 1+
RX LANE 1-
GND
O
O
Module XAUI Output Lane 1+
Module XAUI Output Lane 1-
Electrical Ground
RX LANE 2+
RX LANE 2-
GND
O
O
Module XAUI Output Lane 2+
Module XAUI Output Lane 2-
Electrical Ground
RX LANE 3+
RX LANE 3-
GND
O
O
Module XAUI Output Lane 3+
Module XAUI Output Lane 3-
Electrical Ground
GND
Electrical Ground
GND
Electrical Ground
TX LANE 0+
TX LANE 0-
GND
I
I
Module XAUI Input Lane 0+
Module XAUI Input Lane 0-
Electrical Ground
TX LANE 1+
TX LANE 1-
GND
I
I
Module XAUI Input Lane 1+
Module XAUI Input Lane 1-
Electrical Ground
TX LANE 2+
TX LANE 2-
GND
I
I
Module XAUI Input Lane 2+
Module XAUI Input Lane 2-
Electrical Ground
TX LANE3+
TX LANE3-
GND
I
I
Module XAUI Input Lane 3+
Module XAUI Input Lane 3-
Electrical Ground
NOT CONNECTED
NOT CONNECTED
GND
Electrical Ground
Electrical Ground
GND
14
Figure 7. Mechanical Dimensions
Notes
1. All module and PCB pad dimensions are per X2 MSA Revision 2.0b unless otherwise noted in Figure 7.
15
Management Data Input/Output (MDIO) Interface
MDIO Timing relationship to MDC
The MDIO interface provides a simple, two wire, serial in-
terface to connect a station management entity (STA) and
a managed PHY for the purpose of controlling the PHY and
gathering status from the PHY. The management interface
consists of the two wire physical interface, a frame format,
a protocol specification for exchanging the frames and
a register set that can be read and written using these
frames. The two wires of the physical interface are the
Management Data Clock (MDC) and the Management
Data I/O (MDIO).
MDIO is a bidirectional signal that can be sourced by the
STA or the HFBR-707X2DEM. When the STA sources the
MDIO signal, the STA shall provide a minimum of 10 ns
of setup time and a minimum of 10 ns of hold time ref-
erenced to the rising edge of MDC (see Figure 8). When
the MDIO signal is sourced by the HFBR-707X2DEM, it is
sampled by the STA synchronously with respect to the
rising edge of MDC. The clock output delay from the HFBR-
707X2DEM shall be a minimum of 0 ns and a maximum of
300 ns.
Management Data Clock (MDC)
Management Frame Format
The MDC is sourced by the Station Management entity
(STA) to the PHY as the timing reference for transfer of in-
formation on the MDIO signal. MDC is an aperiodic signal
that has no maximum high or low times.
The HFBR-707X2DEM has an internal address register
which is used to store the address for MDIO reads and
writes. This MDIO address register can be set by using an
address frame that specifies the register address to be ac-
cessed within a particular port device.
Management Data I/O (MDIO)
The following write, read or a post-read-increment-address
frame to the same port device shall access the register
whose address is stored in the HFBR-707X2DEM MDIO
address register. An address frame should be followed im-
mediately by its associated write, read or post-read-incre-
ment-address frame.
MDIO is a bidirectional signal between the PHY (HFBR-
707X2DEM) and the STA. It is used to transfer control and
status information. Data is always driven and sampled
synchronously with respect to MDC. Figure 9 shows that
MDIO open drain driver configuration.
Upon receiving a post-read-increment-address frame
and having completed the read operation, the HFBR-
707X2DEM shall increment and store the address of the
register accessed. If no address cycle is received before
the next write, read or post-read-increment-address frame,
then the HFBR-707X2DEM shall use the stored address for
that register access.
MDC
tsu=10 ns min
MDIO
(STA Sourced)
Data Valid
thd=10 ns min
The Management Frame Format for Indirect Access is
specified in Table 11.
MDC
PRE - Preamble
MDIO
Data Valid
(HFBR-707X2DEM Sourced)
At the beginning of each transaction the STA shall send
a preamble sequence of 32 contiguous logic one bits on
MDIO with 32 corresponding cycles on MDC, to provide
the HFBR-707X2DEM with a pattern that it can use to
establish synchronization. The HFBR-707X2DEM must
observe this preamble sequence before it responds to any
transaction.
tpd=0 ns min, 300 ns max
Figure 8. MDIO/MDC Timing
16
1.2 V
pullup,
R=10 kΩ
receive buffer
external
capacitance loading
C< 700 pF
MDIO pin
Open drain
driver
COREGND
Figure 9. MDIO open Drain Driver Configuration
Table 11. Frame Format
Management Frame Fields
FRAME
ADDRESS
WRITE
PRE
1...1
1...1
1...1
1...1
ST
00
00
00
00
OP
00
01
11
10
PRTAD
DEVAD
DA[4:0]
DA[4:0]
DA[4:0]
DA[4:0]
TA
10
10
Z0
Z0
ADDR/DATA
A[15:0]
IDLE
PRTAD[4:0]
PRTAD[4:0]
PRTAD[4:0]
PRTAD[4:0]
Z
Z
Z
Z
D[15:0]
READ
D[15:0]
READ INC
D[15:0]
ST - Start
PRTAD - Port Address
The Start of Frame is indicated by a <00> pattern. This pat-
tern ensures transitions from the default logic one line to
zero and back to one.
The Port Address is five bits, allowing 32 unique port ad-
dresses. HFBR-707X2DEM’s port address is set through pins
PRTAD<0:4>.
OP - Operation Code
DEVAD - Device Address
The operation code field indicates the type of transaction
being performed by the frame.
The Device Address is five bits, allowing 32 unique devices
per port. The HFBR-707X2DEM supports device addresses
1 (PMA/PMD), 3 (PCS) and 4 (PHY XS).
Table 12. OP Code Definitions
TA - Turnaround
OP Code
Operation
The Turnaround time is a two bit time spacing between the
Register Address field and the Data field of a management
frame to avoid contention during a read transaction (see
IEEE 802.3ae).
00
01
11
10
Register Address
Write Data
Read Data
ADDR/DATA
Post Read Increment Address
The Data/Address field is 16 bits. The first bit transmitted/
received is bit 15 and the last bit is bit 0.
IDLE
The idle condition is a high-impedance state. The MDIO
line will be pulled to a one.
17
EEPROM Interface
Volatile and Non-Volatile Registers
There are two main memory/register types in the HFBR-
707X2DEM which comply with the IEEE 802.3ae and XEN-
PAK standard: volatile and nonvolatile. These areas can be
further divided into user readable and writeable areas.
must be written first to the user accessible nonvolatile
area and then a reload invoked via the NVR Control/Status
register, see Register 1.32768.
Access
At power up the module register space is initialized and,
where appropriate, default values are loaded from the non
user accessible nonvolatile memory. The user accessible
nonvolatile memory is also uploaded entirely into the user
accessible volatile memory.
The XENPAK MSA related Nonvolatile Control/Status regis-
ter is only needed for performing writes to the nonvolatile
user accessible area within the HFBR-707X2DEM because
nonvolatile memory cannot be written to by normal MDIO
write cycles. Other writes to volatile memory and registers
may be performed directly via normal MDIO write cycles.
All volatile and nonvolatile locations may be read directly
via MDIO read cycles, it is not necessary to use the NVR
Control/Status register, other than for status.
It is important to note that writes to the user accessible
volatile memory are not stored to the corresponding user
nonvolatile area and will therefore be lost upon a power
down or reset. For such writes to be permanent the data
DEVICE MANAGEMENT INTERFACE - ADDRESS FRAME STRUCTURE
MDC
MDIO Write
0
0
0
0
A4 A3 A0 R4 R3 R0
1
0
A15 A14 A1 A0
32 "1"s
Idle Preamble
ST
Op Code
PHY Address
Register Address Turn Around
Write
Address
Idle
Idle
Idle
Idle
DEVICE MANAGEMENT INTERFACE - WRITE FRAME STRUCTURE
MDC
MDIO Write
0
0
0
1
A4 A3 A0 R4 R3 R0
1
0
D15 D14 D1 D0
32 "1"s
Idle Preamble
ST
Op Code
PHY Address
Register Address Turn Around
Write
Data
DEVICE MANAGEMENT INTERFACE - READ INCREMENT FRAME STRUCTURE
MDC
MDIO READ
INCREMENT
0
0
1
0
A4 A3 A0 R4 R3 R0
0
D15 D14
D1 D0
32 "1"s
Z
Idle Preamble
ST
Op Code
PHY Address
Write
Register Address
Turn Around
Data
Read
DEVICE MANAGEMENT INTERFACE - READ FRAME STRUCTURE
MDC
MDIO READ
0
0
1
1
A4 A3 A0 R4 R3 R0
0
D15 D14
D1 D0
32 "1"s
Z
Idle Preamble
ST
Op Code
PHY Address
Write
Register Address
Turn Around
Data
Read
Figure 10. MDIO Frame Formats
18
EEPROM Single Byte Read or Write Cycle
Read/Write Command (bit5)
An EEPROM Single Byte Read/Write Cycle is initiated by
setting MDIO EEPROM control register bits 1.32768.1:0 to
10. As for the 256 byte read/write commands, MDIO reg-
ister 1.32768.5 determines if a read or a write cycle will be
performed. The single byte EEPROM address is read from
EEPROM control register 1.32768 bit15:8. The data is placed
in/read from the associated MDIO register.
The XENPAK MSA related 1.32768.5 register must be set to
1 to perform writes to the NVR and zero (read) otherwise
a zero written to bit 5 initiates an NVR read. A 1 written to
bit 5 initiates an NVR write.
If the NVR register bit 5 is set to zero and the extended
command bits set to 11 forces an upload of all values in
the NVR to the volatile areas, including default register
values. Such an upload is performed automatically after a
hard or soft reset.
Monitors and Diagnostic Features
The LASI pin is used to indicate suboptimal performance
in either the receive or transmit path. It can be used as an
interrupt. It is the OR of the tx_alarm, rx_alarm and the
ls_alarm signals each gated with their respective enables.
The enables are read from MDIO register 1.36866, LASI
control.
EEPROM Checksum Checking
The HFBR-707X2DEM will perform a checksum calcula-
tion and compare after every successful 256 byte read.
The checksum for comparison is in EEPROM register 118
=MDIO register 1.32893.7:0. The checksum is equal to the 8
LSB‘s of the sum of bytes 0 to 117 of the EEPROM. The cal-
culated checksum is stored in MDIO register 1.49156.15:8.
The result of the calculated checksum compared with
the one read from EEPROM is placed in MDIO register
1.49155.7.
LASI ={OR of (reg 1.36869.n ‘bit wise AND ‘ reg 1.36866.n)
for n=0 to 15}.
ls_alarm
LS Alarm is latched high each time the link_status signal
changes state. LS_ALARM is the output of this latch AND
the LS_ALARM enable register. link_status is an indicator
of the link health.
EEPROM 256 Byte Read Cycle
An EEPROM 256 Byte Read Cycle is initiated by setting
MDIO bits 1.32768.0,1 to 0 and 1.32768.5 to 0.
link_status = {PMD signal detect (MDIO 1.10.0)
A N D P C S b l o c k _ l o c k ( M D I O 3 . 3 2 . 0 ) A N D
PHY_XS lane_alignment (MDIO 4.24.12)}
The information to be read from the EEPROM stored in
the 256 MDIO registers. A 256 byte read is initiated on hot
plug or reset.
Table 13. LASI Control Registers
MDIO Status
MDIO Enable
Description
Registers (RO)
1.36869.5
1.36869.4
1.36869.3
1.36869.2
1.36869.1
1.36869.0
Type
RO
Registers (R/W)
1.36866.5
1.36866.4
1.36866.3
1.36866.2
1.36866.1
1.36866.0
Default
3.3V supply out of range
APS supply out of range
Reserved
0
0
X
0
0
0
RO
-
RX_ALARM
RO
TX_ALARM
RO
LS_ALARM
RO/LH
19
Rx_alarm
tx_alarm
rx_alarm is used to indicate a problem with the receive
path. rx_alarm is the OR of several receive path status reg-
isters in MDIO registers 1.36867.
tx_alarm is used to indicate a problem with the transmit
path. tx_alarm is the OR of several transmit path status
registers in MDIO registers 1.36868 bit wise AND’d with
the TX_ALARM enable register. The ORing of each term is
enabled by a companion MDIO register in 1.36865.
The ORing of each term is enabled by a companion MDIO
register in 1.36864 and the overall output is enabled by the
RX_ALARM enable register (1.36866.2h).
tx_alarm = {OR of (reg 1.36868 ‘bit wise AND’reg 1.36865)
for n=0 to 15} AND {TX_ALARM enable (reg 1.36866.1)}
rx_alarm ={OR of (reg 1.36867‘bit wise AND‘ reg 1.36864..
n) for n=0 to 15} AND {RX_ALARM enable (1.36866.2h})
Table 14. Receive Alarm Registers
MDIO Status
Registers (RO)
MDIO Enable
Description
WIS local fault
Reserved
Mirrors
Type
RO
Registers (R/W)
1.36864.9
1.36864.6-8
1.36864.5
1.36864.4
1.36864.3
1.36864.2
1.36864.1
1.36864.0
Default
1.36867.9
0
X
1
1
1
X
0
1
1.36867.6-8
-
Receive Optical Power fault 1.36867.5
RO/LH1
RO/LH
RO/LH
-
PMA/PMD fault
PCS fault
1.36867.4
1.36867.3
1.36867.2
1.36867.1
1.36867.0
1.8.10
3.8.10
Reserved
RX_FLAG
RO
PHY XS fault
4.8.10
RO/LH
1. This bit will be read only if bit 9 of the Optional Settings Register at 1.49175 is set to 1, and RO/LH if it is set to 0.
Table 15. Transmit Alarm Registers
MDIO Status
Registers (RO)
MDIO Enable
Registers (R/W)
Description
Mirrors
Type
Default
Laser Bias Current fault
1.36868.9
1.36868.8
1.36868.7
1.36868.6
1.36868.5
1.36868.4
1.36868.3
1.36868.2
1.36868.1
1.36868.0
RO
1.36865.9
1.36865.8
1.36865.7
1.36865.6
1.36865.5
1.36865.4
1.36865.3
1.36865.2
1.36865.1
1.36865.0
1
Laser Temp fault
Laser Output Power fault
Transmit fault
Reserved
RO
1
1
0
X
1
1
X
0
1
RO
RO/LH
-
PMA/PMD fault
PCS fault
1.8.11
3.8.11
RO/LH
RO/LH
-
Reserved
TX_FLAG
RO
PHY XS fault
4.8.11
RO/LH
20
Loopbacks
Reset Operation
When in any system (PMA, PCS or PHY XS system) loopback
mode the HFBR-707X2DEM shall accept data from the
transmit path and return it on the receive path.
Writing a‘1’to any of MDIO registers 1.0.15, 3.0.15 or 4.0.15
causes all the HFBR-707X2DEM registers to be reset to their
default values. These bits are all self-clearing after the reset
function is complete.
During PMA or PHY XS system loopback, a continuous
stream of zeros is propagated through the remaining
transmit data path. In PCS loopback mode, a continuous
pattern of 0x00FF is propagated through the remaining
transmit data path. Transmit data will be propagated
through the remaining transmit data path instead if the
associated‘loopback data output enable bit’is set high for
the enabled loopback mode.
Pulling the RESET pin low causes a full chip reset.
Writes to any bits of the Control register while the RESET
is asserted are ignored. All status and control registers
are reset to their default states. The NVR read sequence is
started when RESET goes high. MDIO register bits 1.0.15,
3.0.15, and 4.0.15 will be held to 1 until the reset sequence
is complete.
When in PMA network loopback mode, the recovered and
retimed 10.3125 GBd signal is looped to the transmitter.
The receive path XAUI output data will be received data.
In PHY XS network loopback the recovered received data is
looped back to the transmit path in the XAUI block.
Enabling of more than one loopback path is invalid.
Table 16. Loopback Summary
loopback
control
register
loopback
direction
bypassed path
default output
data output
enable register
bypassed path
output control’ =1
loopback name
PMA system loopback
Tx -> Rx
Tx -> Rx
1.0.0
stream of 0’s
0x00FF
3.49152.5
3.49152.5
4.49152.15
NA
transmit data
transmit data
transmit data
NA
PCS loopback
3.0.14
PHY XS system loopback Tx -> Rx
PMA network loopback Rx -> Tx
4.49152.14
1.49153.4
stream of 0’s
received data
PHY XS network loop-
Rx -> Tx
back
4.0.14
received data
NA
NA
21
Tx
XTAL
PHY XS
System
PMA Network
Loopback
1.49153.4=1
System
Loopback
4.49152.14
PLL
Loopback
1.0.0=1
64B/66B 1:0 Block sync
XAUI
LANE 0
CDR
Tx
Opto
PLL
XAUI LANE 1
XAUI LANE 2
XAUI LANE 3
PHY XS
System
Loopback
4.49152.14=1
XAUI LANE 0
Driver
PHY XS
Network
Loopback
4.0.14=1
Rx
Opto
XAUI LANE 1
XAUI LANE 2
XAUI LANE 3
EDC
XTAL
PLL
PCS
System
Loopback
3.0.14=1
Figure 11. HFBR-707X2DEM Loopback Modes
22
XENPAK Digital Optical Monitoring (DOM) Overview
The XENPAK Digital Optical Monitoring (DOM) interface
is a derivative of SFF-8472: Digital Diagnostic Monitoring
Interface for Optical Transceivers appropriate to XENPAK
transceivers. This specification defines a 256 byte block
of register space that is accessible over the 2 wire serial
MDIO/MDC interface.
and 1.41071: DOM Capability - Extended). The transceiver
generates this monitoring data by digitization of internal
analog signals, which are calibrated to absolute measure-
ments. Measured parameters are reported in 16 bit data
fields (two concatenated bytes).
Alarm flags are required so DOM indicators can be made
inputs to the Link Alarm Status Interrupt (LASI) function.
Calibrated alarm and warning threshold data is written
during device manufacture.
A memory map is used to access measurements of trans-
ceiver temperature, receive optical power, laser output power,
and laser bias current through the 2 wire serial MDIO/MDC
interface. Support for these measurements is indicated
through the capability registers (1.32890 : DOM Capability
Table 17. XENPAK Digital Optical Monitoring MDIO Register Space
From
Decimal
To
Decimal
Device
Hex
Hex
Register Name
1
32890
40960
41056
41070
41216
807A
32890
40999
41065
41071
41216
807A
DOM Capability
1
1
1
1
A000
A060
A06E
A100
A027
A069
A06F
A100
Alarm and Warning Thresholds
Monitored A/D Values
Optional Status and DOM Extended Capabilities
Optional DOM Control/Status
Table 18. Register 1.32890 - DOM Capability
1
Bit(s)
Name
Description
R/W
Default Value
1.32890.7
DOM Register
Implemented
DOM Control/Status Register:
0 = not implemented
1 = implemented
RO
Specified by Customer
1.32890.6
1.32890.5
DOM Imple-
mented
Set when DOM implemented
RO
mirrors 1.32890.7
0
WDM capability
WDM lane by lane DOM capability: setting this RO
bit indicates that registers A0CO-A0FF are valid.
Setting this bit will NOT override indications
placed in register A06F (DOM capability)
1.32890.4
Laser bias scale
Laser bias scale factor:
0 = 2 µA
RO
1
1 = 10µA
1.32890.3
Reserved
RO
RO
X
1.32890.2:0
External DOM
Address of external DOM device
XXX
23
Alarm and Warning Flags
MDIO registers 1.41072 to 1.41079 contain alarm and
warning flags that monitor A/D values in registers 1.41056-
1.41065.
•
Warning flags (registers 1.41076 - 1.41077) associated
with transceiver temperature, receive optical power, la-
ser output power, and laser bias current. Warning flags
indicate conditions outside the normally guaranteed
bounds, but not necessarily causes of immediate link
failures.
Two flag types are defined:
•
Alarm flags (registers 1.41072 - 1.41073) associated
with transceiver temperature, receive optical power,
laser output power, and laser bias current. Alarm flags
indicate conditions likely to be associated with an in-
operational link and cause for immediate action.
Table 19. Registers Alarm and Warning Flag Memory Map
Default Value
(dec)
Bit(s)
Name
Description
Type
RO
1.41072.7
1.41072.6
1.41072.4-5
1.41072.3
1.41072.2
1.41072.1
1.41072.0
1.41073.7
Transceiver Temp High Alarm
Transceiver Temp Low Alarm
Reserved
Set when transceiver temp exceeds high alarm level
0
Set when transceiver temp is below low alarm level
RO
0
Laser Bias Current High Alarm
Laser Bias Current Low Alarm
Laser Output Power High Alarm
Laser Output Power Low Alarm
Receive Optical Power High Alarm
Set when laser bias current exceeds high alarm level
Set when laser bias current is below low alarm level
Set when laser output power exceeds high alarm level
Set when laser output power is below low alarm level
RO
RO
RO
RO
0
0
0
0
0
Set when receive optical power exceeds high alarm level RO
Set when receive optical power is below low warning
level
1.41073.6
Receive Optical Power Low Warning
RO
0
1.41073.0-5
Reserved
Reserved
1.41074-
75.7:1
1.41076.7
1.41076.6
1.41076.4-5
1.41076.3
1.41076.2
1.41076.1
1.41076.0
Transceiver Temp High Warning
Transceiver Temp Low Warning
Reserved
Set when transceiver temp exceeds high warning level
Set when transceiver temp is below low warning level
RO
RO
0
0
Laser Bias Current High Warning
Laser Bias Current Low Warning
Laser Output Power High Warning
Laser Output Power Low Warning
Set when laser bias current exceeds high warning level
Set when laser bias current is below low warning level
RO
RO
0
0
0
0
Set when laser output power exceeds high warning level RO
Set when laser output power is below low warning level RO
Set when receive optical power exceeds high warning
level
1.41077.7
1.41077.6
Receive Optical Power High Warning
Receive Optical Power Low Warning
RO
0
0
Set when receive optical power is below low warning
level
RO
24
Operation
A top-level block diagram of Digital Optical Monitoring
(DOM) incorporated into the Link Alarm Status Interrupt
(LASI) function is shown in Figure 12.
TX Alarm Flags
1.41072
TX_FLAG
to bit 1 of
TX_ALARM
TX Flag Control
1.36870
RX Alarm Flags
1.41073
RX_FLAG
to bit 1 of
RX_ALARM
TX Flag Control
1.36870
Figure 12. DOM/LASI Block Diagram
TX_FLAG Status
TX_FLAG Control
Assertion of TX_FLAG indicates that one or more of the
transmitter operating parameters (transceiver temperature,
laser bias current, or laser output power) exceeds the alarm
levels. Tx alarm flags only monitor A/D values in registers
1.41056-1.41069. TX_FLAG shall be the logic OR of the bits
in register 1.41072. The contents of the TX_FLAG status
register are shown below. Bit 1 of TX_ALARM (TX_FLAG)
will have the properties of latch high, clear on read (note
that if the condition exists following register read, the bit
will not be cleared).
TX_FLAG may be programmed to assert only when specific
transmit operation parameters exceed their alarm levels.
The programming is performed by writing the contents
of a mask register located at offset 1.36870. The contents
of register 1.41072 shall be AND’ed with the contents of
register 1.36870 prior to application of the OR function
that generates the TX_FLAG signal.
Table 20. Register 1.36870: TX_FLAG Control Bits
Bit(s)
Name
Description
Type
RW
RW
RW
RW
RW
RW
RW
Default Value (dec)
1.36870.7
1.36870.6
1.36870.5:4
1.36870.3
1.36870.2
1.36870.1
1.36870.0
Temp high Enable
Temp low enable
Transceiver Temp High Alarm Enable
Transceiver Temp Low Alarm Enable
Reserved
0
0
0
0
0
0
0
Current High enable
Current low enable
LoP high enable
LoP low enable
Laser Bias Current High Alarm Enable
Laser Bias Current Low Alarm Enable
Laser Output Power High Alarm Enable
Laser Output Power Low Alarm Enable
25
RX_FLAG Status
RX_FLAG Control
Assertion of RX_FLAG indicates that one or more of the
receiver operating parameters (receive optical power)
exceeds the alarm levels. Rx alarm flags only monitor A/D
values in registers 1.41056-1.41070. RX_FLAG shall be
the logic OR of the bits in register 1.41073. The contents
of the RX_FLAG status register are shown below. Bit 1 of
RX_ALARM (RX_FLAG) will have the properties of latch
high, clear on read (note that if the condition exists follow-
ing register read, the bit will not be cleared).
RX_FLAG may be programmed to assert only when specific
receive operation parameters exceed their alarm levels.
The programming is performed by writing the contents
of a mask register located at offset 1.36871. The contents
of register 1.41072 shall be AND’ed with the contents of
register 1.36871 prior to application of the OR function
that generates the RX_FLAG signal.
Table 21. Register 1.36871: RX_FLAG Control Bits
Bit(s)
Name
Description
Type
RW
RW
RW
Default Value (dec)
1.36871.7
1.36871.6
1.36871.5:0
Rx power High enable
Rx power low enable
Receive Optical Power High Alarm Enable
Receive Optical Power Low Alarm Enable
Reserved
0
0
0
Regulatory Compliance
Electromagnetic Interference (EMI)
The HFBR-707X2DEM is intended to enable commercial
system designers to develop equipment that complies
with the various regulations governing Certification of In-
formation Technology equipment (see Table 22).
Most equipment design utilizing these high speed trans-
ceivers from Avago Technologies will be required to meet
the requirements of FCC in the United States, CENELEC
EN55022 (CISPR 22) in Europe and VCCI in Japan. Perfor-
mance of the HFBR-707X2DEM transceiver is dependent
upon customer board and chassis design.
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important. The first case is during handling of
the transceiver prior to plugging into the circuit board. It
is important to use normal ESD handling precautions for
ESD sensitive devices. These precautions include using
grounded wrist straps, work benches and floor mats in
ESD controlled areas. The second case to consider is static
charges to the exterior of the equipment chassis contain-
ing the transceiver parts. To the extent that the SC duplex
connector of the transceiver part is exposed outside of
the equipment chassis, the HFBR-707X2DEM transceiver
is designed to withstand types and levels of ESD indicated
in Table 22 to enable equipment compliance to the system
level criteria it is intended to meet.
Immunity
Equipment utilizing these transceivers will be subject to
radio frequency electromagnetic fields in some environ-
ments. These transceivers have been characterized without
the benefit of the normal equipment chassis enclosure and
results are reported below. Performance of a system con-
taining these transceivers within a well-designed chassis
enclosure is expected to be better than the results of these
tests without a chassis enclosure.
Laser Eye Safety
The HFBR-707X2DEM transceiver is a Class 1 laser product,
compliant with IEC 60825-1:2001-8. The output radiation
wavelength is in the 1260-1355 nm range. The maximum
output power radiation of a module affected by a single
fault is 5 mW. Also see table 22.
26
Table 22. Regulatory Compliance
Feature
Test Method
Performance
General
Telcordia GR-468-CORE
MIL STD 883 Method 3015
JEDEC JES D22-C101
IEC 61000-4-2
Qualified in accordance with Remote termi-
nal requirements
Electrostatic Discharge
- Human Body Model
500 V
Electrostatic Discharge
- Charged Device Model
500 V
Electrostatic Discharge
- Contact Discharge
Air Discharge
8000 V15000 V
Electromagnetic
Interference
FCC Class BCENELEC EN55022 Class B
(CISPR 22B) VCCI Class 2
Margins are dependant on customer board
and chassis design
Immunity
Variation of IEC 61000-4-3
Typically show no measurable effect from a
10 V/m field swept from 80 MHz to 10 GHz
applied to the transceiver without a chassis
enclosure.
Laser Eye Safety
US FDA CDRH AEL Class 1
US 21 CFR, Subchapter J, 1040.10
and Laser Notice # 50
CDRH: in progress
TUV: in progress
(IEC) EN60825-1:2001-8
Component Recognition Underwriters Laboratories and Ca-
nadian Standards Association Joint
UL certificate number PENDING
Component Recognition for Informa-
tion Technology Equipment Including
Electrical Business Equipment
27
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies , Limited, in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies, Limited. All rights reserved.
AV02-0197EN - May 22, 2007
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