HMMC-3122-TR1 [AVAGO]
3122 SERIES, PRESCALER, PDSO8, 4.90 X 3.90 MM, 1.55 MM HEIGHT, 1.25 MM PITCH, PLASTIC, MS-012, SOIC-8;
| 型号： | HMMC-3122-TR1 |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 3122 SERIES, PRESCALER, PDSO8, 4.90 X 3.90 MM, 1.55 MM HEIGHT, 1.25 MM PITCH, PLASTIC, MS-012, SOIC-8 时钟 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：596K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HMMC-3122
DC-12 GHz Packaged High Efficiency Divide-by-2 Prescaler
HMMC-3122-TR1 - 7” diameter reel/500 each
HMMC-3122-BLK - Bubble strip/10 each
Data Sheet
Description
Features
• Wide Frequency Range: 0.2–12 GHz
• High Input Power Sensitivity:
On–chip pre– and post–amps
-15 to +10 dBm (1–8 GHz)
The HMMC-3122 is a packaged GaAs HBT MMIC
prescaler which offers DC to 12 GHz frequency
translation for use in communications and EW systems
incorporating high–frequency PLL oscillator circuits and
signal–path down conversion applications. The
prescaler provides a large input power sensitivity
window and low phase noise.
-10 to +8 dBm (8–10 GHz)
-5 to +2 dBm (10–12 GHz)
• P : 0 dBm (0.5 V
)
p-p
out
Package Details
• Low Phase Noise: -153 dBc/Hz @ 100 kHz Offset
• (+) or (-) Single Supply Bias Operation
Package Type: SOIC-8 Plastic
Package Dimensions: 4.9 x 3.9 mm typ
Package Thickness: 1.55 mm typ
Lead Pitch: 1.25 mm nom
• Wide Bias Supply Range: 4.5 to 6.5 volt operating
range
• Differential I/0 with on–chip 50Ω matching
Lead Width: 0.42 mm nom
1
Absolute Maximum Ratings
(@ T = +25 °C, unless otherwise stated)
A
Symbol
VCC
Parameters/Conditions
Min
-7
Max
Units
volts
volts
volts
volts
dBm
volts
°C
Bias Supply Voltage
+7
VEE
Bias Supply Voltage
|VCC - VEE|
VLogic
Bias Supply Delta
+7
Logic Threshold Voltage
VCC - 1.5
VCC -1.2
+10
Pin(CW)
VRFin
CW RF Input Power
DC Input Voltage (@ RFin or RFin Ports)
Backside Operating Temperature
Storage Temperature
VCC 0.5
+85
2
TBS
-40
-65
Tst
+165
310
°C
Tmax
Maximum Assembly Temperature (60 seconds max)
°C
Notes:
1. Operation in excess of any parameter limit (except T ) may cause permanent damage to the device.
BS
6
2. MTTF >1 x 10 hours @ T <85°C. Operation in excess of maximum operating temperature (T ) will degrade MTTF.
BS
BS
DC Specifications/Physical Properties
(T = +25 °C, V - V = 5.0 volts, unless otherwise listed)
A
CC
EE
Symbol
Parameters/Conditions
Min
Typ
Max
Units
VCC - VEE
Operating bias supply difference1
Bias supply current
4.5
34
5.0
40
6.5
46
volts
mA
|ICC| or |IEE|
VRFin(q)
Quiescent dc voltage appearing at all RF ports
VCC
volts
VRFout(q)
VLogic
Nominal ECL Logic Level
VCC -1.45
VCC -1.32
VCC -1.25
volts
(VLogic contact self-bias voltage, generated on-chip)
Notes:
1. Prescaler will operate over full specified supply voltage range. V or V not to exceed limits specified in Absolute Maximum Ratings
CC
EE
section.
2
RF Specifications
(T = +25 °C, Z = 50 Ω, V - V = 5.0 volts)
A
0
CC
EE
Symbol
Parameters/Conditions
Min
Typ
Max
Units
ƒin(max)
ƒin(min)
ƒSel-Osc.
Pin
Maximum input frequency of operation
Minimum input frequency of operation1 (Pin = -10 dBm)
Output Self-Oscillation Frequency2
@ DC, (Square-wave input)
12
14
GHz
GHz
GHz
dBm
dBm
dBm
dBm
dBm
dB
0.2
0.5
3.4
-15
-15
-15
-10
-5
>-25
>-20
>-20
>-15
>-10
15
+10
+10
+10
+5
@ ƒin = 500 MHz, (Sine-wave input)
ƒin = 1 to 8 GHz
ƒin = 8 to 10 GHz
ƒin = 10 to 12 GHz
-1
RL
S12
jN
Small-Signal Input/Output Return Loss (@ ƒin <10 GHz)
Small-Signal Reverse Isolation (@ ƒin <10 GHz)
30
dB
SSB Phase noise (@ Pin = 0 dBm, 100 KHz offset from a ƒout =
1.2 GHz Carrier)
-153
dBc/Hz
Jitter
Input signal time variation @ zero-crossing (ƒin = 10 GHz, Pin
-10 dBm)
=
1
ps
Tr or Tf
Output transition time (10% to 90% rise/fall time)
@ ƒout < 1 GHz
70
ps
3
Pout
-2.0
-3.5
-4.5
0.0
dBm
dBm
dBm
volts
volts
volts
dBm
@ ƒout = 2.5 GHz
-1.5
-2.5
0.5
@ ƒout = 3.0 GHz
4
|Vout(p-p)
|
@ ƒout < 1 GHz
@ ƒout = 2.5 GHz
0.42
0.37
-50
@ ƒout = 3.0 GHz
PSpitback
ƒout power level appearing at RFin or RFout (@ ƒin 10 GHz,
Unused RFout or RFout unterminated)
ƒout power level appearing at RFin or RFout (@ ƒin 10 GHz, Both
RFout or RFout unterminated)
-55
-30
-25
dBm
dBc
dBc
Pfeedthru
Power level of ƒin appearing at RFout or RFout (@ ƒin = 12 GHz,
Pin = 0 dBm, Referred to Pin (ƒin))
H2
Second harmonic distortion output level (@ ƒout = 3.0 GHz,
Referred to Pout (ƒout))
Notes:
1. For sine–wave input signal. Prescaler will operate down to dc for square–wave input signal. Min. divide frequency limited by input slew
rate.
2. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition can be eliminated by use of the
Input dc offset technique described on page 4.
3. Fundamental of output square wave’s Fourier Series.
4. Square wave amplitude calculated from P
.
out
3
Applications
ac–Coupling and dc–Blocking
The HMMC-3122 is designed for use in high frequency
communications, microwave instrumentation, and EW
radar systems where low phase–noise PLL control
circuitry or broad–band frequency translation is
required.
All RF ports are dc connected on–chip to the V
CC
contact through on–chip 50Ω resistors. Under any bias
conditions where V is not dc grounded the RF ports
CC
should be ac coupled via series capacitors mounted
on the PC– board at each RF port. Only under bias
conditions where V is dc grounded (as is typical for
CC
Operation
negative bias supply operation) may the RF ports be
direct coupled to adjacent circuitry or in some cases,
such as level shifting to subsequent stages. In the latter
case the package heat sink may be “floated” and bias
The device is designed to operate when driven with
either a single–ended or differential sinusoidal input
signal over a 200 MHz to 12 GHz bandwidth. Below
200 MHz the prescaler input is “slew–rate” limited,
requiring fast rising and falling edge speeds to properly
divide. The device will operate at frequencies down to
dc when driven with a square–wave.
applied as the difference between V and V
.
CC
EE
Input dc Offset
If an RF signal with sufficient signal to noise ratio is
present at the RF input lead, the prescaler will operate
and provide a divided output equal the input frequency
divided by the divide modulus. Under certain “ideal”
conditions where the input is well matched at the right
input frequency, the component may “self–oscillate”,
especially under small signal input powers or with only
noise present at the input. This “self–oscillation” will
produce an undesired output signal also known as a
false trigger. To prevent false triggers or self– oscillation
conditions, apply a 20 to 100 mV dc offset voltage
between the RFin and RFin ports. This prevents noise
or spurious low level signals from triggering the divider.
Due to the presence of an off– chip RF–bypass
capacitor inside the package (connected to the V
CC
contact on the device), and the unique design of the
device itself, the component may be biased from either
a single positive or single negative supply bias. The
backside of the package is not dc connected to any dc
bias point on the device.
For positive supply operation, V pins are nominally
biased at any voltage in the +4.5 to +6.5 volt range
with pin 8 (V ) grounded. For negative bias operation
CC
EE
V
pins are typically grounded and a negative voltage
CC
between -4.5 to -6.5 volts is applied to pin 8 (V ).
EE
Adding a 10KΩ resistor between the unused RF input
to a contact point at the VEE potential will result in an
offset of » 25mV between the RF inputs. Note, however,
that the input sensitivity will be reduced slightly due
to the presence of this offset.
VCC
VCC
VCC
6
4
2
150p
V
cc
V
cc
V
cc
By
poss
50
50
50
50
OUT
IN
IN
IN
IN
OUT
5
7
3
÷
OUT
OUT
Pin 1
Vpwr
sel
V
ee
SOIC8 w/Backside GND
8
VEE
Figure 1. Simplified Schematic
4
Assembly Notes
Avago Technologies application note #54, “GaAs MMIC
ESD, Die Attach and Bonding Guidelines” provides
basic information on these subjects.
Independent of the bias applied to the package, the
backside of the package should always be connected
to both a good RF ground plane and a good thermal
heat sinking region on the PC–board to optimize
performance. For single–ended output operation the
unused RF output lead should be terminated into 50Ω
Moisture Sensitivity Classification: Class 1, per JESD22-
A112-A.
Additional References:
PN #18, “HBT Prescaler Evaluation Board.”
Notes:
to a contact point at the V potential or to RF ground
through a dc blocking capacitor.
CC
-
-
-
-
All dimensions in millimeters.
A minimum RF and thermal PC board contact area
equal to or greater than 2.67 x 1.65 mm (0.105" x
0.065") with eight 0.020" diameter plated–wall thermal
vias is recommended.
Refer to JEDEC Outline MS-012 for additional tolerances.
Exposed heat slug area on pkg bottom = 2.67 x 1.65
Exposed heat sink on package bottom must be soldered to PCB
RF ground plane.
MMIC ESD precautions, handling considerations, die
attach and bonding methods are critical factors in
successful GaAs MMIC performance and reliability.
Symbol
Min
1.35
0.0
Max
1.75
.25
A
A1
B
C
0.33
0.19
4.80
3.80
0.51
.025
5.00
4.00
D
E
e
1.27 BSC
H
L
5.80
0.40
0°
6.20
1.27
8°
a
Figure 2. Package & Dimensions
+6.5 volts
)
V
(+4.5 to
CC
~ 1 mf Mo
noblock
Capacitor
To operate component from a negative supply, ground each
connection and supply V witha negative voltage (-4.5
V
CC
EE
to -6.5v)bypassed to ground with~1 mf capacitor.
V
RFin
V
CC
RFout
CC
V
CC
RFin
V
EE
RFout
RF shouldbeterminatedin50Ωto ground. (dc blocking
out
capacitor required for positive bias configuration.)
Exposed heat sink on package bottom
must be soldered toPCB RF ground.
Figure 3. Assembly Diagram (Single-supply, Positive-bias Configuration shown)
5
Supplemental Data
Figure 4. Typical Input Sensitivity Window
Figure 5. Typical Supply Current & V
vs. Supply Voltage
Logic
Figure 6. Typical Phase Noise Performance
Figure 7. Typical Output Power vs. Output Frequency ƒ (GHz)
out
Figure 8. Typical “Spitback” Power (Pƒ ) appearing at RF input
out
port
6
Device Orientation
Reel
Tape
User
Feed
Direction
Cover Tape
Tape Dimensions and Product Orientation
2.0 0.05
See Note 6
1.5+0.1/-0.0
4.0
See Note 1
A
0.30 0.05
1.75
R0.3 MAX.
5.5 0.05
See Note 6
12.0 0.3
Bo
Ao
R0.5 Typical
Ko
1.5 MIN
SECTION A-A
A
Ao =6.4mm
Bo =5.2 mm
Ko =2.1 mm
8.0
Notes:
1. 10 sprocket hole pitch cumulative tolerance: 0.2mm.
2. Camber not to exceed 1mm in 100mm.
3. Material: Black Conductive Advantek Polystyrene.
4. Ao and Bo measured on a plane 0.3mm above the bottom of the pocket.
5. Ko measured from a plane on the inside bottom of the pocket to the top surface of the carrier.
6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.
7
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.
5989-0200EN - June 29, 2006
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