MGA-30989-BLKG [AVAGO]
2 - 6GHz, High Linearity Gain Block; 2 - 6GHz的，高线性增益模块
| 型号： | MGA-30989-BLKG |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 2 - 6GHz, High Linearity Gain Block |
| 文件： | 总13页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MGA-30989
2 - 6GHz, High Linearity Gain Block
Data Sheet
Description
Features
Avago Technologies’ MGA-30989 is a broadband, high
linearity gain block MMIC amplifier achieved through
the use of Avago Technologies’ proprietary 0.25um GaAs
Enhancement-mode pHEMT process.
•ꢀ High linearity
•ꢀ Built in temperature compensated internal bias circuitry
•ꢀ No RF matching components required
[1]
•ꢀ GaAs E-pHEMT Technology
The device required simple dc biasing components to
achieve wide bandwidth performance. The temperature
compensated internal bias circuit provides stable current
over temperature and process threshold voltage variation.
•ꢀ Standard SOT89 package
•ꢀ Single, Fixed 5V supply
•ꢀ Excellent uniformity in product specifications
•ꢀ MSL-1 and Lead-free halogen free
•ꢀ High MTTF for base station application
The MGA-30989 is housed inside a low cost RoHS
compliant SOT89 industry standard SMT package (4.5 x
4.1 x 1.5 mm).
Specifications
3.5GHz, 5V, 51mA (typical)
Component Image
•ꢀ 12 dB Gain
•ꢀ 36.8 dBm Output IP3
9GX
•ꢀ 2 dB Noise Figure
•ꢀ 23.6 dBm Output Power at 1dB gain compression
#3
RFout
#2
#1
RFin
#1
RFin
#2
#3
5GHz, 5V, 51mA (typical)
•ꢀ 9.6 dB Gain
GND
GND RFout
Top View
Bottom View
•ꢀ 38.4 dBm Output IP3
•ꢀ 1.65 dB Noise Figure
Notes:
Package marking provides orientation and identification
“9G”= Device Code
•ꢀ 23.8 dBm Output Power at 1dB gain compression
“X” = Month of Manufacture
Applications
•ꢀ IF amplifier, RF driver amplifier
•ꢀ General purpose gain block
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 50 V
Note:
1. Enhancement mode technology employs positive gate voltage,
thereby eliminating the need of negative gate voltage associated
with conventional depletion mode devices.
ESD Human Body Model = 1000 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.
[1]
Absolute Maximum Rating T =25°C
Thermal Resistance
A
[2]
Symbol
Vdd,max
Pin,max
Pdiss
Parameter
Units
V
Absolute Max.
Thermal Resistance
θ = 81.2°C/W
JC
(Vdd = 5 V, Ids = 48 mA, Tc = 85°C)
Device Voltage, RF output to ground
5.5
Notes:
CW RF Input Power
dBm
W
24
1. Operation of this device in excess of any of
these limits may cause permanent damage.
2. Thermal resistance measured using Infrared
measurement technique.
3. This is limited by maximum Vdd and Ids.
Derate 12.3 mW/°C for Tc >112°C.
Total Power Dissipation [3]
Junction Temperature
Storage Temperature
0.47
Tj,MAX
TSTG
°C
150
°C
-65 to 150
[1, 2]
Product Consistency Distribution Charts
LSL
USL
LSL
USL
50
60
8.5
9
9.5
10
10.5
Figure 1. Ids, LSL=42mA , nominal=51mA, USL=66mA
Figure 2. Gain, LSL=8.5dB, nominal=9.6dB, USL=10.5dB
LSL
LSL
35
36
37
38
39
22
22.5
23
23.5
24
24.5
Figure 3. OIP3, LSL=35dBm, nominal=38.4dBm
Figure 4. P1dB, LSL=22dBm, nominal=23.8dBm
USL
Notes:
1. Distribution data sample size is 3000 samples taken from 3 different
wafer lots. Future wafers allocated to this product may have nominal
values anywhere between the upper and lower limits.
2. Measurements were made on a characterization test board, which
represents a trade-off between optimal OIP3, gain and P1dB. Circuit
trace losses have not been de-embedded from measurements
above.
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
Figure 5. NF, nominal=1.65dB, USL=2.1dB
2
[1]
Electrical Specifications
T = 25°C, Vdd = 5V
A
Symbol
Ids
Parameter and Test Condition
Quiescent current
Gain
Frequency
Units
mA
dB
Min.
Typ.
Max.
N/A
42
51
66
Gain
3.5 GHz
5 GHz
12
9.6
8.5
35
–
10.5
–
OIP3 [2]
NF
Output Third Order Intercept Point
Noise Figure
3.5 GHz
5 GHz
dBm
dB
36.8
38.4
3.5 GHz
5 GHz
2
1.65
2.1
S11
Input Return Loss, 50Ω source
Output Return Loss, 50Ω load
Reverse Isolation
3.5 GHz
5 GHz
dB
-18
-16
S22
3.5 GHz
5 GHz
dB
-16
-15
S12
3.5 GHz
5 GHz
dB
-21
-18
OP1dB
Notes:
Output Power at 1dB Gain Compression
3.5 GHz
5 GHz
dBm
22
23.8
22
–
1. Measurements obtained using demo board described in Figure 22 and 23. Both 3.5GHz and 5GHz data were taken with 3GHz - 6GHz Application
Test Circuits.
2. OIP3 test condition: F - F = 10MHz with input power of -10dBm per tone measured at worse side band.
RF1
RF2
3. Use proper bias, heat sink and de-rating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application
note (if applicable) for more details.
3
Typical Performance (2GHz - 4GHz)
T = 25°C, Vdd = 5V, Input Signal = CW. Application Test Circuit is shown in Figure 22 and Table 1.
A
80
70
60
50
40
30
16
15
14
13
12
11
10
9
85°C
25°C
-40°C
8
7
6
Temperature (°C)
Frequency (GHz)
Figure 6. Ids over Temperature
Figure 7. Gain over Frequency and Temperature
46
44
42
40
38
36
34
32
30
28
26
27
26
25
24
23
22
21
20
19
18
17
85°C
25°C
-40°C
85°C
25°C
-40°C
Frequency (GHz)
Frequency (GHz)
Figure 8. OIP3 over Frequency and Temperature
Figure 9. P1dB over Frequency and Temperature
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
-35
-40
85°C
25°C
-40°C
85°C
25°C
-40°C
Frequency (GHz)
Frequency (GHz)
Figure 10. S11 over Frequency and Temperature
Figure 11. S22 over Frequency and Temperature
4
Typical Performance (2GHz - 4GHz)
T = 25°C, Vdd = 5V, Input Signal = CW. Application Test Circuit is shown in Figure 22 and Table 1.
A
-16
-18
-20
-22
-24
-26
-28
-30
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
85°C
25°C
-40°C
85°C
25°C
-40°C
Frequency (GHz)
Frequency (GHz)
Figure 13. Noise Figure over Frequency and Temperature
Figure 12. S12 over Frequency and Temperature
Typical Performance (3GHz - 6GHz)
T = 25°C, Vdd = 5V, Input Signal = CW. Application Test Circuit is shown in Figure 22 and Table 2.
A
80
70
60
50
40
30
16
15
14
13
12
11
10
9
85°C
25°C
-40°C
8
7
6
Temperature (°C)
Frequency (GHz)
Figure 14. Ids over Temperature
Figure 15. Gain over Frequency and Temperature
46
44
42
40
38
36
34
32
30
28
26
27
26
25
24
23
22
21
20
19
18
17
85°C
25°C
-40°C
85°C
25°C
-40°C
Frequency (GHz)
Frequency (GHz)
Figure 16. OIP3 over Frequency and Temperature
Figure 17. P1dB over Frequency and Temperature
5
Typical Performance (3GHz - 6GHz)
T = 25°C, Vdd = 5V, Input Signal = CW. Application Test Circuit is shown in Figure 22 and Table 2.
A
0
-5
0
-5
85°C
25°C
-40°C
85°C
25°C
-40°C
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
Frequency (GHz)
Frequency (GHz)
Figure 18. S11 over Frequency and Temperature
Figure 19. S22 over Frequency and Temperature
-11
-13
-15
-17
-19
-21
-23
-25
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
85°C
25°C
-40°C
85°C
25°C
-40°C
Frequency (GHz)
Frequency (GHz)
Figure 20. S12 over Frequency and Temperature
Figure 21. Noise Figure over Frequency and Temperature
6
Application Schematic Components Table and Demo Board
Vdd
C1
C2
C3
Top View
L1
Vdd
RFout 3
C8
C13
C14
C7
RFin
RFout
RFin
1
GND 2
Figure 22. Application Schematic
C14
C13
– Recommended PCB material is 10 mils Rogers RO4350,
with FR4 backing for mechanical strength.
– Suggested component values may vary according to
layout and PCB material.
Figure 23. Demo board Layout
7
Demo board Part List
Table 1. 2GHz - 4GHz Application Schematic Components
Circuit Symbol
Size
Value
8.2nH
100pF
0.1uF
2.2uF
1nH
Part Number
Description
L1
0603
0402
0402
0805
0402
0402
0402
0402
LLQ1608-F8N2 (Toko)
Wire Wound Chip Inductor
Ceramic Chip Capacitor
Ceramic Chip Capacitor
Ceramic Chip Capacitor
MLC Inductor
C1
GRM1555C1H101JZ01 (Murata)
GRM155R71C104KA88D (Murata)
GRM21BR61E225KA12L (Murata)
LL1005-FHL1N0 (Toko)
C2
C3
C7
C8
1nH
LL1005-FHL1N0 (Toko)
MLC Inductor
C13
C14
39pF
39pF
CM05CH390J50AH (Kyocera)
CM05CH390J50AH (Kyocera)
Ceramic Chip Capacitor
Ceramic Chip Capacitor
Table 2. 3GHz - 6GHz Application Schematic Components
Circuit Symbol
Size
Value
8.2nH
100pF
0.1uF
2.2uF
39pF
39pF
Part Number
Description
L1
0603
0402
0402
0805
0402
0402
LLQ1608-F8N2 (Toko)
GRM1555C1H101JZ01 (Murata)
GRM155R71C104KA88D (Murata)
GRM21BR61E225KA12L (Murata)
CM05CH390J50AH (Kyocera)
CM05CH390J50AH (Kyocera)
NA
Wire Wound Chip Inductor
Ceramic Chip Capacitor
Ceramic Chip Capacitor
Ceramic Chip Capacitor
Ceramic Chip Capacitor
Ceramic Chip Capacitor
C1
C2
C3
C7
C8
C13
C14
NA
Test Circuit for S-Parameter and Noise Parameter
Top View
Port1
RFin
1
GND
2
3
Vdd
RFout
Port2 /
Bias Tee
Figure 24. S-parameter and Noise parameter test circuit
8
Typical S-Parameter (Vdd = 5V, T = 25°C, 50 ohm)
A
S11
(dB)
-0.83
S11
(ang)
171.33
133.94
69.70
S21
(dB)
S21
(ang)
107.91
73.45
S12
(dB)
S12
(ang)
11.18
8.53
S22
(dB)
-11.42
-9.79
S22
(ang)
156.15
54.38
Freq (GHz)
0.1
0.5
1
-49.08
-29.47
-7.88
14.19
15.26
15.08
14.78
14.41
14.06
13.71
13.35
12.98
12.60
12.21
11.82
11.45
11.09
10.78
10.50
10.23
9.97
-70.09
-72.22
-51.74
-28.40
-24.68
-23.80
-23.09
-22.45
-21.86
-21.30
-20.77
-20.30
-19.87
-19.49
-19.14
-18.81
-18.49
-18.16
-17.82
-17.50
-17.18
-16.90
-16.65
-16.45
-16.30
-16.21
-16.17
-16.19
-16.24
-16.31
-16.31
-16.20
-16.99
-18.81
-19.97
-19.81
-18.85
-19.03
-18.91
-17.33
-15.36
-12.58
-10.96
-0.85
-1.73
124.85
-16.36
-118.45
-146.17
-169.72
169.77
151.46
134.78
119.28
104.86
91.24
42.20
-110.19
162.38
140.85
123.10
107.84
94.47
82.34
71.05
60.36
50.23
40.73
31.67
23.05
14.81
6.72
-7.59
-28.70
-84.47
-119.30
-136.97
-147.15
-119.61
-73.79
-90.05
-116.49
-140.25
-159.02
-173.92
175.19
166.34
160.06
154.58
150.45
145.29
123.26
106.21
91.68
1.5
2
-18.64
-16.77
-17.69
-17.47
-17.54
-18.71
-21.50
-26.62
-25.94
-20.44
-16.93
-14.77
-13.39
-12.66
-12.37
-12.28
-12.32
-11.90
-11.51
-10.94
-10.14
-9.13
13.90
-13.30
-16.46
-20.71
-27.25
-36.62
-33.44
-29.50
-26.66
-23.92
-21.74
-20.32
-19.31
-19.03
-19.23
-19.80
-20.57
-21.46
-24.67
-23.37
-21.51
-19.44
-17.49
-15.67
-13.97
-12.52
-11.26
-10.27
-7.84
21.81
2.2
2.4
2.6
2.8
3
26.98
27.84
21.54
9.75
-7.64
3.2
3.4
3.6
3.8
4
-45.95
-124.50
-160.65
-177.59
170.22
160.76
151.96
142.32
131.95
119.49
102.53
86.82
78.46
66.38
4.2
4.4
4.6
4.8
5
54.96
43.99
33.45
23.16
-1.24
12.97
-9.24
5.2
5.4
5.6
5.8
6
2.27
-17.80
-25.83
-33.97
-42.22
-50.47
-58.70
-66.81
-74.66
-82.14
-89.21
-120.23
-152.20
175.54
150.58
134.70
116.35
92.19
65.52
51.09
35.32
16.25
-11.48
-43.88
9.69
-7.74
70.38
9.40
-17.72
-27.77
-37.67
-47.47
-57.15
-66.64
-75.60
-83.99
-121.23
-158.46
164.95
136.43
117.68
96.90
53.71
9.10
79.92
38.09
8.75
69.67
6.2
6.4
6.6
6.8
7
-8.04
24.75
8.37
59.26
-6.95
13.52
7.95
48.91
-5.97
4.20
7.50
38.89
-5.14
-2.97
7.00
28.93
-4.46
-8.67
6.51
19.35
8
-2.90
-25.68
-52.31
-90.52
-118.15
-129.25
-143.32
-166.19
168.37
157.29
147.97
133.03
112.54
92.05
4.58
-28.28
-69.12
-97.97
-118.40
-131.60
-146.90
-168.13
162.57
153.40
140.45
133.73
116.79
93.24
9
-2.46
2.99
-6.19
10
11
12
13
14
15
16
17
18
19
20
-1.73
0.67
-4.64
-0.89
-2.55
-5.00
-6.00
-6.20
-7.47
-8.58
-8.14
-7.18
-5.32
-4.57
-3.14
-0.61
-2.55
-0.76
-2.38
-1.01
70.58
-2.68
-0.88
41.66
-2.36
-0.85
25.78
-2.07
-1.18
9.21
-2.29
-1.83
-10.20
-38.11
-70.41
-2.52
-3.05
-4.28
-4.26
-5.03
9
Typical Noise Parameters (Vdd = 5V, T = 25°C, 50 ohm)
Part Number Ordering Information
A
Part Number
No. of Devices
Container
Freq (GHz)
2.0
F
(dB)
Γ
Mag
Γ
49
Ang
R /Z
n 0
min
opt
opt
MGA-30989-BLKG
MGA-30989-TR1G
100
Antistatic Bag
13”Tape/Reel
2.95
2.32
1.83
1.54
1.53
1.61
1.78
2.05
2.22
0.086
0.12
0.15
0.18
0.22
0.24
0.27
0.30
0.33
0.52
0.29
0.19
0.18
0.17
0.21
0.22
0.32
0.37
3000
2.5
90
3.0
122
174
-145
-103
-62
-35
-7.8
3.5
4.0
4.5
5.0
5.5
6.0
10
SOT89 Package Dimensions
D
D
POLISH
D1
D1
E1
L
E1
OR
E
E
L
e
e
C
S
e1
S
e1
1.625
D2
D1
MATTE FINISH
HALF ETCHING
DEPTH 0.100
A
OR
E
b
b1
b
POLISH
b1
Dimensions in mm
Dimensions in inches
Symbols
Minimum
1.40
0.89
0.36
0.41
0.38
4.40
1.40
1.45
3.94
2.40
2.90
0.65
1.40
Nominal
1.50
1.04
0.42
0.47
0.40
4.50
1.60
1.65
-
Maximum
1.60
1.20
0.48
0.53
0.43
4.60
1.75
1.80
4.25
2.60
3.10
0.85
1.60
Minimum
0.055
0.0350
0.014
0.016
0.014
0.173
0.055
0.055
0.155
0.094
0.114
0.026
0.054
Nominal
0.059
0.041
0.016
0.018
0.015
0.177
0.062
0.062
-
Maximum
0.063
0.047
0.018
0.030
0.017
0.181
0.069
0.069
0.167
0.102
0.122
0.034
0.063
A
L
b
b1
C
D
D1
D2
E
E1
e1
S
2.50
3.00
0.75
1.50
0.098
0.118
0.030
0.059
e
11
Device Orientation
REEL
CARRIER
TAPE
USER FEED
DIRECTION
COVER TAPE
Tape Dimensions
Ø 1.5 +0.1/-0.0
8.00
Ø 1.50 MIN.
2.00 .05 SEE NOTE 3
4.00 SEE NOTE 1
1.75 .10
0.30 .05
R 0.3 MAX.
A
A
5.50 .05
SEE NOTE 3
Bo
12.0 .3
Ko
R 0.3 TYP.
Ao
SECTION A - A
Ao = 4.60
Bo = 4.90
Ko = 1.90
DIMENSIONS IN MM
NOTES:
1. 10 SPROCKET HOLE PITCH CUMULATIVE TOLERANCE 0.2
2. CAMBER IN COMPLIANCE WITH EIA 481
3. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED
AS TRUE POSITION OF POCKET, NOT POCKET HOLE
12
Reel Dimensions – 13” Reel
R
R
LOKREEL
MINNEAPOLIS USA
U.S PAT 4726534
102.0
REF
ATTENTION
Electrostatic Sensitive Devices
Safe Handling Required
1.5
88 REF
330.0
REF
"A"
96.5
6
PS
Detail "B"
+0.3
- 0.2
(MEASURED AT HUB)
(MEASURED AT HUB)
8.4
6
PS
11.1 MAX.
Detail "A"
Ø 20.2
Dimensions in mm
Ø 13.0 +0.5
-0.2
2.0 0.5
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-2251EN - May 23, 2013
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