ADC80MAH-12-BI [BB]
ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, Word Access, Hybrid, CDIP32, HERMETIC SEALED PACKAGE-32;![ADC80MAH-12-BI](http://pdffile.icpdf.com/pdf1/p00097/img/icpdf/ADC80MAH-12_515815_icpdf.jpg)
型号: | ADC80MAH-12-BI |
厂家: | ![]() |
描述: | ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Serial, Parallel, Word Access, Hybrid, CDIP32, HERMETIC SEALED PACKAGE-32 转换器 |
文件: | 总4页 (文件大小:44K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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®
ADC80MAH-12
Monolithic12-Bit
ANALOG-TO-DIGITAL CONVERTER
circuits have been redesigned to allow simplified free-
running operation with internal or external clock.
FEATURES
● INDUSTRY-STANDARD 12-BIT ADC
● MONOLITHIC CONSTRUCTION
● LOW COST
Data is available in parallel and serial form with
corresponding clock and status signals. All digital
input and output signals are TTL/LSTTL-compatible,
with internal pull-up resistors included on all digital
inputs to eliminate the need for external pull-up resis-
tors on digital inputs not requiring connection. The
ADC80MAH-12 operates equally well with either
±15V or ±12V analog power supplies, and also re-
quires use of a +5V logic power supply. However,
unlike many ADC80-type products, a +5V analog
power supply is not required. It is packaged in a
hermetic 32-pin side-brazed ceramic dual-in-line pack-
age.
● ±0.012% LINEARITY
● 25µs max CONVERSION TIME
● ±12V OR ±15V OPERATION
● NO MISSING CODES: –25°C to +85°C
● HERMETIC 32-PIN PACKAGE
● PARALLEL OR SERIAL OUTPUTS
● 705mW max DISSIPATION
DESCRIPTION
The ADC80MAH-12 is a 12-bit single-chip succes-
sive-approximation analog-to-digital converter for low
cost converter applications. It is complete with a
comparator, a 12-bit DAC which includes a 6.3V
reference laser-trimmed for minimum temperature
coefficient, a successive approximation register (SAR),
clock, and all other associated logic functions.
Clock
Inhibit
External
Clock
Clock
Out
Clock
Short
Cycle
Parallel
Data
Output
Comparator
In
Successive
Approximation
Register
Internal scaling resistors are provided for the selection
of analog input signal ranges of ±2.5V, ±5V, ±10V, 0
to +5V, or 0 to +10V. Gain and offset errors may be
externally trimmed to zero, enabling initial end-point
accuracies of better than ±0.12% (±1/2LSB).
Serial
Out
20V Range
10V Range
Comparator
The maximum conversion time of 25µs makes the
ADC80MAH-12 ideal for a wide range of 12-bit
applications requiring system throughput sampling
rates up to 40kHz. In addition, this A/D converter may
be short-cycled for faster conversion speed with re-
duced resolution, and an external clock may be used to
synchronize the converter to the system clock or to
obtain higher-speed operation. The convert command
12-Bit D/A
Converter
Bipolar
Offset
Reference Out
International Airport Industrial Park
•
Mailing Address: PO Box 11400
Cable: BBRCORP
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111
•
•
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1986 Burr-Brown Corporation
PDS-694A
Printed in U.S.A. October, 1993
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, ±VCC = 12V or 15V, VDD = +5V, unless otherwise specified.
ADC80MAH-12
TYP
PARAMETER
RESOLUTION
INPUT
MIN
MAX
UNITS
12
Bits
ANALOG
Voltage Ranges: Unipolar
Bipolar
0 to +5, 0 to +10
±2.5, ±5, ±10
V
V
Impedance: 0 to +5V, ±2.5V
0 to +10V, ±5V
±10V
2.45
4.9
9.8
2.5
5
10
2.55
5.1
10.2
kΩ
kΩ
kΩ
DIGITAL
Logic Characteristics (Over specification temperature range)
VIH (Logic “1”)
VIL (Logic “0”)
IIH (VIN = +2.7V)
IIL (VIN = +0.4V)
2
–0.3
5.5
+0.8
20
V
V
µA
µA
µs
–20
100ns
Convert Command Pulse Width(1)
20
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error(2)
±0.01
±0.05
±0.1
±0.3
±0.2
±0.3
±0.012
±3/4
% of FSR(3)
% of FSR
% of FSR
% of FSR
LSB
Offset Error(2): Unipolar
Bipolar
Linearity Error
Differential Linearity Error
Inherent Quantization Error
±1/2
±1/2
LSB
POWER SUPPLY SENSITIVITY
11.4V ≤ ±VCC ≤ 16.5V
+4.5V ≤ ±VDD ≤ +5.5V
±0.003
±0.002
±0.009
±0.005
% of FSR/%VCC
% of FSR/%VDD
DRIFT
Total Accuracy, Bipolar(4)
Gain
Offset: Unipolar
Bipolar
Linearity Error Drift
Differential Linearity over Temperature Range
No Missing Code Temperature Range
Monotonicity Over Temperature Range
±10
±15
±3
±7
±1
±23
±30
ppm/°C
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
LSB
±15
±3
±3/4
±85
–25
°C
Guaranteed
22
CONVERSION TIME(5)
OUTPUT
25
µs
DIGITAL (Bits 1-12 , Clock Out, Status, Serial Out)
Output Codes(6)
Parallel: Unipolar
CSB
Bipolar
Serial (NRZ)(7)
COB, CTC
CSB, COB
Logic Levels: Logic 0 (ISINK ≤ 3.2mA)
Logic 1 (ISOURCE ≤ 80µA)
Internal Clock Frequency
+0.4
V
V
kHz
+2.4
520
INTERNAL REFERENCE VOLTAGE
Voltage
Source Current Available for External Loads(8)
Temperature Coefficient
+6.20
200
+6.3
+6.40
V
µA
ppm/°C
±10
±30
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
2
ADC80MAH-12
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = +25°C, ±VCC = 12V or 15V, VDD = +5V, unless otherwise specified.
ADC80MAH-12
TYP
PARAMETER
MIN
MAX
UNITS
POWER SUPPLY REQUIREMENTS
Rated Supply Voltages
Supply Ranges: ±VCC
+5, ±12 or ±15
V
V
V
mA
mA
mA
mW
°C/W
±11.4
+4.5
+16.5
+5.5
11
24
36
VDD
Supply Drain: +ICC (+VCC = 15V)
–ICC (–VCC = 15V)
IDD (VCC = 5V)
Power Dissipation (±VCC = 15V, VDD = 5V)
Thermal Resistance, θJA
8.5
21
30
593
50
705
TEMPERATURE RANGE (Ambient)
Specification
Operating (derated specs)
Storage
–25
–55
–65
+85
+125
+150
°C
°C
°C
NOTES: (1) Accurate conversion will be obtained with any convert command pulse width of greater than 100ns; however, it must be limited to 20µs (max) to assure
the specified conversion time. (2) Gain and offset errors are adjustable to zero. See “Optional External Gain and Offset Adjustment” section. (3) FSR means Full-
Scale Range and is 20V for ±10V range, 10V for ±5V and 0 to +10V ranges, etc. (4) Includes drift due to linearity, gain, and offset drifts. (5) Conversion time is
specified using internal clock. For operation with an external clock see “Clock Options” section. This converter may also be short-cycled to less than 12-bit resolution
for shorter conversion time; see “Short Cycle Feature” section. (6) CSB means Complementary Straight Binary, COB means Complementary Offset Binary, and
CTC means Complementary Two’s Complement coding. See Table I for additional information. (7) NRZ means Non-Return-to-Zero coding. (8) External loading
must be constant during conversion, and must not exceed 200µA for guaranteed specification.
ABSOLUTE MAXIMUM RATINGS PCM1760
ORDERING INFORMATION
RESOLUTION
(Bits)
+VCC to Analog Common ........................................................ 0 to +16.5V
–VCC to Analog Common ........................................................ 0 to –16.5V
MODEL
V
DD to Digital Common ................................................................ 0 to +7V
ADC80MAH-12
12
Analog Common to Digital Common ................................................ ±0.5V
Logic Inputs (Convert Command, Clock In)
BURN-IN SCREENING OPTION
BURN-IN TEMPERATURE
(160h)(1)
to Digital Common ........................................................... –0.3V to +VCC
Analog Inputs (Analog In, Bipolar Offset)
MODEL
to Analog Common ..................................................................... ±16.5V
Reference Output ......................................... Indefinite Short to Common,
Momentary Short to VCC
ADC80MAH-12-BI
12
NOTE: (1) Or equivalent.
Lead Temperature, (soldering, 10s) .............................................. +300°C
Maximum Junction Temperature .................................................. +160°C
PACKAGE INFORMATION
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE DRAWING
NUMBER(1)
MODEL
PACKAGE
ADC80MAH-12
32-Pin Hermetic
212
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
ADC80MAH-12
PIN ASSIGNMENTS
CONNECTION DIAGRAM
PIN
DESCRIPTION
PIN
DESCRIPTION
Top View
1
2
Bit 6
Bit 5
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Bit 7
Bit 8
1
2
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
Bit 4
Bit 9
4
Bit 3
Bit 10 (LSB-10 Bits)
Bit 11
5
Bit 2
6
Bit 1 (MSB)
NC(1)
Bit 12 (LSB-12 Bits)
Serial Out
12-Bit Successive
Approximation Register
7
4
5
8
Bit 1 (MSB)
+5V Digital Supply
Digital Common
Comparator In
Bipolar Offset
R1 10V Range
R2 20V Range
Analog Common
Gain Adjust
–VCC
9
Reference Out (+6.3V)
Clock Out
10
11
12
13
14
15
16
6
Status
Short Cycle
Clock Inhibit
External Clock
Convert Command
+VCC
7
8
12-Bit D/A
Converter
9
10
11
12
13
14
15
16
NOTE: (1) +5V applied to pin 7 has no effect on circuit.
6.3kΩ
R1
5kΩ
R2
5kΩ
Clock
Covert
Command
tCD
Internal
Clock
tCP
tCW
tSD
Status
tR
Bit 1
Bit 2
Bit 3
Bit 4
Bit 12
tDV
Serial
Data
Data Invalid
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12
SYMBOL
PARAMETER
TYP
UNITS
tCD
tCP
tCW
tSD
tR
Clock delay from convert command
Nominal clock period
153
1.81
0.87
186
141
–15
ns
µs
µs
ns
ns
ns
Nominal clock pulse width
Status delay from convert command
All bits reset delay from convert command
Data valid time from clock pulse high
tDV
FIGURE 1. Timing Diagram (nominal values at +25°C with internal clock).
®
4
ADC80MAH-12
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