ADS1217IPFBT [BB]
8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER; 8通道，24位模拟数字转换器
| 型号： | ADS1217IPFBT |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总28页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1217
A
D
S
1
2
1
7
SBAS260B – MAY 2002 – REVISED OCTOBER 2004
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● 24 BITS NO MISSING CODES
● INL: 0.0012% of FSR (max)
● FULL-SCALE INPUT: ±2VREF
● PGA FROM 1 TO 128
The ADS1217 is a precision, wide dynamic range, delta-
sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-
tion operating from 2.7V to 5.25V supplies. The delta-sigma,
A/D converter provides up to 24 bits of no missing code
performance and effective resolution of 22 bits.
● 22 BITS EFFECTIVE RESOLUTION
The eight input channels are multiplexed. Internal buffering
can be selected to provide a very high input impedance for
direct connection to transducers or low-level voltage signals.
Burnout current sources are provided that allow for the
detection of an open or shorted sensor. An 8-bit Digital-to-
Analog Converter (DAC) provides an offset correction with a
range of 50% of the FSR (Full-Scale Range).
(PGA = 1), 19 BITS (PGA = 128)
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
● ON-CHIP 1.25V/2.5V REFERENCE
● ON-CHIP CALIBRATION
The PGA (Programmable Gain Amplifier) provides selectable
gains of 1 to 128 with an effective resolution of 19 bits at a gain
of 128. The A/D conversion is accomplished with a 2nd-order,
delta-sigma modulator and programmable sinc filter. The
reference input is differential and can be used for ratiometric
measurements. The onboard current DACs operate indepen-
dently with the maximum current set by an external resistor.
● SPI COMPATIBLE
● POWER SUPPLY: 2.7V to 5.25V
● < 1mW POWER CONSUMPTION, VDD = 3V
APPLICATIONS
The serial interface is SPI compatible. Eight bits of digital I/O
are also provided that can be used for input or output. The
ADS1217 is designed for high-resolution measurement appli-
cations in smart transmitters, industrial process control, weigh
scales, chromatography, and portable instrumentation.
● INDUSTRIAL PROCESS CONTROL
● LIQUID/GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
● WEIGH SCALES
AGND AVDD
RDAC
VREFOUT
VRCAP
VREF+ VREF–
XIN
XOUT
8-Bit
IDAC2
IDAC
Clock Generator
● PRESSURE TRANSDUCERS
Voltage
Reference
8-Bit
IDAC
IDAC1
Offset
DAC
PDWN
DYSNC
RESET
A
IN0
AIN
AIN
AIN
AIN
AIN
AIN
AIN
1
2
3
4
5
6
7
Registers
Program-
Controller
2nd-Order
Modulator
mable
Digital
Filter
MUX
+
BUF
PGA
RAM
POL
SCLK
DIN
AINCOM
Serial Interface
DOUT
CS
Digital I/O
Interface
DRDY
BUFEN
DVDD DGND
D0 ... D7
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002-2004, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
AVDD to AGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
IN ................................................................... GND –0.5V to AVDD + 0.5V
AVDD to DVDD ........................................................................... –6V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND .................................... –0.3V to DVDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS1217
TQFP-48
PFB
–40°C to +85°C
ADS1217
ADS1217IPFBT
ADS1217IPFBR
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
"
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V,
unless otherwise specified.
ADS1217
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM
Full-Scale Input Voltage
Analog Input Voltage
)
(AIN+) – (AIN–
Buffer OFF
Buffer ON
)
±2VREF /PGA
V
V
V
AGND – 0.1
AGND + 0.05
AVDD + 0.1
AVDD – 1.5
Differential Input Impedance
Input Current
Buffer OFF
Buffer ON
10/PGA
0.5
MΩ
nA
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
–3dB
–3dB
–3dB
0.469fDATA
0.318fDATA
0.262fDATA
Hz
Hz
Hz
Programmable Gain Amplifier
Burnout Current Sources
User Selectable Gain Ranges
1
8
128
2
µA
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
±VREF /(PGA)
V
Bits
%
±1
1
ppm/°C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Nonlinearity
24
Bits
Bits
% of FSR(1)
Sinc3 Filter
End Point Fit, Differential Input,
Buffer Off
24
0.0012
0.0003
Offset Error
Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection
Before Calibration
7.5
0.02
0.005
0.5
ppm of FSR
ppm of FSR/°C
Before Calibration
%
ppm/°C
dB
at DC
100
f
CM = 60Hz, fDATA = 10Hz
130
120
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 50Hz
SIG = 60Hz, fDATA = 60Hz
dB
Output Noise
Power-Supply Rejection
See Typical Characteristics
95
(2)
at DC, dB = –20log(∆VOUT /∆VDD
)
80
dB
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1217
SBAS260B
2
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications at –40°C to +85°C, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V,
unless otherwise specified.
ADS1217
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REFERENCE INPUT
Reference Input (VREF
Negative Reference Input (VREF–
Positive Reference Input (VREF+
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
)
VREF ≡ (VREF+) – (VREF–
)
0.1
2.5
2.6
V
V
V
dB
dB
µA
)
AGND – 0.1
(VREF–) + 0.1
(VREF+) – 0.1
AVDD + 0.1
)
at DC
120
120
1.3
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 2.5V, PGA = 1
ON-CHIP VOLTAGE REFERENCE
Output Voltage
REF HI = 1
REF HI = 0
2.4
2.5
1.25
8
50
15
10
3
2.6
V
V
mA
Short-Circuit Current Source
Short-Circuit Current Sink
Drift
Noise
Output Impedance
Startup Time
µA
ppm/°C
µVrms
Ω
VRCAP = 0.1µF, BW = 0.1Hz to 100Hz
Sourcing 100µA
5
ms
IDAC
Full-Scale Output Current
RDAC = 150kΩ, Range = 1
RDAC = 150kΩ, Range = 2
RDAC = 150kΩ, Range = 3
RDAC = 15kΩ, Range = 3
0.5
1
2
mA
mA
mA
mA
kΩ
Bits
V
20
Current Setting Resistance (RDAC
Monotonicity
Compliance Voltage
Output Impedance
PSRR
)
10
8
0
RDAC = 150kΩ
AVDD – 1
See Typical Characteristics
VOUT = AVDD/2, Code > 16
Individual IDAC
400
5
ppm/V
%
Gain Error
Gain Error Drift
Gain Error Mismatch
Gain Error Mismatch Drift
Individual IDAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
75
0.25
15
ppm/°C
%
ppm/°C
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AVDD
4.75
5.25
V
Analog Current (IADC + IVREF + IIDAC)
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
1
nA
µA
µA
µA
µA
µA
µA
A/D Converter Current (IADC
)
175
500
250
900
250
480
275
750
350
1375
375
675
VREF Current (IVREF
)
IIDAC Current (IIDAC
)
Excludes Load Current
Digital Current
Normal Mode, DVDD = 5V
SLEEP Mode, DVDD = 5V
Read Data Continuous Mode, DVDD = 5V
PDWN = 0
180
150
230
1
275
µA
µA
µA
nA
Power Dissipation
PGA = 1, Buffer OFF, REFEN = 0,
IDACs OFF, DVDD = 5V
1.8
2.8
mW
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1217
SBAS260B
3
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V,
unless otherwise specified.
ADS1217
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM
Full-Scale Input Voltage
Analog Input Range
)
(AIN+) – (AIN–
Buffer OFF
Buffer ON
Buffer OFF
Buffer ON
)
±2VREF /PGA
V
V
V
MΩ
nA
AGND – 0.1
AGND + 0.05
AVDD + 0.1
AVDD – 1.5
Input Impedance
Input Current
10/PGA
0.5
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
–3dB
–3dB
–3dB
0.469fDATA
0.318fDATA
0.262fDATA
Hz
Hz
Hz
Programmable Gain Amplifier
Burnout Current Sources
User Selectable Gain Ranges
1
8
128
2
µA
OFFSET DAC
Offset DAC Range
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
±VREF /(PGA)
V
Bits
%
±1
2
ppm/°C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Nonlinearity
24
Bits
Bits
% of FSR(1)
Sinc3 Filter
End Point Fit, Differential Input,
Buffer Off, T = 25°C
24
0.0012
0.0003
Offset Error
Offset Drift
Gain Error
Gain Error Drift
Common-Mode Rejection
Before Calibration
15
0.04
0.010
1.0
ppm of FSR
ppm of FSR/°C
Before Calibration
%
ppm/°C
dB
at DC
100
f
CM = 60Hz, fDATA = 10Hz
130
120
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 50Hz
SIG = 60Hz, fDATA = 60Hz
dB
Output Noise
Power-Supply Rejection
See Typical Characteristics
90
(2)
at DC, dB = –20 log(∆VOUT /∆VDD
)
75
dB
VOLTAGE REFERENCE INPUT
Reference Input (VREF
Negative Reference Input (VREF–
Positive Reference Input (VREF+
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
)
VREF ≡ (VREF+) – (VREF–
)
0.1
1.25
1.3
V
V
V
dB
dB
µA
)
AGND – 0.1
(VREF–) + 0.1
(VREF+) – 0.1
AVDD + 0.1
)
at DC
120
120
0.65
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 1.25V
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Short-Circuit Current Source
Short-Circuit Current Sink
Drift
Noise
Output Impedance
Startup Time
REF HI = 0
1.2
1.25
3
50
15
10
3
1.3
V
mA
µA
ppm/°C
µVrms
Ω
VRCAP = 0.1µF, BW = 0.1Hz to 100Hz
Sourcing 100µA
5
ms
IDAC
Full-Scale Output Current
RDAC = 75kΩ, Range = 1
RDAC = 75kΩ, Range = 2
RDAC = 75kΩ, Range = 3
RDAC = 15kΩ, Range = 3
0.5
1
2
mA
mA
mA
mA
kΩ
Bits
V
20
Current Setting Resistance (RDAC
Monotonicity
Compliance Voltage
Output Impedance
PSRR
)
10
8
0
RDAC = 75kΩ
AVDD – 1
See Typical Characteristics
VOUT = AVDD /2, Code > 16
Individual IDAC
600
5
ppm/V
%
Gain Error
Gain Error Drift
Gain Error Mismatch
Gain Error Mismatch Drift
Individual IDAC
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
75
0.25
15
ppm/°C
%
ppm/°C
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1217
SBAS260B
4
www.ti.com
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications at –40°C to +85°C, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA = 10Hz, and VREF = +1.25V,
unless otherwise specified.
ADS1217
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AVDD
2.7
3.3
V
Analog Current (IADC + IVREF + IIDAC
)
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
1
nA
µA
µA
µA
µA
µA
µA
A/D Converter Current (IADC
)
160
450
230
850
250
480
250
700
325
1325
375
675
VREF Current (IVREF
)
IIDAC Current (IIDAC
)
Excludes Load Current
Digital Current
Normal Mode, DVDD = 3V
SLEEP Mode, DVDD = 3V
Read Data Continuous Mode, DVDD = 3V
PDWN = 0
90
75
113
1
200
µA
µA
µA
nA
Power Dissipation
PGA = 1, Buffer OFF, REFEN = 0,
IDACs OFF, DVDD = 3V
0.8
1.4
mW
NOTES: (1) FSR is Full-Scale Range. (2) ∆VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ELECTRICAL CHARACTERISTICS: Digital
All specifications at –40°C to +85°C, and DVDD = +2.7V to 5.25V.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT/OUTPUT
Logic Level
VIH
0.8 × DVDD
DGND
DVDD
0.2 × DVDD
V
V
(1)
VIL
VOH
VOL
IOH = 1mA
IOL = 1mA
0 < VI < DVDD
DVDD – 0.4
DGND
V
V
µA
DGND + 0.4
10
Input Leakage: IIN
–10
CLOCK RATES
Master Clock Rate: fOSC
Master Clock Period: tOSC
1
125
8
MHz
ns
1/fOSC
1000
NOTE: (1) Maximum VIL for XIN is DGND + 0.05V.
ADS1217
SBAS260B
5
www.ti.com
PIN CONFIGURATION
Top View
TQFP
36 35 34 33 32 31 30 29 28 27 26 25
D0 37
D1 38
24 RESET
23 BUFEN
22 DGND
21 DGND
20 DGND
19 DGND
18 DGND
17 RDAC
D2 39
D3 40
D4 41
D5 42
ADS1217
D6 43
D7 44
AGND 45
VREFOUT 46
VREF+ 47
VREF– 48
16 IDAC2
15 IDAC1
14 VRCAP
13 AVDD
1
2
3
4
5
6
7
8
9
10 11 12
PIN DESCRIPTIONS
PIN
PIN
NUMBER
NAME
DESCRIPTION
NUMBER
NAME
DESCRIPTION
25
26
27
XIN
Clock Input
1
2
AVDD
Analog Power Supply
Analog Ground
Analog Input 0
XOUT
Clock Output, used with crystal or resonator.
AGND
PDWN
Active LOW. Power Down. The power-down
function shuts down the analog and digital
circuits.
3
A
A
IN0
IN1
4
Analog Input 1
5
AIN
2
Analog Input 2
28
29
POL
DSYNC
DGND
DVDD
DRDY
CS
Serial Clock Polarity Input
Active LOW, Synchronization Control Input
Digital Ground
6
A
A
IN3
IN4
Analog Input 3
7
Analog Input 4
30
8
AIN
5
Analog Input 5
31
Digital Power Supply
9
A
A
IN6
IN7
Analog Input 6
32
Active LOW, Data Ready Output
Active LOW, Chip Select Input
Serial Clock, Schmitt Trigger
Serial Data Input, Schmitt Trigger
Serial Data Output
10
11
12
13
14
15
16
17
18-22
23
24
Analog Input 7
33
AINCOM
AGND
AVDD
Analog Input Common
Analog Ground
Analog Power Supply
34
SCLK
DIN
35
36
DOUT
VRCAP
IDAC1
IDAC2
RDAC
VREFOUT Bypass Capacitor
Current DAC1 Output
Current DAC2 Output
Current DAC Resistor
Digital Ground
37-44
45
D0-D7
AGND
VREFOUT
VREF+
VREF–
Digital I/O 0-7
Analog Ground
46
Voltage Reference Output
Positive Differential Reference Input
Negative Differential Reference Input
47
DGND
BUFEN
RESET
48
Buffer Enable Input
Active LOW, resets the entire chip.
ADS1217
SBAS260B
6
www.ti.com
TIMING DIAGRAMS
CS
t3
t1
t2
t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t2
t4
t5
t6
t11
DIN
MSB
LSB
t7
t8
t9
(Command or Command and Data)
MSB(1)
LSB(1)
DOUT
NOTE: (1) Bit Order = 0.
ADS1217
Resets On
SCLK Reset Waveform
Falling Edge
t13
t13
SCLK
t12
t14
t15
t16
t17
RESET, DSYNC, PDWN
DRDY
TIMING CHARACTERISTICS
SPEC
DESCRIPTION
MIN
MAX
UNITS
t1
SCLK Period
4
tOSC Periods
3
DRDY Periods
t2
t3
t4
t5
t6
SCLK Pulse Width, HIGH and LOW
CS LOW to First SCLK Edge; Setup Time(1)
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
200
0
ns
ns
50
50
ns
ns
Delay Between Last SCLK Edge for DIN and First SCLK
Edge for DOUT
:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM
CSREG, CSRAMX, CSRAM
CSARAM, CSARAMX
50
200
1100
tOSC Periods
tOSC Periods
tOSC Periods
(2)
t7
SCLK Edge to Valid New DOUT
50
10
ns
ns
(2)
t8
SCLK Edge to DOUT, Hold Time
0
6
t9
Last SCLK Edge to DOUT Tri-State
tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10
t11
CS LOW Time After Final SCLK Edge
Final SCLK Edge of One Op Code Until First Edge SCLK
of Next Command:
0
ns
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, DSYNC, SLEEP, RDATA,
RDATAC, STOPC
CREG, CRAM
CREGA
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (Input pin, command, or SCLK pattern)
tOSC Periods
4
220
1600
7
14
16
tOSC Periods
tOSC Periods
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
t12
t13
t14
t15
t16
t17
300
500
5
550
1050
4
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
750
1250
Pulse Width
Data Not Valid
4
NOTES: (1) CS may be tied LOW. (2) Load = 20pF.
ADS1217
SBAS260B
7
www.ti.com
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA2
PGA8
PGA4
PGA2
PGA4
PGA8
PGA1
PGA1
PGA128
PGA64
PGA32
PGA128
PGA64
PGA16
PGA32
PGA16
Sinc3 Filter, BUFFER OFF
Sinc3 Filter, BUFFER ON
0
500
1000
Decimation Ratio =
1500
fMOD
2000
0
0
0
500
1000
Decimation Ratio =
1500
fMOD
2000
fDATA
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA4
PGA8
PGA2
PGA4
PGA8
PGA2
PGA1
PGA1
PGA64
PGA32
PGA16
PGA128
PGA128
PGA32
PGA64
PGA16
Sinc3 Filter, VREF = 1.25V, BUFFER OFF
Sinc3 Filter, VREF = 1.25V, BUFFER ON
500
1000
1500
2000
0
500
1000
1500
fMOD
2000
Decimation Ratio
Decimation Ratio =
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA2
PGA4
PGA8
PGA1
PGA16 PGA64
PGA32
PGA128
Sinc2 Filter
Fast Settling Filter
0
500
1000
1500
2000
500
1000
1500
fMOD
2000
fMOD
Decimation Ratio =
Decimation Ratio =
fDATA
fDATA
ADS1217
SBAS260B
8
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
COMMON-MODE REJECTION RATIO vs FREQUENCY
NOISE vs INPUT SIGNAL
130
120
110
100
90
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
80
70
60
50
40
30
20
10
0
–5
–4
–3
–2
–1
0
1
2
3
4
5
1
10
100
1k
10k
100k
V
IN (V)
Frequency of CM Signal (Hz)
OFFSET vs TEMPERATURE
POWER-SUPPLY REJECTION RATIO vs FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
140
120
100
80
PGA128
60
PGA64
40
PGA1
20
0
PGA16
–20
–40
–50
0
50
100
1
10
100
1k
10k
100k
Temperature (°C)
Frequency of Power Supply (Hz)
GAIN vs TEMPERATURE
INTEGRAL NONLINEARITY vs INPUT SIGNAL
–40°C
6
4
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
2
0
+25°C
–2
–4
–6
+85°C
–1
–50
–30
–10
10
30
50
70
90
–5
–4
–3
–2
0
1
2
3
4
5
Temperature (°C)
VIN (V)
ADS1217
SBAS260B
9
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
CURRENT vs TEMPERATURE
A/D CURRENT vs PGA
AVDD = 5V, Buffer = ON
Buffer = OFF
270
240
210
180
150
900
800
700
600
500
400
300
200
100
0
IANALOG
AVDD = 3V, Buffer = ON
Buffer = OFF
IDIGITAL
60
–60
–30
0
30
90
120
5.5
2.5
1
2
4
8
16
32
64
128
Temperature (°C)
PGA Setting
DIGITAL CURRENT
HISTOGRAM OF OUTPUT DATA
5000
4000
3000
2000
1000
0
400
350
300
250
200
150
100
50
Normal
4.91MHz
SLEEP
4.91MHz
Normal
2.45MHz
SLEEP
2.45MHz
0
2.5
3.0
3.5
4.0
4.5
5
–2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
2.0
VDD (V)
ppm of FS
VREFOUT vs LOAD CURRENT
OFFSET DAC: OFFSET vs TEMPERATURE
200
170
140
110
80
2.55
2.50
2.45
50
20
–10
–40
–70
–100
–50
–30
–10
10
30
50
70
90
–0.5
0
0.5
1.0
1.5
2.0
Temperature (°C)
VREFOUT Current Load (mA)
ADS1217
SBAS260B
10
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TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, and VREF = +2.5V, unless otherwise specified.
OFFSET DAC: GAIN vs TEMPERATURE
IDAC IOUT vs VOUT
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
1.0000
1.000
0.999
0.999
0.998
+85°C
+25°C
–40°C
–50
–30
–10
10
30
50
70
90
0
1
2
3
4
5
Temperature (°C)
VDD – VOUT (V)
IDAC NORMALIZED IOUT vs TEMPERATURE
IDAC MATCHING vs TEMPERATURE
1.010
1.005
1.000
0.995
0.990
0.985
3000
2000
1000
0
–1000
–2000
–3000
–4000
–5000
–6000
–50
–30
–10
10
30
50
70
90
–50
–30
–10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
IDAC DIFFERENTIAL NONLINEARITY
(Range = 1, RDAC = 150kΩ, VREF = 2.5V)
IDAC INTEGRAL NONLINEARITY
(Range = 1, RDAC = 150kΩ, VREF = 2.5V)
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
IDAC Code
IDAC Code
ADS1217
SBAS260B
11
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BURNOUT CURRENT SOURCES
OVERVIEW
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2µA of current.
The current source on the negative input channel sinks ap-
proximately 2µA. This allows for the detection of an open circuit
(full-scale reading) or short circuit (0V differential reading) on
the selected input differential pair.
INPUT MULTIPLEXER
The input multiplexer (mux) provides for any combination of
differential inputs to be selected on any of the input channels,
as shown in Figure 1. If channel 1 is selected as the positive
differential input channel, any other channel can be selected
as the negative differential input channel. With this method,
it is possible to have up to eight fully differential input
channels.
INPUT BUFFER
The input impedance of the ADS1217 without the buffer
is 10MΩ/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the buffer pin with
the state of the BUFFER bit in the ACR register. See Applica-
tion Report Input Currents for High-Resolution ADCs
(SBAA090) for more information.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the pins.
AIN0
IDAC1 AND IDAC2
AIN
AIN
AIN
AIN
AIN
AIN
AIN
1
2
3
4
5
6
7
AVDD
The ADS1217 has two 8-bit current output DACs that can
be controlled independently. The output current is set with
Burnout Current Source On
R
DAC, the range select bits in the ACR register, and the
8-bit digital value in the IDAC register. The output
current = (VREF/8RDAC) (2RANGE–1) (DAC CODE). With
V
REFOUT = 2.5V and RDAC = 150kΩ, the full-scale output can
AIN+
be selected to be 0.5, 1, or 2mA. The compliance voltage
range is AGND to within 1V of AVDD. When the internal
voltage reference of the ADS1217 is used, it is the refer-
ence for the IDAC. An external reference may be used for
the IDACs by disabling the internal reference and tying the
external reference input to the VREFOUT pin.
AIN–
Burnout Current Source On
PGA
AGND
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can improve the effective resolution of the A/D
converter. For instance, with a PGA of 1 on a 10V full-scale
range, the A/D converter can resolve to 2µV. With a PGA of
128 on a 80mV full-scale range, the A/D converter can resolve
to 150nV.
IDAC1
AINCOM
PGA OFFSET DAC
FIGURE 1. Input Multiplexer Configuration.
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign and
the seven LSBs provide the magnitude of the offset. Using the
ODAC does not reduce the performance of the A/D converter.
See Application Report The Offset DAC (SBAA077) for more
information.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to all
1s, the diode is connected to the input of the A/D converter.
All other channels are open. The anode of the diode is
connected to the positive input of the A/D converter, and the
cathode of the diode is connected to negative input of the
A/D converter. The output of IDAC1 is connected to the
anode to bias the diode and the cathode of the diode is also
connected to ground to complete the circuit.
MODULATOR
The modulator is a single-loop, 2nd-order system. The modu-
lator runs at a clock speed (fMOD) that is derived from the
external clock (fOSC). The frequency division is determined by
the SPEED bit in the setup register.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode. See Application Report
Measuring Temperature with the ADS1216, ADS1217, or
ADS1218 (SBAA073) for more information.
SPEED BIT
fMOD
0
1
fOSC /128
f
OSC/256
ADS1217
SBAS260B
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VOLTAGE REFERENCE INPUT
complete both an offset and gain calibration. Self-gain cali-
bration is optimized for PGA gains less than 8. When using
higher gains, system gain calibration is recommended.
The ADS1217 uses a differential voltage reference input.
The input signal is measured against the differential voltage
VREF ≡ (VREF+) – (VREF–). For AVDD = 5V, VREF is typically
2.5V. For AVDD = 3V, VREF is typically 1.25V. Due to the
sampling nature of the modulator, the reference input current
increases with higher modulator clock frequency (fMOD) and
higher PGA settings.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“zero” differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive “full-scale” differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven tDATA periods to complete.
ON-CHIP VOLTAGE REFERENCE
Calibration must be performed after power on, a change in
decimation ratio, or a change of the PGA. For operation with
a reference voltage greater than (AVDD – 1.5V), the buffer
must also be turned off during calibration.
A selectable voltage reference (1.25V or 2.5V) is available for
supplying the voltage reference input. To use, connect VREF–
to AGND and VREF+ to VREFOUT. The enabling and voltage
selection are controlled through bits REF EN and REF HI in
the setup register. The 2.5V reference requires AVDD = 5V.
When using the on-chip voltage reference, the VREFOUT pin
should be bypassed with a 0.1µF capacitor to AGND.
At the completion of calibration, the DRDY signal goes LOW,
which indicates the calibration is finished and valid data is
available. See Application Report Calibration Routine and
Register Value Generation for the ADS121x Series (SBAA099)
for more information.
VRCAP PIN
This pin provides a bypass cap for noise filtering on internal
VREF circuitry only. As this is a sensitive pin, place the
capacitor as close as possible and avoid any resistive load-
ing. The recommended capacitor is a 0.001µF ceramic cap.
If an external VREF is used, this pin can be left unconnected.
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc2, or
sinc3 filter, as shown in Figure 3. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the
fast settling filter; It will then use the sinc2 followed by the
sinc3 filter. This combines the low-noise advantage of the
sinc3 filter with the quick response of the fast settling time
filter. See Figure 4 for the frequency response of each filter.
CLOCK GENERATOR
The clock source for the ADS1217 can be provided from a
crystal, oscillator, or external clock. When the clock source is
a crystal, external capacitors must be provided to ensure start-
up and a stable clock frequency; see Figure 2 and Table I.
When using the fast setting filter, select a decimation value
set by the DEC0 and M/DEC1 registers that is evenly
divisible by four for the best gain accuracy. For example,
choose 260 rather than 261.
XIN
C1
Crystal
Adjustable Digital Filter
Sinc3
XOUT
C2
FIGURE 2. Crystal Connection.
Modulator
Output
Sinc2
Data Out
CLOCK
PART
SOURCE FREQUENCY
C1
C2
NUMBER
Fast Settling
Crystal
Crystal
Crystal
Crystal
2.4576
4.9152
4.9152
4.9152
0-20pF 0-20pF ECS, ECSD 2.45 - 32
0-20pF 0-20pF
0-20pF 0-20pF
ECS, ECSL 4.91
ECS, ECSD 4.91
FILTER SETTLING TIME
FILTER
SETTLING TIME
0-20pF 0-20pF CTS, MP 042 4M9182
(Conversion Cycles)
TABLE I. Typical Clock Sources.
Sinc3
Sinc2
Fast
3
2
1
CALIBRATION
The offset and gain errors in the ADS1217, or the complete
system, can be reduced with calibration. Internal calibration
of the ADS1217 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven tDATA periods to complete. It takes 14 tDATA periods to
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
1
2
3
4+
Fast
Sinc2
Sinc3
Sinc3
FIGURE 3. Filter Step Responses.
ADS1217
SBAS260B
13
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SINC3 FILTER RESPONSE(1)
SINC2 FILTER RESPONSE(1)
(–3dB = 0.262 • fDATA = 15.76Hz)
(–3dB = 0.318 • fDATA = 19.11Hz)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
30
60 90 120 150 180 210 240 270 300
Frequency (Hz)
0
30
60 90 120 150 180 210 240 270 300
Frequency (Hz)
FAST SETTLING FILTER RESPONSE(1)
(–3dB = 0.469 • fDATA = 28.125Hz)
0
–20
–40
–60
–80
–100
–120
0
30
60 90 120 150 180 210 240 270 300
Frequency (Hz)
NOTE: (1) fDATA = 60Hz.
FIGURE 4. Filter Frequency Responses.
DIGITAL I/O INTERFACE
back with no delay in SCLKs or toggling of CS. Make sure
to avoid glitches on SCLK as they can cause extra shifting of
the data.
The ADS1217 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as inputs.
All of the digital I/O pins are individually configurable as inputs
or outputs. They are configured through the DIR control regis-
ter. The DIR register defines whether the pin is an input or
output, and the DIO register defines the state of the digital
output. When the digital I/O are configured as inputs, DIO is
used to read the state of the pin. If the digital I/O are not used,
either 1) configure as outputs; or, 2) leave as inputs and tie to
ground, this prevents excess power dissipation.
Polarity (POL)
The serial clock polarity is specified by the POL input. When
SCLK is active HIGH, set POL HIGH. When SCLK is active
LOW, set POL LOW.
DATA READY
The DRDY output is used as a status signal to indicate when
data is ready to be read from the ADS1217. DRDY goes LOW
when new data is available. It is reset HIGH when a read
operation from the data register is complete. It also goes HIGH
prior to the updating of the output register to indicate when not
to read from the device to ensure that a data read is not
attempted while the register is being updated.
SERIAL PERIPHERAL INTERFACE
The Serial Peripheral Interface (SPI) allows a controller to
communicate synchronously with the ADS1217. The ADS1217
operates in slave only mode.
Chip Select (CS
)
DSYNC OPERATION
The chip select (CS) input of the ADS1217 must be exter-
nally asserted before a master device can exchange data
with the ADS1217. CS must be LOW for the duration of the
transaction. CS can be tied low.
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the DSYNC pin or the DSYNC
command. When the DSYNC pin is used, the filter counter is
reset on the falling edge of DSYNC. The modulator is held in
reset until DSYNC is taken HIGH. Synchronization occurs on
the next rising edge of the system clock after DSYNC is
taken HIGH.
Serial Clock (SCLK)
SCLK, a Schmitt Trigger input, clocks data transfer on the DIN
input and DOUT output. When transferring data to or from the
ADS1217, multiple bits of data may be transferred back-to-
ADS1217
SBAS260B
14
www.ti.com
When the DSYNC command is sent, the filter counter is reset
on the edge of the last SCLK on the DSYNC command. The
modulator is held in reset until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command. After a DSYNC operation, DRDY is held HIGH
until valid data is ready.
Configuration
Registers
16 bytes
RAM
128 Bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
DIR
Bank 0
16 bytes
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
RESET
There are three methods to reset the ADS1217: the RESET
input, the RESET command, and a special SCLK input pat-
tern. When using the RESET input, take it LOW to force a
reset. Make sure to follow the minimum pulse width timing
specifications before taking the RESET input back high. Also,
avoid glitches on the RESET input as these may cause
accidental resets. The RESET command takes effect after all
8 bits have been shifted into DIN. Afterwards, the reset
releases automatically. The ADS1217 can also be reset with
a special pattern on SCLK, see the Timing Diagram. Reset
occurs on the falling edge of the last SCLK edge in the pattern
(for POL = 0). Afterwards, the reset releases automatically.
Bank 2
16 bytes
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotonically.
Bank 7
16 bytes
MEMORY
Two types of memory are used on the ADS1217: registers
and RAM. 16 registers directly control the various functions
(PGA, DAC value, Decimation Ratio, etc.) and can be directly
read or written. Collectively, the registers contain all the
information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio,
etc. Additional registers, such as output data, are accessed
through dedicated instructions.
FIGURE 5. Memory Organization.
The RAM provides eight “banks”, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively with-
out having to address each bank individually. For example,
if you were currently accessing bank 0 at offset 0FH (the last
location of bank 0), the next access would be bank 1 and
offset 00H. Any access after bank 7 and offset 0FH will wrap
around to bank 0 and Offset 00H.
REGISTER BANK TOPOLOGY
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers;
that is, the RAM can be used as general-purpose RAM.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of
bank and offset addressing. Looking at linear and bank
addressing syntax, we have the following comparison: in the
linear memory map, the address 14H is equivalent to bank
1 and offset 04H. Simply stated, the most significant four bits
represent the bank, and the least significant four bits repre-
sent the offset. The offset is equivalent to the register
address for that bank of memory.
The ADS1217 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations—one per input channel. In order
to facilitate this type of usage, eight separate register banks
are available. Therefore, each configuration could be written
once and recalled as needed without having to serially
retransmit all the configuration data. Checksum commands
are also included, which can be used to verify the integrity of
RAM.
ADS1217
SBAS260B
15
www.ti.com
REGISTER MAP
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
SETUP
MUX
ID
ID
ID
SPEED
PSEL0
REF EN
NSEL3
REF HI
NSEL2
PGA2
BUF EN
NSEL1
PGA1
BIT ORDER
NSEL0
PGA0
PSEL3
BOCS
PSEL2
IDAC2R1
IDAC1_6
IDAC2_6
OSET_6
DIO_6
PSEL1
IDAC2R0
IDAC1_5
IDAC2_5
OSET_5
DIO_5
ACR
IDAC1R1
IDAC1_4
IDAC2_4
OSET_4
DIO_4
IDAC1R0
IDAC1_3
IDAC2_3
OSET_3
DIO_3
IDAC1
IDAC2
ODAC
DIO
IDAC1_7
IDAC2_7
SIGN
IDAC1_2
IDAC2_2
OSET_2
DIO_2
IDAC1_1
IDAC2_1
OSET_1
DIO_1
IDAC1_0
IDAC2_0
OSET_0
DIO_0
DIO_7
DIR_7
DIR
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
DEC07
DRDY
DEC06
U/B
DEC05
SMODE1
OCR05
OCR13
OCR21
FSR05
FSR13
FSR21
DEC04
SMODE0
OCR04
OCR12
OCR20
FSR04
DEC03
Reserved
OCR03
OCR11
OCR19
FSR03
DEC02
DEC10
OCR02
OCR10
OCR18
FSR02
FSR10
FSR18
DEC01
DEC09
OCR01
OCR09
OCR17
FSR01
FSR09
FSR17
DEC00
DEC08
OCR00
OCR08
OCR16
FSR00
OCR07
OCR15
OCR23
FSR07
FSR15
FSR23
OCR06
OCR14
OCR22
FSR06
FSR14
FSR22
FSR12
FSR11
FSR08
FSR20
FSR19
FSR16
TABLE II. Registers.
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iii01110
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
NSEL1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL0
ID
ID
ID
SPEED
REF EN
REF HI
BUF EN BIT ORDER
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
bit 7-5 Factory Programmed Bits
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1s)
1111 = Temperature Sensor Diode
bit 4
bit 3
bit 2
bit 1
bit 0
SPEED: Modulator Clock Speed
0 : fMOD = fOSC/128 (default)
1 : fMOD = fOSC/256
REF EN: Internal Voltage Reference Enable
0 = Internal Voltage Reference Disabled
1 = Internal Voltage Reference Enabled (default)
REF HI: Internal Reference Voltage Select
0 = Internal Reference Voltage = 1.25V
1 = Internal Reference Voltage = 2.5V (default)
BUF EN: Buffer Enable
0 = Buffer Disabled
1 = Buffer Enabled (default)
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel
Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
0111 = AIN7
BIT ORDER: Set Order Bits are Transmitted
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted into the part most significant
bit first. Data is always shifted out of the part most
significant byte first. This configuration bit only con-
trols the bit order within the byte of data that is
shifted out.
1xxx = AINCOM (except when all bits are 1s)
1111 = Temperature Sensor Diode
ADS1217
SBAS260B
16
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ACR (Address 02H) Analog Control Register
ODAC (Address 05H) Offset DAC Setting
Reset Value = 00H
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BOCS
IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0
PGA2
PGA1
PGA0
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
bit 7
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 7
Offset Sign
0 = Positive
1 = Negative
VREF
VREF
PGA
Code
2RANGE−1 DAC Code
(
)
)
•
(
IDAC Current =
bit 6-0 Offset =
8RDAC
127
bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for
NOTE: The offset must be used after calibration or the
calibration will notify the effects.
IDAC2
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
DIO (Address 06H) Digital I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
IDAC1
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
A value written to this register will appear on the digital
I/O pins if the pin is configured as an output in the DIR
register. Reading this register will return the value of the
digital I/O pins.
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier
Gain Selection
000 = 1 (default)
001 = 2
DIR (Address 07H) Direction control for digital I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
010 = 4
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
011 = 8
100 = 16
101 = 32
Each bit controls whether the Digital I/O pin is an output
(= 0) or input (= 1). The default power-up state is as inputs.
110 = 64
111 = 128
DEC0 (Address 08H) Decimation Register
(Least Significant 8 bits)
IDAC1 (Address 03H) Current DAC 1
Reset Value = 80H
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
The decimation value is defined with 11 bits for a range of 20
to 2047. This register is the least significant 8 bits. The 3
most significant bits are contained in the M/DEC1 register.
The default data rate is 10Hz with a 2.4576MHz crystal.
The DAC code bits set the output of DAC1 from 0 to full-
scale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC1 range bits in the ACR register.
IDAC2 (Address 04H) Current DAC 2
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
The DAC code bits set the output of DAC2 from 0 to full-
scale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC2 range bits in the ACR register.
ADS1217
SBAS260B
17
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M/DEC1 (Address 09H) Mode and Decimation Register
Reset Value = 07H
OCR2 (Address 0CH) Offset Calibration Coefficient
(Most Significant Byte)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset Value = 00H
DRDY
U/B
SMODE1 SMODE0 Reserved DEC10
DEC09
DEC08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
FSR0 (Address 0DH) Full-Scale Register
(Least Significant Byte)
Reset Value = 24H
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
U/B
ANALOG INPUT
DIGITAL OUTPUT
+FS
Zero
–FS
+FS
Zero
–FS
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
0
FSR1 (Address 0EH) Full-Scale Register
(Middle Byte)
Reset Value = 90H
1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR15
FSR14
FSR13
FSR12
FSR011
FSR10
FSR09
FSR08
bit 5-4 SMODE1: SMODE0: Settling Mode
00 = Auto (default)
01 = Fast Settling filter
10 = Sinc2 filter
11 = Sinc3 filter
FSR2 (Address 0FH) Full-Scale Register
(Most Significant Byte)
Reset Value = 67H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of
the Decimation Value
FSR23
FSR22
FSR21
FSR20
FSR019
FSR18
FSR17
FSR16
OCR0 (Address 0AH) Offset Calibration Coefficient
(Least Significant Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR1 (Address 0BH) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
ADS1217
SBAS260B
18
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Operands:
COMMAND DEFINITIONS
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
The commands listed below control the operation of the
ADS1217. Some of the commands are stand-alone com-
mands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four fOSC
cycles before the data is ready (e.g., RDATA).
a = RAM bank address (0 to 7)
COMMANDS
DESCRIPTION
COMMAND BYTE
2ND COMMAND BYTE
RDATA
RDATAC
STOPC
RREG
RRAM
CREG
CREGA
WREG
WRAM
CRAM
CSRAMX
CSARAMX
CSREG
CSRAM
CSARAM
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
WAKEUP
DSYNC
Read Data
0000 0001 (01H)
0000 0011 (03H)
0000 1111 (0FH)
0001 r r r r (1xH)
0010 0aaa (2xH)
0100 0aaa (4xH)
0100 1000 (48H)
0101 r r r r (5xH)
0110 0aaa (6xH)
1100 0aaa (CxH)
1101 0aaa (DxH)
1101 1000 (D8H)
1101 1111 (DFH)
1110 0aaa (ExH)
1110 1000 (E8H)
1111 0000 (F0H)
1111 0001 (F1H)
1111 0010 (F2H)
1111 0011 (F3H)
1111 0100 (F4H)
1111 1011 (FBH)
1111 1100 (FCH)
1111 1101 (FDH)
1111 1110 (FEH)
—
—
—
Read Data Continuously
Stop Read Data Continuously
Read from REG Bank rrrr
Read from RAM Bank aaa
Copy REGs to RAM Bank aaa
Copy REGS to all RAM Banks
Write to REG rrrr
Write to RAM Bank aaa
Copy RAM Bank aaa to REG
Calc RAM Bank aaa Checksum
Calc all RAM Bank Checksum
Calc REG Checksum
Calc RAM Bank aaa Checksum
Calc all RAM Banks Checksum
Self Cal Offset and Gain
Self Cal Offset
Self Cal Gain
Sys Cal Offset
Sys Cal Gain
Wake Up From Sleep Mode
Sync DRDY
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SLEEP
RESET
Put in Sleep Mode
Reset to Power-Up Values
NOTE: (1) The data received by the A/D converter is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATA
Read Data
RDATAC
Read Data Continuous
Description: Read a single 24-bit ADC conversion result. On
completion of read back, DRDY goes HIGH.
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands: None
Bytes:
1
Encoding: 0000 0001
Operands: None
Data Transfer Sequence:
Bytes:
1
Encoding: 0000 0011
DRDY
Data Transfer Sequence:
Command terminated when uuuu uuuu equals STOPC
or RESET.
0000 0001
• • •(1)
xxxx xxxx
MSB
xxxx xxxx
Mid-Byte
xxxx xxxx
LSB
DIN
DOUT
DIN
0000 0011
• • •(1)
uuuu uuuu
MSB
uuuu uuuu
Mid-Byte
uuuu uuuu
LSB
• • •
DOUT
DRDY
DIN
• • •
uuuu uuuu
uuuu uuuu
uuuu uuuu
• • •
DOUT
MSB
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
ADS1217
SBAS260B
19
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STOPC
Stop Continuous
CREG
Copy Registers to RAM Bank
Description: Ends the continuous data output mode.
Operands: None
Description: Copy the 16 control registers to the RAM bank
specified in the op code. Refer to timing specifications for
command execution time.
Bytes:
1
Operands:
Bytes:
a
1
Encoding: 0000 1111
Data Transfer Sequence:
Encoding: 0100 0aaa
Data Transfer Sequence:
Copy Register Values to RAM Bank 3
0000 1111
DIN
0100 0011
DIN
RREG
Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte.
Ifthecountexceedstheremainingregisters,theaddresseswill
wrap back to the beginning.
CREGA
Copy Registers to All RAM Banks
Description: Duplicate the 16 control registers to all the RAM
banks. Refer to timing specifications for command execution
time.
Operands: r, n
Operands: None
Bytes:
2
Bytes:
1
Encoding: 0001 rrrr xxxx nnnn
Encoding: 0100 1000
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
Data Transfer Sequence:
0100 1000
DIN
0001 0001
0000 0001
• • •(1)
xxxx xxxx
MUX
xxxx xxxx
ACR
DIN
DOUT
WREG
Write to Register
Description: Write to the registers starting with the register
specifiedaspartoftheinstruction.Thenumberofregistersthat
will be written is one plus the value of the second byte.
RRAM
Read from RAM
Description: Up to 128 bytes can be read from RAM starting
at the bank specified in the op code. All reads start at the
address for the beginning of the RAM bank. The number of
bytes to read will be one plus the value of the second byte.
Operands: r, n
Bytes:
2
Encoding: 0101 rrrr xxxx nnnn
Data Transfer Sequence:
Write Two Registers Starting from 06H (DIO)
Operands: a, n
Bytes:
2
Encoding: 0010 0aaa xnnn nnnn
Data Transfer Sequence:
DIN
0101 0110
xxxx 0001
Data for DIO
Data for DIR
Read Two RAM Locations Starting from 20H
0010 0010
x000 0001
• • •(1)
xxxx xxxx
xxxx xxxx
DIN
RAM Data
20H
RAM Data
21H
DOUT
NOTE: (1) For wait time, refer to timing specification.
ADS1217
SBAS260B
20
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WRAM
Write to RAM
Calculate the Checksum
for all RAM Banks
CSARAMX
Description: Write up to 128 RAM locations starting at the
beginning of the RAM bank specified as part of the instruction.
The number of bytes written is RAM is one plus the value of the
second byte.
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY, and DIO bits are masked so they are
not included in the checksum.
Operands: a, n
Operands: None
Bytes:
2
Bytes:
1
Encoding: 0110 0aaa xnnn nnnn
Encoding: 1101 1000
Data Transfer Sequence:
Write to Two RAM Locations starting from 10H
Data Transfer Sequence:
Data for
10H
Data for
11H
DIN
0110 0001
x000 0001
1101 1000
• • •(1)
xxxx xxxx
DIN
Checksum
DOUT
CRAM
Copy RAM Bank to Registers
Description: Copy the selected RAM Bank to the Configura-
tion Registers. This will overwrite all of the registers with the
data from the RAM bank.
Calculate the Checksum
of Registers
CSREG
Operands:
Bytes:
a
1
Description: Calculate the checksum of all the registers. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Encoding: 1100 0aaa
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
Operands: None
Bytes:
1
Encoding: 1101 1111
1100 0000
DIN
Data Transfer Sequence:
CSRAMX
Calculate RAM Bank Checksum
1101 1111
• • •(1)
xxxx xxxx
DIN
Description: Calculate the checksum of the selected RAM
Bank.Thechecksumiscalculatedasasumofallthebyteswith
the carry ignored. The ID, DRDY, and DIO bits are masked so
they are not included in the checksum.
Checksum
DOUT
Operands:
Bytes:
a
1
CSRAM
Calculate RAM Bank Checksum
Description: Calculate the checksum of the selected RAM
Bank.Thechecksumiscalculatedasasumofallthebyteswith
the carry ignored. All bits are included in the checksum
calculation, there is no masking of bits.
Encoding: 1101 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
Operands:
Bytes:
a
1
1101 0011
• • •(1)
xxxx xxxx
DIN
Encoding: 1110 0aaa
Checksum
DOUT
Data Transfer Sequence:
Calculate Checksum for RAM Bank 2
1110 0010
• • •(1)
xxxx xxxx
DIN
Checksum
DOUT
NOTE: (1) For wait time, refer to timing specification.
ADS1217
SBAS260B
21
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Calculate Checksum
for all RAM Banks
SELFGCAL
Gain Self Calibration
CSARAM
Description: Starts the process of self-calibration for gain.
TheFull-ScaleRegister(FSR)isupdatedwithnewvaluesafter
this operation.
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored.Allbitsareincludedinthechecksumcalculation,there
is no masking of bits.
Operands: None
Bytes:
1
Operands: None
Encoding: 1111 0010
Bytes:
1
Data Transfer Sequence:
Encoding: 1110 1000
Data Transfer Sequence:
1111 0010
DIN
1110 1000
• • •(1)
xxxx xxxx
DIN
SYSOCAL
System Offset Calibration
Checksum
DOUT
Description: Starts the system offset calibration process. For
a system offset calibration the input should be set to 0V
differential, and the ADS1217 computes the OCR register
value that will compensate for offset errors. The Offset Control
Register (OCR) is updated after this operation.
SELFCAL
Offset and Gain Self Calibration
Description: Starts the process of self calibration. The Offset
Control Register (OCR) and the Full-Scale Register (FSR) are
updated with new values after this operation.
Operands: None
Bytes:
1
Encoding: 1111 0011
Operands: None
Data Transfer Sequence:
Bytes:
1
Encoding: 1111 0000
Data Transfer Sequence:
1111 0011
DIN
1111 0000
DIN
SYSGCAL
System Gain Calibration
Description: Starts the system gain calibration process. For
a system gain calibration, the differential input should be set to
the reference voltage and the ADS1217 computes the FSR
register value that will compensate for gain errors. The FSR is
updated after this operation.
SELFOCAL
Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Control Register (OCR) is updated after this opera-
tion.
Operands: None
Operands: None
Bytes:
1
Bytes:
1
Encoding: 1111 0100
Encoding: 1111 0001
Data Transfer Sequence:
Data Transfer Sequence:
1111 0100
DIN
1111 0001
DIN
NOTE: (1) For wait time, refer to timing specification.
ADS1217
SBAS260B
22
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DSYNC
Sync DRDY
WAKEUP Wakeup From Sleep Mode
Description: Synchronizes the ADS1217 to the serial clock
edge.
Description: Use this command to wake up from sleep mode.
Operands: None
Operands: None
Bytes:
1
Bytes:
1
Encoding: 1111 1011
Encoding: 1111 1100
Data Transfer Sequence:
Data Transfer Sequence:
1111 1011
DIN
1111 1100
DIN
RESET
Reset to Power-Up Values
SLEEP
Sleep Mode
Description: Restore the registers to their power-up values.
This command will also stop the Read Continuous mode. It
does not affect the contents of RAM.
Description: Puts the ADS1217 into a low power sleep mode.
SCLK must be inactive while in sleep mode. To exit this mode,
issue the WAKEUP command.
Operands: None
Operands: None
Bytes:
1
Bytes:
1
Encoding: 1111 1110
Encoding: 1111 1101
Data Transfer Sequence:
Data Transfer Sequence:
1111 1110
DIN
1111 1101
DIN
LSB
MSB
0000
0001
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
x
rdata
x
rdatac
x
x
x
x
x
x
x
x
x
x
x
stopc
rreg
0
rreg
1
rreg
2
rreg
3
rreg
4
rreg
5
rreg
6
rreg
7
rreg
8
rreg
9
rreg
A
rreg
B
rreg
C
rreg
D
rreg
E
rreg
F
0010
rram
0
rram
1
rram
2
rram
3
rram
4
rram
5
rram
6
rram
7
x
x
x
x
x
x
x
x
0011
0100
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
creg
0
creg
1
creg
2
creg
3
creg
4
creg
5
creg
6
creg
7
crega
0101
0110
wreg
0
wreg
1
wreg
2
wreg
3
wreg
4
wreg
5
wreg
6
wreg
7
wreg
8
wreg
9
wreg
A
wreg
B
wreg
C
wreg
D
wreg
E
wreg
F
wram
0
wram
1
wram
2
wram
3
wram
4
wram
5
wram
6
wram
7
x
x
x
x
x
x
x
x
0111
1000
1001
1010
1011
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1100 cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7
1101 csramx csramx csramx csramx csramx csramx csramx csramx
csa
0
1
2
3
4
5
6
7
ramx
csreg
x
1110
1111
cs
cs
cs
ram2
cs
cs
cs
cs
cs
ram 7
csa
ram
x
x
x
x
x
x
x
x
ram 0 ram 1
ram 3 ram 4
ram 5 ram 6
self
cal
self
ocal
self
gcal
sys
ocal
sys
gcal
x
x
x
x
wakeup dsync
sleep
reset
x
x = Reserved
TABLE IV. Command Map.
ADS1217
SBAS260B
23
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DEFINITION OF TERMS
BITS rms
BIPOLAR Vrms
UNIPOLAR Vrms
Analog Input Voltage—the voltage at any one analog input
4VREF
2VREF
relative to AGND.
PGA
6.02 •ENOB
PGA
6.02 •ENOB
Analog Input Differential Voltage—given by the following
20
20
10
10
equation: (AIN+) – (AIN–). Thus, a positive digital output is
24
22
20
18
16
14
12
596nV
2.38µV
9.54µV
38.1µV
153µV
610µV
2.44mV
298nV
1.19µV
4.77µV
19.1µV
76.4µV
305µV
1.22mV
produced whenever the analog input differential voltage is
positive, while a negative digital output is produced whenever
the differential is negative.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2 • 2.5V. The negative full-scale output is produced
when the differential is 2 • (–2.5V). In each case, the actual
input voltages must remain within the AGND to AVDD range.
f
DATA—the frequency of the digital output data produced by
the ADS1217, fDATA is also referred to as the Data Rate.
Conversion Cycle—the term conversion cycle usually refers
to a discrete A/D conversion operation, such as that per-
formed by a successive approximation converter. As used
here, a conversion cycle refers to the tDATA time period.
However, each digital output is actually based on the modu-
lator results from several tDATA time periods.
fMOD
fOSC
fDATA
=
=
DecimationRatio
mfactor • DecimationRatio
fMOD—the frequency or speed at which the modulator of the
ADS1217 is running. This depends on the SPEED bit as
shown below:
FILTER SETTING
Fast Settling
Sinc2
MODULATOR RESULTS
1 tDATA Time Period
2 tDATA Time Period
3 tDATA Time Period
SPEED BIT
fMOD
0
1
fOSC/128
OSC/256
f
Sinc3
fOSC—the frequency of the crystal input signal at the XIN input
of the ADS1217.
Data Rate—the rate at which conversions are completed.
See definition for fDATA
.
fSAMP—the frequency, or switching speed, of the input sam-
pling capacitor. The value is given by one of the following
equations:
Decimation Ratio—defines the ratio between the output of
the modulator and the output Data Rate. Valid values for the
Decimation Ratio are from 20 to 2047. Larger Decimation
Ratios will have lower noise.
PGA SETTING
SAMPLING FREQUENCY
Effective Resolution—the effective resolution of the
ADS1217 in a particular configuration can be expressed in
two different units: bits rms (referenced to output) and Vrms
(referenced to input). Computed directly from the converter’s
output data, each is a statistical calculation. The conversion
from one to the other is shown below.
fOSC
1, 2, 4, 8
f SAMP
=
=
mfactor
2fOSC
8
16
fSAMP
mfactor
8fOSC
fSAMP
fSAMP
fSAMP
=
=
=
mfactor
16fOSC
32
Effective number of bits (ENOB) or effective resolution is
commonly used to define the usable resolution of the
A/D converter. It is calculated from empirical data taken
directly from the device. It is typically determined by applying
a fixed known signal source to the analog input and comput-
ing the standard deviation of the data sample set. The rms
noise defines the ±σ interval about the sample mean.
mfactor
16fOSC
64, 128
mfactor
Filter Selection—the ADS1217 uses a (sinx/x) filter or sinc
filter. There are three different sinc filters that can be se-
lected. A fast settling filter will settle in one tDATA cycle. The
sinc2 filter will settle in two cycles and have lower noise. The
sinc3 will achieve lowest noise and higher number of effective
bits, but requires three cycles to settle. The ADS1217 will
operate with any one of these filters, or it can operate in an
auto mode, where it will first select the fast settling filter after
a new channel is selected and will then switch to sinc2 for one
reading, followed by sinc3 from then on.
The data from the A/D converter is output as codes, which
then can be easily converted to other units, such as ppm or
volts. The equations and table below show the relationship
between bits or codes, ppm, and volts.
–20log(ppm)
ENOB =
6.02
ADS1217
SBAS260B
24
www.ti.com
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1217 is defined as the “input”,
which produces the positive full-scale digital output minus the
“input”, which produces the negative full-scale digital output.
The full-scale range changes with gain setting, see Table V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
Full − Scale Range
LSB Weight =
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: 2 • [1.25V (positive full-scale) minus –1.25V (nega-
tive full-scale)] = 5V.
2N
where N is the number of bits in the digital output.
tDATA—the inverse of fDATA, or the period between each data
output.
5V SUPPLY ANALOG INPUT(1)
DIFFERENTIAL
GENERAL EQUATIONS
PGA OFFSET
RANGE
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
PGA SHIFT
RANGE
GAIN SETTING
FULL-SCALE RANGE INPUT VOLTAGES(2)
4VREF
PGA
±2VREF
1
2
10V
5V
±5V
±2.5
±VREF
PGA
PGA
±2.5V
±1.25V
4
2.5V
±1.25V
±0.625V
8
1.25V
±0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
16
32
64
128
0.625V
312.5mV
156.25mV
78.125mV
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
NOTES: (1) With a 2.5V reference. (2) The ADS1217 allows common-mode voltage as long as the absolute input voltage on AIN+ or AIN– does not go below
AGND or above AVDD
.
TABLE V. Full-Scale Range versus PGA Setting.
ADS1217
SBAS260B
25
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Oct-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS1217IPFBR
ADS1217IPFBT
ACTIVE
ACTIVE
TQFP
TQFP
PFB
PFB
48
48
2000
250
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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相关型号：
ADS1218Y/250G4
24-Bit, 780SPS ADC w/ Flash Memory, 8 Ch, VREF, Buffer, 2 IDACs, Serial Out, Digital I/O, Low Power 48-TQFP -40 to 85
TI
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