ADS1218Y/250 [BB]
8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory; 8通道，24位模拟数字转换器与FLASH存储器
| 型号： | ADS1218Y/250 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory |
| 文件： | 总30页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS1218
ADS1218
SBAS187 – SEPTEMBER 2001
8-Channel, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
with FLASH Memory
DESCRIPTION
FEATURES
● 24 BITS NO MISSING CODES
● 0.0015% INL
The ADS1218 is a precision, wide dynamic range, delta-sigma, Analog-to-
Digital(A/D)converterwith24-bitresolutionandFLASHmemoryoperating
from 2.7V to 5.25V supplies. The delta-sigma, A/D converter provides up to
24 bits of no missing code performance and effective resolution of 22 bits.
● 22 BITS EFFECTIVE RESOLUTION
(PGA = 1), 19 BITS (PGA = 128)
The eight input channels are multiplexed. Internal buffering can be selected
to provide a very high input impedance for direct connection to transducers
or low-level voltage signals. Burn out current sources are provided that allow
for the detection of an open or shorted sensor. An 8-bit Digital-to-Analog (D/
A) converter provides an offset correction with a range of 50% of the FSR
(Full-Scale Range).
● 4K BYTES OF FLASH MEMORY
PROGRAMMABLE FROM 2.7V TO 5.25V
● PGA FROM 1 TO 128
● SINGLE CYCLE SETTLING MODE
● PROGRAMMABLE DATA OUTPUT RATES
UP TO 1kHz
The PGA (Programmable Gain Amplifier) provides selectable gains of 1 to
128 with an effective resolution of 19 bits at a gain of 128. The A/D
conversion is accomplished with a second-order delta-sigma modulator and
programmable sinc filter. The reference input is differential and can be used
for ratiometric conversion. The on-board current DACs (Digital-to-Analog
Converters) operate independently with the maximum current set by an
external resistor.
●
PRECISION ON-CHIP 1.25V/2.5V REFERENCE:
ACCURACY: 0.2%
DRIFT: 5ppm/°C
● EXTERNAL DIFFERENTIAL REFERENCE
OF 0.1V TO 2.5V
● ON-CHIP CALIBRATION
● PIN COMPATIBLE WITH ADS1216
● SPI™ COMPATIBLE
The serial interface is SPI compatible. Eight bits of digital I/O are also provided
thatcanbeusedforinputoroutput. TheADS1218isdesignedforhigh-resolution
measurement applications in smart transmitters, industrial process control, weight
scales, chromatography, and portable instrumentation.
● 2.7V TO 5.25V
● < 1mW POWER CONSUMPTION
AGND AVDD
RDAC
VREFOUT
VRCAP
VREF+
VREF–
XIN
XOUT
8-Bit
IDAC
IDAC2
IDAC1
APPLICATIONS
Clock Generator
1.25V or
2.5V
Reference
8-Bit
IDAC
● INDUSTRIAL PROCESS CONTROL
● LIQUID/GAS CHROMATOGRAPHY
● BLOOD ANALYSIS
AVDD
2µA
Offset
DAC
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTATION
● WEIGHT SCALES
AIN
AIN
0
1
A = 1:128
PGA
Registers
RAM
IN+
AIN2
Program-
mable
Digital
Filter
2nd-Order
Modulator
AIN
AIN
AIN
AIN
AIN
3
4
5
6
7
MUX
+
Controller
BUF
IN–
● PRESSURE TRANSDUCERS
4K Bytes
FLASH
WREN
POL
SPI is a registered trademark of Motorola.
AINCOM
SCLK
DIN
Serial Interface
RESET DRDY
2µA
Digital I/O
Interface
DOUT
AGND
CS
DVDD
DGND BUFEN
D0 ... D7
PDWN DSYNC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments
recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation
procedures can cause damage.
AVDD to AGND ...................................................................... –0.3V to +6V
DVDD to DGND ...................................................................... –0.3V to +6V
Input Current ............................................................... 100mA, Momentary
Input Current ................................................................. 10mA, Continuous
A
IN ................................................................... GND –0.5V to AVDD + 0.5V
AVDD to DVDD ........................................................................... –6V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
Digital Input Voltage to GND .................................... –0.3V to DVDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to DVDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –60°C to +100°C
Lead Temperature (soldering, 10s) .............................................. +300°C
Electrostatic discharge can cause damage ranging from perfor-
mance degradation to complete device failure. Texas Instruments
recommends that all integrated circuits be handled and stored using
appropriate ESD protection methods.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
SPECIFIED
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS1218Y
TQFP-48
PFB
–40°C to +85°C
ADS1218Y
ADS1218Y/250
ADS1218Y/2K
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “ADS1218Y/2K” will get a single 2000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS: AVDD = 5V
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA = 10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM
)
Analog Input Range
Buffer OFF
Buffer ON
(In+) – (In–), See Block Diagram
Buffer OFF
AGND – 0.1
AGND + 0.05
AVDD + 0.1
AVDD – 1.5
±VREF /PGA
V
V
V
MΩ
nA
Full-Scale Input Voltage Range
Differential Input Impedance
Input Current
5/PGA
0.5
Buffer ON
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
–3dB
–3dB
–3dB
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Hz
Hz
Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User Selectable Gain Ranges
1
128
9
5
2
pF
pA
µA
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
±VREF /(2 • PGA)
V
Bits
%
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
±10
1
ppm/°C
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Non-Linearity
Offset Error(1)
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
24
Bits
Bits
% of FS
ppm of FS
sinc3
End Point Fit
Before Calibration
24
±0.0015
7.5
0.02
0.005
0.5
ppm of FS/°C
After Calibration
%
ppm/°C
dB
at DC
100
f
CM = 60Hz, fDATA = 10Hz
130
120
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 50Hz
SIG = 60Hz, fDATA = 60Hz
dB
Output Noise
Power-Supply Rejection
See Typical Characteristics
95
(2)
at DC, dB = –20 log(∆VOUT /∆VDD
)
80
dB
ADS1218
2
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 5V (Cont.)
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 150kΩ, fDATA =10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE REFERENCE INPUT
Reference Input Range
VREF
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–)
at DC
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 2.5V
0
0.1
AVDD
2.6
V
V
dB
dB
µA
2.5
120
120
1.3
ON-CHIP VOLTAGE REFERENCE
Output Voltage
REF HI = 1 at 25°C
2.495
2.50
1.25
2.505
V
V
REF HI = 0
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
Drift
Noise
Output Impedance
Startup Time
8
50
Indefinite
mA
µA
Sink or Source
5
10
3
ppm/°C
µVp-p
Ω
BW = 0.1Hz to 100Hz
Sourcing 100µA
50
µs
IDAC
Full-Scale Output Current
RDAC = 150kΩ, Range = 1
RDAC = 150kΩ, Range = 2
RDAC = 150kΩ, Range = 3
RDAC = 15kΩ, Range = 3
RDAC = 10kΩ
0.5
1
2
20
mA
mA
mA
mA
Maximum Short-Circuit Current Duration
Indefinite
RDAC = 0Ω
10
Minutes
Monotonicity
RDAC = 150kΩ
8
0
Bits
V
Compliance Voltage
Output Impedance
PSRR
Absolute Error
Absolute Drift
Mismatch Error
Mismatch Drift
AVDD – 1
see Typical Characteristics
VOUT = AVDD /2
Individual IDAC
Individual IDAC
400
5
75
0.25
15
ppm/V
%
ppm/°C
%
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
ppm/°C
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AVDD
4.75
5.25
V
Analog Current (IADC + IVREF + IDAC
ADC Current (IADC
)
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
1
nA
µA
µA
µA
µA
µA
µA
)
175
500
250
900
250
480
275
750
350
1375
375
675
VREF Current (IVREF
)
IDAC Current (IDAC
)
Excludes Load Current
Digital Current
Normal Mode, DVDD = 5V
SLEEP Mode, DVDD = 5V
Read Data Continuous Mode, DVDD = 5V
PDWN= LOW
180
150
230
1
275
µA
µA
µA
nA
Power Dissipation
PGA = 1, Buffer OFF, REFEN = 0,
IDACS OFF, DVDD = 5V
1.8
2.8
mW
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) Calibration can minimize these errors. (2) ∆ VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
ADS1218
3
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 3V
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA=10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (AIN0 – AIN7, AINCOM
)
Analog Input Range
Buffer OFF
Buffer ON
(In+) – (In–) See Block Diagram
Buffer OFF
AGND – 0.1
AGND + 0.05
AVDD + 0.1
AVDD – 1.5
±VREF /PGA
V
V
V
MΩ
nA
Full-Scale Input Voltage Range
Input Impedance
Input Current
5/PGA
0.5
Buffer ON
Bandwidth
Fast Settling Filter
Sinc2 Filter
Sinc3 Filter
–3dB
–3dB
–3dB
0.469 • fDATA
0.318 • fDATA
0.262 • fDATA
Hz
Hz
Hz
Programmable Gain Amplifier
Input Capacitance
Input Leakage Current
Burnout Current Sources
User Selectable Gain Ranges
1
128
9
5
2
pF
pA
µA
Modulator OFF, T = 25°C
OFFSET DAC
Offset DAC Range
±VREF /(2 • PGA)
V
Bits
%
Offset DAC Monotonicity
Offset DAC Gain Error
Offset DAC Gain Error Drift
8
±10
2
ppm/°C
SYSTEM PERFORMANCE
Resolution
24
Bits
No Missing Codes
Integral Non-Linearity
Offset Error(1)
24
±0.0015
Bits
% of FS
ppm of FS
ppm of FS/°C
%
ppm/°C
dB
End Point Fit
Before Calibration
15
0.04
0.010
1.0
Offset Drift(1)
Gain Error
Gain Error Drift(1)
Common-Mode Rejection
After Calibration
at DC
100
f
CM = 60Hz, fDATA = 10Hz
130
120
120
100
100
dB
dB
dB
dB
fCM = 50Hz, fDATA = 50Hz
fCM = 60Hz, fDATA = 60Hz
Normal-Mode Rejection
f
f
SIG = 50Hz, fDATA = 50Hz
SIG = 60Hz, fDATA = 60Hz
dB
Output Noise
Power-Supply Rejection
see Typical Characteristics
90
(2)
at DC, dB = –20 log(∆VOUT /∆VDD
)
75
dB
VOLTAGE REFERENCE INPUT
Reference Input Range
VREF
Common-Mode Rejection
Common-Mode Rejection
Bias Current(3)
REF IN+, REF IN–
VREF ≡ (REF IN+) – (REF IN–)
at DC
fVREFCM = 60Hz, fDATA = 60Hz
VREF = 1.25V
0
0.1
AVDD
1.25
V
V
dB
dB
µA
120
120
0.65
ON-CHIP VOLTAGE REFERENCE
Output Voltage
REF HI = 0 at 25°C
1.245
1.25
1.255
V
Short-Circuit Current Source
Short-Circuit Current Sink
Short-Circuit Duration
Drift
Noise
Output Impedance
Startup Time
3
50
Indefinite
mA
µA
Sink or Source
5
10
3
ppm/°C
µVp-p
Ω
BW = 0.1Hz to 100Hz
Sourcing 100µA
50
µs
IDAC
Full-Scale Output Current
RDAC = 75kΩ, Range = 1
RDAC = 75kΩ, Range = 2
RDAC = 75kΩ, Range = 3
RDAC = 15kΩ, Range = 3
RDAC = 10kΩ
0.5
1
2
20
Indefinite
mA
mA
mA
mA
Maximum Short-Circuit Current Duration
RDAC = 0Ω
RDAC = 75kΩ
10
Minute
Bits
V
Monotonicity
8
0
Compliance Voltage
Output Impedance
PSRR
Absolute Error
Absolute Drift
Mismatch Error
Mismatch Drift
AVDD – 1
see Typical Characteristics
VOUT = AVDD /2
Individual IDAC
Individual IDAC
600
5
75
0.25
15
ppm/V
%
ppm/°C
%
Between IDACs, Same Range and Code
Between IDACs, Same Range and Code
ppm/°C
ADS1218
4
SBAS187
ELECTRICAL CHARACTERISTICS: AVDD = 3V (Cont.)
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer ON, RDAC = 75kΩ, fDATA=10Hz,
VREF ≡ (REF IN+) – (REF IN–) = +1.25V unless otherwise specified.
ADS1218
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
POWER-SUPPLY REQUIREMENTS
Power-Supply Voltage
AVDD
2.7
3.3
V
nA
µA
µA
µA
µA
µA
µA
µA
µA
µA
nA
mW
Analog Current (IADC + IVREF + IDAC
ADC Current (IADC
)
PDWN = 0, or SLEEP
PGA = 1, Buffer OFF
PGA = 128, Buffer OFF
PGA = 1, Buffer ON
PGA = 128, Buffer ON
1
)
160
450
230
850
250
480
90
75
113
1
250
700
325
1325
375
675
200
VREF Current (IVREF
)
IDAC Current (IDAC
Digital Current
)
Excludes Load Current
Normal Mode, DVDD = 3V
SLEEP Mode, DVDD = 3V
Read Data Continuous Mode, DVDD = 3V
PDWN = 0
Power Dissipation
PGA = 1, Buffer OFF, REFEN = 0,
IDACS OFF, DVDD = 3V
0.8
1.4
TEMPERATURE RANGE
Operating
Storage
–40
–60
+85
+100
°C
°C
NOTES: (1) Calibration can minimize these errors. (2) ∆ VOUT is change in digital result. (3) 12pF switched capacitor at fSAMP clock frequency.
DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Input/Output
Logic Family
CMOS
Logic Level: VIH
0.8 • DVDD
DGND
DVDD
0.2 • DVDD
V
V
VIL
VOH
IOH = 1mA
IOL = 1mA
VI = DVDD
VI = 0
DVDD – 0.4
DGND
V
V
µA
µA
MHz
ns
VOL
Input Leakage: IIH
IIL
Master Clock Rate: fOSC
Master Clock Period: tOSC
DGND + 0.4
10
–10
1
200
(1)
5
1000
(1)
1/fOSC
NOTE: (1) For FLASH E/W operations, the SPEED bit in the SETUP register must be set appropriately and the device operating frequency must be:
2.3MHz < FOSC < 4.13MHz.
FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Current
Page Write
DVDD = 5V, During WR2F Command
DVDD = 3V, During WR2F Command
DVDD = 5V, During RF2R Command
DVDD = 3V, During RF2R Command
6.5
3.75
4.0
mA
mA
mA
Page Read
1.2
mA
Endurance
Data Retention
DVDD for Erase/Write
100,000
E/W Cycles
Years
V
at 25°C
100
2.7
5.25
ADS1218
5
SBAS187
PIN CONFIGURATION (TQFP-48)
36 35 34 33 32 31 30 29 28 27 26 25
D0 37
D1 38
24 RESET
23 BUFEN
22 DGND
21 DGND
20 DGND
19 DGND
18 WREN
17 RDAC
D2 39
D3 40
D4 41
D5 42
ADS1218
D6 43
D7 44
AGND 45
VREFOUT 46
VREF+ 47
VREF– 48
16 IDAC2
15 IDAC1
14 VRCAP
13 AVDD
1
2
3
4
5
6
7
8
9
10 11 12
PIN DESCRIPTIONS
PIN
PIN
NUMBER
NAME
DESCRIPTION
NUMBER
NAME
DESCRIPTION
24
25
26
27
RESET
XIN
Active LOW, resets the entire chip.
Clock Input
1
2
AVDD
Analog Power Supply
Analog Ground
AGND
XOUT
Clock Output, used with crystal or resonator.
3
A
IN0
Analog Input 0
PDWN
Active LOW. Power Down. The power down
function shuts down the analog and digital
circuits.
4
AIN
1
Analog Input 1
5
A
A
IN2
IN3
Analog Input 2
6
Analog Input 3
28
29
POL
DSYNC
DGND
DVDD
DRDY
CS
Serial Clock Polarity
7
AIN
4
Analog Input 4
Active LOW, Synchronization Control
Digital Ground
8
A
A
IN5
IN6
Analog Input 5
30
9
Analog Input 6
31
Digital Power Supply
10
11
12
13
14
15
16
17
18
19-22
23
AIN
7
Analog Input 7
32
Active LOW, Data Ready
Active LOW, Chip Select
Serial Clock, Schmitt Trigger
Serial Data Input, Schmitt Trigger
Serial Data Output
AINCOM
AGND
AVDD
Analog Input Common
Analog Ground
33
34
SCLK
DIN
Analog Power Supply
VREF Bypass CAP
Current DAC1 Output
Current DAC2 Output
Current DAC Resistor
35
VRCAP
IDAC1
IDAC2
RDAC
36
DOUT
37-44
45
D0-D7
AGND
VREFOUT
VREF+
VREF–
Digital I/O 0-7
Analog Ground
46
Voltage Reference Output
Positive Differential Reference Input
Negative Differential Reference Input
WREN
DGND
BUFEN
Active High, FLASH Write Enable
Digital Ground
47
48
Buffer Enable
ADS1218
6
SBAS187
TIMING SPECIFICATIONS
CS
t3
t1
t2
t10
SCLK
(POL = 0)
SCLK
(POL = 1)
t2
t4
t5
t6
t11
DIN
MSB
LSB
t7
t8
t9
(Command or Command and Data)
MSB(1)
LSB(1)
DOUT
NOTE: (1) Bit Order = 0.
ADS1218
SCLK Reset Waveform
t13
Resets On
Falling Edge
t13
SCLK
t16
t12
t14
t15
RESET, DSYNC, PDWN
DDR Update Timing
DRDY
t17
TIMING SPECIFICATION TABLES
SPEC
DESCRIPTION
MIN
MAX
UNITS
t1
SCLK Period
4
tOSC Periods
3
DRDY Periods
t2
t3
t4
t5
t6
SCLK Pulse Width, HIGH and LOW
CS LOW to first SCLK Edge; Setup Time
DIN Valid to SCLK Edge; Setup Time
Valid DIN to SCLK Edge; Hold Time
200
0
50
50
ns
ns
ns
ns
Delay between last SCLK edge for DIN and first SCLK
edge for DOUT
:
RDATA, RDATAC, RREG, WREG, RRAM, WRAM
CSREG, CSRAMX, CSRAM
CHKARAM, CHKARAMX
50
200
1100
tOSC Periods
tOSC Periods
tOSC Periods
ns
(1)
t7
t8
SCLK Edge to Valid New DOUT
SCLK Edge to DOUT, Hold Time
Last SCLK Edge to DOUT Tri-State
50
10
(1)
0
6
ns
t9
tOSC Periods
NOTE: DOUT goes tri-state immediately when CS goes HIGH.
t10
t11
CS LOW time after final SCLK edge
Final SCLK edge of one op code until first edge SCLK
0
ns
of next command:
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX,
CSRAM, CSARAM, CSREG, SLEEP,
RDATA, RDATAC, STOPC
DSYNC, RESET
CSFL
CREG, CRAM
RF2R
CREGA
4
16
33,000
220
1090
1600
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
DRDY Periods
DRDY Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
tOSC Periods
WR2F
76,850 (SPEED = 0)
101,050 (SPEED = 1)
4
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL
SELFCAL
RESET (Command, SCLK, or Pin)
SCLK Reset, First HIGH Pulse
SCLK Reset, LOW Pulse
SCLK Reset, Second HIGH Pulse
SCLK Reset, Third HIGH Pulse
Pulse Width
7
14
16
300
5
550
1050
4
t12
t13
t14
t15
t16
t17
500
750
1250
DOR Data Not Valid
4
NOTE: (1) Load = 20pF 10kΩ to DGND.
ADS1218
7
SBAS187
TYPICAL CHARACTERISTICS
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA1
PGA4
PGA2
PGA8
PGA1
PGA1
PGA1
PGA2
PGA4
PGA8
PGA16 PGA32
PGA64
PGA128
PGA32
PGA64
PGA128
PGA16
Sinc3 Filter, Buffer ON
Sinc3 Filter
0
0
0
500
1000
Decimation Ratio =
1500
fMOD
2000
0
0
0
500
1000
Decimation Ratio =
1500
fMOD
2000
fDATA
fDATA
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA1
PGA4
PGA2
PGA8
PGA2
PGA4
PGA8
PGA64
PGA128
PGA16 PGA32
PGA64
PGA32
PGA128
PGA16
Sinc3 Filter, VREF = 1.25V, Buffer OFF
Sinc3 Filter, VREF = 1.25V, Buffer ON
500
1000
1500
fMOD
2000
500
1000
1500
fMOD
2000
Decimation Ratio =
Decimation Ratio =
fDATA
fDATA
FAST SETTLING FILTER
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO
EFFECTIVE NUMBER OF BITS
vs DECIMATION RATIO
22
21
20
19
18
17
16
15
14
13
12
22
21
20
19
18
17
16
15
14
13
12
PGA2
PGA4
PGA8
PGA64
PGA128
PGA32
PGA16
Sinc2 Filter
Fast Settling Filter
500
1000
1500
fMOD
2000
500
1000
Decimation Ratio =
1500
fMOD
2000
Decimation Ratio =
fDATA
fDATA
ADS1218
8
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
CMRR vs FREQUENCY
NOISE vs INPUT SIGNAL
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–2.5
–1.5
–0.5
0.5
1.5
2.5
1
10
100
1k
10k
100k
VIN (V)
Frequency of CM Signal (Hz)
OFFSET vs TEMPERATURE
PSRR vs FREQUENCY
120
110
100
90
80
70
60
50
40
30
20
10
0
50
0
PGA16
PGA1
–50
PGA64
–100
–150
–200
PGA128
–50
–30
–10
10
30
50
70
90
1
10
100
1k
10k
100k
Temperature (°C)
Frequency of Power Supply (Hz)
GAIN vs TEMPERATURE
INTEGRAL NON-LINEARITY vs INPUT SIGNAL
1.00010
1.00006
1.00002
0.99998
0.99994
0.99990
0.99986
10
8
–40°C
6
4
+85°C
2
0
–2
–4
–6
–8
–10
+25°C
–50
–30
–10
10
30
50
70
90
–2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
Temperature (°C)
VIN (V)
ADS1218
9
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
CURRENT vs TEMPERATURE
ADC CURRENT vs PGA
250
200
150
100
50
900
800
700
600
500
400
300
200
100
0
AVDD = 5V, Buffer = ON
Buffer = OFF
IDIGITAL
IANALOG
IANALOG
AVDD = 3V, Buffer = ON
Buffer = OFF
IDIGITAL
0
–50
–30
–10
10
30
50
70
90
0
1
2
4
8
16
32
64
128
Temperature (°C)
PGA Setting
DIGITAL CURRENT
HISTOGRAM OF OUTPUT DATA
4500
4000
3500
3000
2500
2000
1500
1000
500
400
350
300
250
200
150
100
50
Normal
fOSC = 4.91MHz
SPEED = 0
Normal
SLEEP
fOSC = 4.91MHz
fOSC = 2.45MHz
Power
Down
SLEEP
fOSC = 2.45MHz
0
0
–2
–1.5
–1
–0.5
0
0.5
1
1.5
2
3.0
4.0
5.0
ppm of FS
VDD (V)
OFFSET DAC - OFFSET vs TEMPERATURE
VREFOUT vs LOAD CURRENT
200
170
140
110
80
2.55
2.50
2.45
50
20
–10
–40
–70
–100
–50
–30
–10
10
30
50
70
90
–0.5
0
0.5
1.0
1.5
2.0
2.5
Temperature (°C)
VREFOUT Current Load (mA)
ADS1218
10
SBAS187
TYPICAL CHARACTERISTICS (Cont.)
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, fDATA = 10Hz, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, unless otherwise specified.
IDAC ROUT vs VOUT
OFFSET DAC - GAIN vs TEMPERATURE
1.00020
1.00016
1.00012
1.00008
1.00004
1.00000
0.99996
0.99992
0.99988
0.99984
0.99980
0.99976
1.000
1.000
0.999
0.999
0.998
+85°C
+25°C
–40°C
–50
–30
–10
10
30
50
70
90
0
1
2
3
4
5
Temperature (°C)
VDD – VOUT (V)
IDAC MATCHING vs TEMPERATURE
IDAC NORMALIZED vs TEMPERATURE
3000
2000
1000
0
1.01
1.005
1
–1000
–2000
–3000
–4000
–5000
–6000
0.995
0.99
0.985
–50
–30
–10
10
30
50
70
90
–50
–30
–10
10
30
50
70
90
Temperature (°C)
Temperature (°C)
IDAC DIFFERENTIAL NON-LINEARITY
RANGE = 1, RDAC = 150kΩ, VREF = 2.5V
IDAC INTEGRAL NON-LINEARITY
RANGE = 1, RDAC = 150kΩ, VREF = 2.5V
0.5
0.4
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
32
64
96
128
160
192
224
255
0
32
64
96
128
160
192
224
255
IDAC Code
IDAC Code
ADS1218
11
SBAS187
BURNOUT CURRENT SOURCES
OVERVIEW
When the Burnout bit is set in the ACR configuration register,
two current sources are enabled. The current source on the
positive input channel sources approximately 2µA of current.
The current source on the negative input channel sinks ap-
proximately 2µA. This allows for the detection of an open
circuit (full-scale reading) or short circuit (0V differential
reading) on the selected input differential pair.
INPUT MULTIPLEXER
The input multiplexer provides for any combination of
differential inputs to be selected on any of the input chan-
nels, as shown in Figure 1. For example, if channel 1 is
selected as the positive differential input channel, any other
channel can be selected as the negative differential input
channel. With this method, it is possible to have up to eight
fully differential input channels.
INPUT BUFFER
The input impedance of the ADS1218 without the buffer
is 5MΩ/PGA. With the buffer enabled, the input voltage range
is reduced and the analog power-supply current is higher. The
buffer is controlled by ANDing the state of the BUFEN pin
with the state of the BUFFER bit in the ACR register.
In addition, current sources are supplied that will source or
sink current to detect open or short circuits on the input pins.
IDAC1 AND IDAC2
A
IN0
The ADS1218 has two 8-bit current output DACs that can be
controlled independently. The output current is set with
RDAC, the range select bits in the ACR register, and the 8-bit
digital value in the IDAC register. The output current
= VREF/(8 • RDAC)(2RANGE–1)(DAC CODE). With VREFOUT
= 2.5V and RDAC = 150kΩ to AGND the full-scale output
can be selected to be 0.5, 1, or 2mA. The compliance voltage
range is 0 to within 1V of AVDD. When the internal voltage
reference of the ADS1218 is used, it is the reference for the
IDAC. An external reference may be used for the IDACs by
disabling the internal reference and tying the external refer-
ence input to the VREFOUT pin.
AIN
AIN
AIN
AIN
AIN
AIN
AIN
1
2
3
4
5
6
7
AVDD
Burnout Current Source On
PGA
Burnout Current Source On
The Programmable Gain Amplifier (PGA) can be set to gains
of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually
improve the effective resolution of the A/D converter. For
instance, with a PGA of 1 on a 5V full-scale range, the A/D
converter can resolve to 1µV. With a PGA of 128, on a 40mV
full-scale range, the A/D converter can resolve to 75nV. With
a PGA of 1 on a 5V full-scale range, it would require a 26-bit
A/D converter to resolve 75nV.
AGND
IDAC1
AINCOM
PGA OFFSET DAC
FIGURE 1. Input Multiplexer Configuration.
The input to the PGA can be shifted by half the full-scale input
range of the PGA by using the ODAC register. The ODAC
(Offset DAC) register is an 8-bit value; the MSB is the sign
and the seven LSBs provide the magnitude of the offset. Using
the ODAC register does not reduce the performance of the
A/D converter.
TEMPERATURE SENSOR
An on-chip diode provides temperature sensing capability.
When the configuration register for the input MUX is set to
all 1s, the diode is connected to the input of the A/D
converter. All other channels are open. The anode of the
diode is connected to the positive input of the A/D converter,
and the cathode of the diode is connected to negative input
of the A/D converter. The output of IDAC1 is connected to
the anode to bias the diode and the cathode of the diode is
also connected to ground to complete the circuit.
MODULATOR
The modulator is a single-loop second-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the external clock (fOSC). The frequency division is deter-
mined by the SPEED bit in the SETUP register.
In this mode, the output of IDAC1 is also connected to the
output pin, so some current may flow into an external load
from IDAC1, rather than the diode.
SPEED BIT
fMOD
0
1
fOSC/128
f
OSC/ 256
ADS1218
12
SBAS187
CALIBRATION
settling filter for the next two conversions, the first of which
should be discarded. It will then use the sinc2 followed by the
sinc3 filter to improve noise performance. This combines the
low-noise advantage of the sinc3 filter with the quick response
of the fast settling time filter. The frequency response of each
filter is shown in Figure 3.
The offset and gain errors in the ADS1218, or the complete
system, can be reduced with calibration. Internal calibration of
the ADS1218 is called self calibration. This is handled with
three commands. One command does both offset and gain
calibration. There is also a gain calibration command and an
offset calibration command. Each calibration process takes
seven tDATA periods to complete. Therefore, it takes 14 tDATA
SINC3 FILTER RESPONSE
(–3dB = 0.262 • fDATA = 15.76Hz)
periods to complete both an offset and gain calibration.
0
For system calibration, the appropriate signal must be
applied to the inputs. The system offset command requires a
“zero” differential input signal. It then computes an offset that
will nullify offset in the system. The system gain command
requires a positive “full-scale” differential input signal. It then
computes a value to nullify gain errors in the system. Each of
these calibrations will take seven tDATA periods to complete.
–20
–40
–60
–80
Calibration should be performed after power on, a change in
temperature, a change in decimation ratio, or a change in the
PGA. Calibration will remove the offset in the ODAC register.
Therefore, changes to the ODAC register must be done after
calibration.
–100
–120
0
0
0
30
30
30
60 90 120 150 180 210 240 270 300
Frequency (Hz)
At the completion of calibration, the DRDY signal will go
LOW to indicate that calibration is complete and valid data is
available.
SINC2 FILTER RESPONSE
(–3dB = 0.318 • fDATA = 19.11Hz)
0
–20
DIGITAL FILTER
The Digital Filter can use either the fast settling, sinc2, or sinc3
filter, as shown in Figure 2. In addition, the Auto mode
changes the sinc filter after the input channel or PGA is
changed. When switching to a new channel, it will use the fast
–40
–60
–80
Adjustable Digital Filter
Sinc3
–100
–120
60 90 120 150 180 210 240 270 300
Frequency (Hz)
Modulator
Output
Sinc2
Data Out
FAST SETTLING FILTER RESPONSE
(–3dB = 0.469 • fDATA = 28.125Hz)
0
–20
Fast Settling
FILTER SETTLING TIME
FILTER
–40
SETTLING TIME
(Conversion Cycles)
–60
Sinc3
Sinc2
Fast
3(1)
2(1)
1(1)
–80
–100
–120
NOTE: (1) With Synchronized Channel Changes.
AUTO MODE FILTER SELECTION
CONVERSION CYCLE
60 90 120 150 180 210 240 270 300
Frequency (Hz)
1
2
3
4+
Discard
Fast
Sinc2
Sinc3
NOTE: fDATA = 60Hz.
FIGURE 2. Filter Step Responses.
FIGURE 3. Filter Frequency Responses.
ADS1218
13
SBAS187
VOLTAGE REFERENCE
DIGITAL I/O INTERFACE
The voltage reference used for the ADS1218 can either be
internal or external. The power-up configuration for the
voltage reference is 2.5V internal. The selection for the
voltage reference is made through the status configuration
register.
The ADS1218 has eight pins dedicated for digital I/O. The
default power-up condition for the digital I/O pins are as
inputs. All of the digital I/O pins are individually configurable
as inputs or outputs. They are configured through the DIR
control register. The DIR register defines whether the pin is an
input or output, and the DIO register defines the state of the
digital output. When the digital I/O are configured as inputs,
DIO is used to read the state of the pin.
The internal voltage reference is selectable as either 1.25V
or 2.5V (AVDD = 5V only). The VREFOUT pin should have a
0.1µF capacitor to AGND.
The external voltage reference is differential and is repre-
sented by the voltage difference between the pins: +VREF
and –VREF. The absolute voltage on either pin (+VREF and
–VREF) can range from AGND to AVDD, however, the
differential voltage must not exceed 2.5V. The differential
voltage reference provides easy means of performing
ratiometric measurement.
SERIAL INTERFACE
The serial interface is standard four-wire SPI compatible (DIN,
DOUT, SCLK, and CS). The ADS1218 also offers the flexibil-
ity to select the polarity of the serial clock through the POL
pin. The serial interface can be clocked up to fOSC/4. If CS
goes HIGH, the serial interface is reset. When CS goes LOW,
a new command is expected.
VRCAP PIN
The serial interface operates independently of DRDY. DRDY
is used to indicate availability of data in the DOR. In order to
ensure the validity of the data being read, DOR timing
requirements must be met.
This pin provides a bypass cap for noise filtering on internal
VREF circuitry only. The recommended capacitor is a 0.001µF
ceramic cap. If an external VREF is used, this pin can be left
unconnected.
DSYNC OPERATION
CLOCK GENERATOR
DSYNC is used to provide for synchronization of the A/D
conversion with an external event. Synchronization can be
achieved either through the DSYNC pin or the DSYNC
command. When the DSYNC pin is used, the filter counter
is reset on the falling edge of DSYNC. The modulator is held
in reset until DSYNC is taken HIGH. Synchronization
occurs on the next rising edge of the system clock after
DSYNC is taken HIGH.
The clock source for the ADS1218 can be provided from a
crystal, ceramic resonator, oscillator, or external clock. When
the clock source is a crystal or ceramic resonator, external
capacitors must be provided to ensure start-up and a stable
clock frequency. This is shown in Figure 4 and Table I.
When the DSYNC command is sent, the filter counter is
reset after the last SCLK on the DSYNC command. The
modulator is held in RESET until the next edge of SCLK is
detected. Synchronization occurs on the next rising edge of
the system clock after the first SCLK after the DSYNC
command.
XIN
C1
C2
Crystal
or
Ceramic Resonator
XOUT
POWER-UP—SUPPLY VOLTAGE RAMP RATE
The power-on reset circuitry was designed to accommodate
digital supply ramp rates as slow as 1V/10ms. To ensure
proper operation, the power supply should ramp monotoni-
cally. The POR issues the RESET command as described
below.
FIGURE 4. Crystal or Ceramic Resonator Connection.
CLOCK
PART
SOURCE FREQUENCY
C1
C2
NUMBER
Crystal
Crystal
Crystal
Crystal
2.4576
4.9152
4.9152
4.9152
0-20pF 0-20pF ECS, ECSD 2.45 - 32
RESET
0-20pF 0-20pF
0-20pF 0-20pF
ECS, ECSL 4.91
ECS, ECSD 4.91
There are three methods of reset. The RESET pin, the
RESET command, and the SCLK Reset pattern. They all
perform the same function. After a reset, the FLASH data
values from Page 0 are loaded into RAM, subsequently data
values from Bank 0 of RAM are loaded into the configura-
tion registers.
0-20pF 0-20pF CTS, MP 042 4M9182
TABLE I. Typical Clock Sources.
ADS1218
14
SBAS187
MEMORY
basis. Also, the RAM can be directly read or written through
the serial interface on power-up. The banks allow separate
storage of settings for each input.
Three types of memory are used on the ADS1218: registers,
RAM, and FLASH. 16 registers directly control the various
functions (PGA, DAC value, Decimation Ratio, etc.) and can
be directly read or written to. Collectively, the registers contain
all the information needed to configure the part, such as data
format, mux settings, calibration settings, decimation ratio, etc.
Additional registers, such as conversion data, are accessed
through dedicated instructions.
Configuration
Register Bank
16 bytes
RAM
128 Bytes
FLASH
4k Bytes
SETUP
MUX
ACR
IDAC1
IDAC2
ODAC
DIO
The on-chip FLASH can be used to store non-volatile data. The
FLASH data is separate from the configuration registers and
therefore can be used for any purpose, in addition to device
configuration. The FLASH page data is read and written in 128
byte blocks through the RAM banks, i.e. all RAM banks map
to a single page of FLASH, as shown in Figure 5.
DIR
Bank 0
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
16 bytes
Bank 2
16 bytes
REGISTER BANK TOPOLOGY
Page 0
128 bytes
The operation of the device is set up through individual
registers. The set of the 16 registers required to configure the
device is referred to as a Register Bank, as shown in Figure 5.
RAM
Reads and Writes to Registers and RAM occur on a byte
basis. However, copies between registers and RAM occurs
on a bank basis. The RAM is independent of the Registers,
i.e.: the RAM can be used as general-purpose RAM.
Bank 7
16 bytes
The ADS1218 supports any combination of eight analog
inputs. With this flexibility, the device could easily support
eight unique configurations—one per input channel. In order
to facilitate this type of usage, eight separate register banks are
available. Therefore, each configuration could be written once
and recalled as needed without having to serially retransmit all
the configuration data. Checksum commands are also in-
cluded, which can be used to verify the integrity of RAM.
Page 31
128 bytes
The RAM provides eight “banks”, with a bank consisting of
16 bytes. The total size of the RAM is 128 bytes. Copies
between the registers and RAM are performed on a bank
FIGURE 5. Memory Organization.
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
SETUP
MUX
ID
ID
ID
SPEED
PSEL0
REF EN
NSEL3
IDAC1R0
IDAC1_3
IDAC2_3
OSET_3
DIO_3
REF HI
NSEL2
PGA2
BUF EN
NSEL1
PGA1
BIT ORDER
NSEL0
PGA0
PSEL3
BOCS
PSEL2
IDAC2R1
IDAC1_6
IDAC2_6
OSET_6
DIO_6
PSEL1
IDAC2R0
IDAC1_5
IDAC2_5
OSET_5
DIO_5
ACR
IDAC1R1
IDAC1_4
IDAC2_4
OSET_4
DIO_4
IDAC1
IDAC2
ODAC
DIO
IDAC1_7
IDAC2_7
SIGN
IDAC1_2
IDAC2_2
OSET_2
DIO_2
IDAC1_1
IDAC2_1
OSET_1
DIO_1
IDAC1_0
IDAC2_0
OSET_0
DIO_0
DIO_7
DIR_7
DIR
DIR_6
DIR_5
DIR_4
DIR_3
DIR_2
DIR_1
DIR_0
DEC0
M/DEC1
OCR0
OCR1
OCR2
FSR0
FSR1
FSR2
DEC07
DRDY
DEC06
U/B
DEC05
SMODE1
OCR05
OCR13
OCR21
FSR05
FSR13
FSR21
DEC04
SMODE0
OCR04
OCR12
OCR20
FSR04
DEC03
WREN
DEC02
DEC10
OCR02
OCR10
OCR18
FSR02
FSR10
FSR18
DEC01
DEC09
OCR01
OCR09
OCR17
FSR01
FSR09
FSR17
DEC00
DEC08
OCR00
OCR08
OCR16
FSR00
OCR07
OCR15
OCR23
FSR07
FSR15
FSR23
OCR06
OCR14
OCR22
FSR06
FSR14
FSR22
OCR03
OCR11
OCR19
FSR03
FSR11
FSR19
FSR12
FSR08
FSR20
FSR16
TABLE II. Registers.
ADS1218
15
SBAS187
The RAM address space is linear, therefore accessing RAM
is done using an auto-incrementing pointer. Access to RAM
in the entire memory map can be done consecutively without
having to address each bank individually. For example, if
you were currently accessing bank 0 at offset 0xF (the last
location of bank 0), the next access would be bank 1 and
offset 0x0. Any access after bank 7 and offset 0xF will wrap
around to bank 0 and Offset 0x0.
The ADS1218 supports any combination of eight analog
inputs and the FLASH memory supports up to 32 unique Page
configurations. With this flexibility, the device could support
32 unique configurations for each of the eight analog input
channels. For instance, the on-chip temperature sensor could
be used to monitor temperature then different calibration
coefficients could be recalled for each of the eight analog
input channels based on the change in temperature. This
would enable the user to recall calibration coefficients for
every 4°C change in temperature over the industrial tempera-
ture range which could be used to correct for drift errors.
Checksum commands are also included, which can be used to
verify the integrity of FLASH.
Although the Register Bank memory is linear, the concept of
addressing the device can also be thought of in terms of bank
and offset addressing. Looking at linear and bank addressing
syntax, we have the following comparison: in the linear
memory map, the address 0x14 is equivalent to bank 1 and
offset 0x4. Simply stated, the most significant four bits
represent the bank, and the least significant four bits repre-
sent the offset. The offset is equivalent to the register
address for that bank of memory.
The following two commands can be used to manipulate the
FLASH. First, the contents of FLASH can be written to with
the WR2F (write RAM to FLASH) command. This com-
mand first erases the designated FLASH page and then
writes the entire content of RAM (all banks) into the desig-
nated FLASH page. Second, the contents of FLASH can be
read with the RF2R (read FLASH to RAM) command. This
command reads the designated FLASH page into the entire
contents of RAM (all banks). In order to ensure maximum
endurance and data retention, the SPEED bit in the SETUP
register must be set for the appropriate fOSC frequency.
FLASH
Reads and Writes to FLASH occur on a Page basis.
Therefore, the entire contents of RAM is used for both
Read and Write operations. The FLASH is independent of
the Registers, i.e., the FLASH can be used as general-
purpose FLASH.
Upon power-up or reset, the contents of FLASH Page 0 are
loaded into RAM subsequently the contents of RAM Bank
0 are loaded into the configuration register. Therefore, the
user can customize the power-up configuration for the de-
vice. Care should be taken to ensure that data for FLASH
Page 0 is written correctly, in order to prevent unexpected
operation upon power-up.
Writing to or erasing FLASH can be disabled either through
the WREN pin or the WREN register bit. If the WREN pin
is LOW OR the WREN bit is cleared, then the WR2F
command has no effect. This protects the integrity of the
FLASH data from being inadvertently corrupted.
Accessing the FLASH data either through read, write, or
erase may effect the accuracy of the conversion result.
Therefore, the conversion result should be discarded when
accesses to FLASH are done.
ADS1218
16
SBAS187
DETAILED REGISTER DEFINITIONS
SETUP (Address 00H) Setup Register
Reset Value = iii01110
ACR (Address 02H) Analog Control Register
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BOCS
IDAC2R1 IDAC2R0 IDAC1R1 IDAC1R0
PGA2
PGA1
PGA0
ID
ID
ID
SPEED
REF EN
REF HI
BUF EN BIT ORDER
bit 7
BOCS: Burnout Current Source
0 = Disabled (default)
1 = Enabled
bit 7-5 Factory Programmed Bits
bit 4
bit 3
bit 2
bit 1
bit 0
SPEED: FLASH Access Clock Speed
0 : 2.30MHz > fOSC > 3.12MHz (default)
1 : 3.12MHz > fOSC > 4.13MHz
VREF
2RANGE−1 DAC Code
IDAC Current =
(
)
)
(
REF EN: Internal Voltage Reference Enable
0 = Internal Voltage Reference Disabled
1 = Internal Voltage Reference Enabled (default)
8• RDAC
bit 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for
REF HI: Internal Reference Voltage Select
0 = Internal Reference Voltage = 1.25V
1 = Internal Reference Voltage = 2.5V (default)
IDAC2
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
BUF EN: Buffer Enable
0 = Buffer Disabled
1 = Buffer Enabled (default)
bit 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for
BIT ORDER: Set Order Bits are Transmitted
0 = Most Significant Bit Transmitted First (default)
1 = Least Significant Bit Transmitted First
Data is always shifted into the part most significant
bit first. Data is always shifted out of the part most
significant byte first. This configuration bit only
controls the bit order within the byte of data that is
shifted out.
IDAC1
00 = Off (default)
01 = Range 1
10 = Range 2
11 = Range 3
bit 2-0 PGA2: PGA1: PGA0: Programmable Gain Ampli-
fier
Gain Selection
000 = 1 (default)
001 = 2
MUX (Address 01H) Multiplexer Control Register
Reset Value = 01H
010 = 4
011 = 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
100 = 16
101 = 32
110 = 64
111 = 128
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
bit 7-4 PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel
Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2
IDAC1 (Address 03H) Current DAC 1
Reset Value = 00H
0011 = AIN3
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0100 = AIN4
0101 = AIN5
IDAC1_7 IDAC1_6 IDAC1_5 IDAC1_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
0110 = AIN6
0111 = AIN7
1xxx = AINCOM (except when all bits are 1’s)
1111 = Temperature Sensor Diode Anode
The DAC code bits set the output of DAC1 from 0 to full-
scale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC1 range bits in the ACR register.
bit 3-0 NSEL3: NSEL2: NSEL1: NSEL0: Negative Chan-
IDAC2 (Address 04H) Current DAC 2
Reset Value = 00H
nel Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
IDAC2_7 IDAC2_6 IDAC2_5 IDAC2_4 IDAC1_3 IDAC1_2 IDAC1_1 IDAC1_0
0011 = AIN3
0100 = AIN4
0101 = AIN5
0110 = AIN6
The DAC code bits set the output of DAC2 from 0 to full-
scale. The value of the full-scale current is set by this Byte,
VREF, RDAC, and the DAC2 range bits in the ACR register.
0111 = AIN7
1xxx = AINCOM (except when all bits are 1’s)
1111 = Temperature Sensor Diode Cathode Analog GND
ADS1218
17
SBAS187
ODAC (Address 05H) Offset DAC Setting
Reset Value = 00H
bit 5-4 SMODE1: SMODE0: Settling Mode
00 = Auto (default)
01 = Fast Settling filter
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
10 = Sinc2 filter
SIGN
OSET6
OSET5
OSET4
OSET3
OSET2
OSET1
OSET0
11 = Sinc3 Flash filter
bit 7
Offset Sign
0 = Positive
bit 3
WREN: Write Enable
0 = Flash Writing Disabled (default)
1 = Flash Writing Enabled
This bit is AND’d with the WREN pin to enable or
disable Flash Writing and Erasing
1 = Negative
VREF
Code
127
•
bit 6-0 Offset =
2 • PGA
bit 2-0 DEC10: DEC09: DEC08: Most Significant Bits of
the Decimation Value
NOTE: Calibration will cancel the value in the ODAC register. Therefore, writing
to the ODAC register should be done after calibration.
OCR0 (Address 0AH) Offset Calibration Coefficient
(Least Significant Byte)
DIO (Address 06H) Digital I/O
Reset Value = 00H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reset Value = 00H
DIO7
DIO6
DIO5
DIO4
DIO3
DIO2
DIO1
DIO0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A value written to this register will appear on the digital
I/O pins if the pin is configured as an output in the DIR
register. Reading this register will return the value of the
digital I/O pins.
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR1 (Address 0BH) Offset Calibration Coefficient
(Middle Byte)
Reset Value = 00H
DIR (Address 07H) Direction control for digital I/O
Reset Value = FFH
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCR15
OCR14
OCR13
OCR12
OCR11
OCR10
OCR09
OCR08
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
DIR1
DIR0
OCR2 (Address 0CH) Offset Calibration Coefficient
(Most Significant Byte)
Reset Value = 00H
Each bit controls whether the Digital I/O pin is an output
(= 0) or input (= 1). The default power-up state is as inputs.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DEC0 (Address 08H) Decimation Register
(Least Significant 8 bits)
OCR23
OCR22
OCR21
OCR20
OCR19
OCR18
OCR17
OCR16
Reset Value = 80H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR0 (Address 0DH) Full-Scale Register
(Least Significant Byte)
DEC07
DEC06
DEC05
DEC04
DEC03
DEC02
DEC01
DEC00
Reset Value = 24H
The decimation value is defined with 11 bits for a range of
20 to 2047. This register is the least significant 8 bits. The
3 most significant bits are contained in the M/DEC1 register.
The default data rate is 10Hz with a 2.4576MHz crystal.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR07
FSR06
FSR05
FSR04
FSR03
FSR02
FSR01
FSR00
FSR1 (Address 0EH) Full-Scale Register
(Middle Byte)
Reset Value = 90H
M/DEC1 (Address 09H) Mode and Decimation Register
Reset Value = 07H
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DRDY
U/B
SMODE1 SMODE0
WREN
DEC10
DEC09
DEC08
FSR15
FSR14
FSR13
FSR12
FSR011
FSR10
FSR09
FSR08
bit 7
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
FSR2 (Address 0FH) Full-Scale Register
(Most Significant Byte)
Reset Value = 67H
bit 6
U/B: Data Format
0 = Bipolar (default)
1 = Unipolar
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FSR23
FSR22
FSR21
FSR20
FSR019
FSR18
FSR17
FSR16
U/B
ANALOG INPUT
DIGITAL OUTPUT
+FSR
Zero
–FSR
+FSR
Zero
0x7FFFFF
0x000000
0x800000
0xFFFFFF
0x000000
0x000000
0
1
–FSR
ADS1218
18
SBAS187
Operands:
COMMAND DEFINITIONS
n = count (0 to 127)
r = register (0 to 15)
x = don’t care
The commands listed below control the operation of the
ADS1218. Some of the commands are stand-alone com-
mands (e.g., RESET) while others require additional bytes
(e.g., WREG requires command, count, and the data bytes).
Commands that output data require a minimum of four fOSC
cycles before the data is ready (e.g., RDATA).
a = RAM bank address (0 to 7)
f = FLASH page address (0 to 31)
COMMANDS
DESCRIPTION
COMMAND BYTE
2ND COMMAND BYTE
RDATA
RDATAC
STOPC
RREG
RRAM
CREG
CREGA
WREG
WRAM
RF2R
WR2F
Read Data
0000 0001 (01H)
0000 0011 (03H)
0000 1111 (0FH)
0001 r r r r (1xH)
0010 0aaa (2xH)
0100 0aaa (4xH)
0100 1000 (48H)
0101 r r r r (5xH)
0110 0aaa (6xH)
100f f f f f (8, 9xH)
101f f f f f (A,BxH)
1100 0aaa (CxH)
1101 0aaa (DxH)
1101 1000 (D8H)
1101 1111 (DFH)
1110 0aaa (ExH)
1110 1000 (E8H)
1110 1100 (ECH)
1111 0000 (F0H)
1111 0001 (F1H)
1111 0010 (F2H)
1111 0011 (F3H)
1111 0100 (F4H)
1111 1100 (FCH)
1111 1101 (FDH)
1111 1110 (FEH)
—
—
—
Read Data Continuously
Stop Read Data Continuously
Read from REG Bank “rrrr”
Read from RAM Bank “aaa”
Copy REGs to RAM Bank “aaa”
Copy REGS to all RAM Banks
Write to REG “rrrr”
Write to RAM Bank “aaa”
Read FLASH page to RAM
Write RAM to FLASH page
Copy RAM Bank “aaa” to REG
Calc RAM Bank “aaa” Checksum
Calc all RAM Bank Checksum
Calc REG Checksum
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
xxxx_nnnn (# of reg-1)
xnnn_nnnn (# of bytes-1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRAM
CSRAMX
CSARAMX
CSREG
CSRAM
CSARAM
CSFL
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
DSYNC
SLEEP
Calc RAM Bank “aaa” Checksum
Calc all RAM Banks Checksum
Calc FLASH Checksum
Self Cal Offset and Gain
Self Cal Offset
Self Cal Gain
Sys Cal Offset
Sys Cal Gain
Sync DRDY
Put in SLEEP Mode
Reset to Power-Up Values
RESET
NOTE: (1) The data received by the A/D is always MSB First, the data out format is set by the BIT ORDER bit in ACR reg.
TABLE III. Command Summary.
RDATA
Read Data
RDATAC
Read Data Continuous
Description: Read a single data value from the Data Output
Register (DOR) which is the most recent conversion result.
This is a 24-bit value.
Description: Read Data Continuous mode enables the con-
tinuous output of new data on each DRDY. This command
eliminates the need to send the Read Data Command on each
DRDY. This mode may be terminated by either the STOP
Read Continuous command or the RESET command.
Operands: None
Bytes:
1
Operands: None
Encoding: 0000 0001
Bytes:
1
Data Transfer Sequence:
Encoding: 0000 0011
Data Transfer Sequence:
Command terminated when “uuuu uuuu” equals STOPC
or RESET.
0000 0001
xxxx xxxx
• • •(1)
xxxx xxxx
MSB
xxxx xxxx
Mid-Byte
xxxx xxxx
LSB
DIN
• • •(1)
DOUT
DIN
0000 0011
• • •(1)
uuuu uuuu
MSB
uuuu uuuu
Mid-Byte
uuuu uuuu
LSB
NOTE: (1) For wait time, refer to timing specification.
• • •
DOUT
DRDY
DIN
xxxx xxxx
• • •(1)
• • •
xxxx
MSB
xxxx
xxxx
• • •
DOUT
Mid-Byte
LSB
NOTE: (1) For wait time, refer to timing specification.
ADS1218
19
SBAS187
STOPC
Stop Continuous
CREG
Copy Registers to RAM Bank
Description: Ends the continuous data output mode.
Operands: None
Description: Copy the 16 control registers to the RAM bank
specified in the op code. Refer to timing specifications for
command execution time.
Bytes:
1
Operands:
Bytes:
a
Encoding: 0000 1111
1
Data Transfer Sequence:
Encoding: 0100 0aaa
Data Transfer Sequence:
Copy Register Values to RAM Bank 3
0000 1111
xxxx xxxx
DIN
DOUT
0100 0011
xxxx xxxx
DIN
DOUT
RREG
Read from Registers
Description: Output the data from up to 16 registers starting
with the register address specified as part of the instruction.
The number of registers read will be one plus the second byte.
Ifthecountexceedstheremainingregisters,theaddresseswill
wrap back to the beginning.
CREGA Copy Registers to All RAM Banks
Description: Duplicate the 16 control registers to all the
RAM banks. Refer to timing specifications for command
execution time.
Operands: r, n
Operands: None
Bytes:
2
Bytes:
1
Encoding: 0001 rrrr xxxx nnnn
Encoding: 0100 1000
Data Transfer Sequence:
Read Two Registers Starting from Register 01H (MUX)
Data Transfer Sequence:
0100 1000
xxxx xxxx
DIN
0001 0001
xxxx xxxx
0000 0001
xxxx xxxx
• • •(1)
xxxx xxxx
MUX
xxxx xxxx
ACR
DIN
• • •(1)
DOUT
DOUT
NOTE: (1) For wait time, refer to timing specification.
WREG
Write to Register
RRAM
Read from RAM
Description: Write to the registers starting with the register
specified as part of the instruction. The number of registers
that will be written is one plus the value of the second byte.
Description: Up to 128 bytes can be read from RAM starting
at the bank specified in the op code. All reads start at the
address for the beginning of the RAM bank. The number of
bytes to read will be one plus the value of the second byte.
Operands: r, n
Bytes:
2
Encoding: 0101 rrrr xxxx nnnn
Operands: a, n
Data Transfer Sequence:
Write Two Registers Starting from 06H (DIO)
Bytes:
2
Encoding: 0010 0aaa xnnn nnnn
Data Transfer Sequence:
Read Two RAM Locations Starting from 20H
DIN
0101 0110
xxxx xxxx
xxxx 0001
xxxx xxxx
Data for DIO
xxxx xxxx
Data for DIR
xxxx xxxx
0010 0010
xxxx xxxx
x000 0001
xxxx xxxx
• • •(1)
xxxx xxxx
xxxx xxxx
DOUT
DIN
RAM Data
20H
RAM Data
21H
• • •(1)
DOUT
NOTE: (1) For wait time, refer to timing specification.
ADS1218
20
SBAS187
WRAM
Write to RAM
CRAM
Copy RAM Bank to Registers
Description: Write up to 128 RAM locations starting at the
beginning of the RAM bank specified as part of the instruc-
tion. ThenumberofbyteswrittenisRAMisoneplusthevalue
of the second byte.
Description: Copy the selected RAM Bank to the Configura-
tion Registers. This will overwrite all of the registers with the
data from the RAM bank.
Operands:
Bytes:
a
Operands: a, n
1
Bytes:
2
Encoding: 1100 0aaa
Encoding: 0110 0aaa xnnn nnnn
Data Transfer Sequence:
Data Transfer Sequence:
Copy RAM Bank 0 to the Registers
Write to Two RAM Locations starting from 10H
1100 0000
xxxx xxxx
DIN
Data for
10H
Data for
DIN
0110 0001
xxxx xxxx
x000 0001
xxxx xxxx
11H
DOUT
DOUT
xxxx xxxx
xxxx xxxx
CSRAMX
Calculate RAM Bank Checksum
RF2R Read FLASH Page to RAM
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. The ID, DRDY and DIO bits are
masked so they are not included in the checksum.
Description: Read the selected FLASH page to the RAM.
Operands:
Bytes:
f
1
Operands:
Bytes:
a
Encoding: 100f ffff
1
Data Transfer Sequence:
Encoding: 1101 0aaa
Read FLASH Page 2 to RAM
Data Transfer Sequence:
Calculate Checksum for RAM Bank 3
1000 0010
DIN
1101 0011
xxxx xxxx
DIN
xxxx xxxx
DOUT
DOUT
WR2F Write RAM to FLASH
Description: Write the contents of RAM to the selected
FLASH page.
CSARAMX Calculate the Checksum
for all RAM Banks
Operands:
Bytes:
f
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
1
Encoding: 101f ffff
Data Transfer Sequence:
Write RAM to FLASH page 31
Operands: None
Bytes:
1
1011 1111
DIN
Encoding: 1101 1000
Data Transfer Sequence:
xxxx xxxx
DOUT
1101 1000
xxxx xxxx
DIN
DOUT
ADS1218
21
SBAS187
CSFL Calculate Checksum for all FLASH Pages
CSREG
Calculate the Checksum of
Registers
Description: Calculate the checksum for all FLASH pages.
The checksum is calculated as a sum of all the bytes with the
carry ignored. All bits are included in the checksum calcula-
tion, there is no masking of bits.
Description: Calculate the checksum of all the registers. The
checksum is calculated as a sum of all the bytes with the carry
ignored. The ID, DRDY and DIO bits are masked so they are
not included in the checksum.
Operands: None
Bytes:
1
Operands: None
Encoding: 1110 1100
Bytes:
1
Data Transfer Sequence:
Encoding: 1101 1111
Data Transfer Sequence:
1110 1100
xxxx xxxx
DIN
1101 1111
xxxx xxxx
DIN
DOUT
DOUT
SELFCAL Offset and Gain Self Calibration
CSRAM
Calculate RAM Bank Checksum
Description: Starts the process of self calibration. The Offset
ControlRegister(OCR)andtheFull-ScaleRegister(FSR)are
updated with new values after this operation.
Description: Calculate the checksum of the selected RAM
Bank. The checksum is calculated as a sum of all the bytes
with the carry ignored. All bits are included in the checksum
calculation, there is no masking of bits.
Operands: None
Bytes:
1
Operands:
Bytes:
a
Encoding: 1111 0000
1
Data Transfer Sequence:
Encoding: 1110 0aaa
Data Transfer Sequence:
Calculate Checksum for RAM Bank 2
1111 0000
xxxx xxxx
DIN
DOUT
1110 0010
xxxx xxxx
DIN
DOUT
SELFOCAL Offset Self Calibration
Description: Starts the process of self-calibration for offset.
The Offset Control Register (OCR) is updated after this
operation.
CSARAM
Calculate Checksum for all
RAM Banks
Operands: None
Description: Calculate the checksum of all RAM Banks. The
checksum is calculated as a sum of all the bytes with the carry
ignored. All bits are included in the checksum calculation,
there is no masking of bits.
Bytes:
1
Encoding: 1111 0001
Data Transfer Sequence:
Operands: None
1111 0001
xxxx xxxx
DIN
Bytes:
1
Encoding: 1110 1000
DOUT
Data Transfer Sequence:
1110 1000
xxxx xxxx
DIN
DOUT
ADS1218
22
SBAS187
SELFGCAL Gain Self Calibration
DSYNC
Sync DRDY
Description: Starts the process of self-calibration for gain.
The Full-Scale Register (FSR) is updated with new values
after this operation.
Description: Synchronizes the ADS1218 to the serial clock
edge.
Operands: None
Operands: None
Bytes:
1
Bytes:
1
Encoding: 1111 1100
Encoding: 1111 0010
Data Transfer Sequence:
Data Transfer Sequence:
1111 1100
xxxx xxxx
DIN
1111 0010
xxxx xxxx
DIN
DOUT
DOUT
SLEEP
Sleep Mode
Description:PutstheADS1218intoalowpowersleepmode.
To exit sleep mode strobe SCLK.
SYSOCAL System Offset Calibration
Description: Starts the system offset calibration process. For
a system offset calibration the input should be set to 0V
differential, and the ADS1218 computes the OCR register
value that will compensate for offset errors. The Offset
Control Register (OCR) is updated after this operation.
Operands: None
Bytes:
1
Encoding: 1111 1101
Data Transfer Sequence:
Operands: None
Bytes:
1
DIN
1111 1101
xxxx xxxx
Encoding: 1111 0011
Data Transfer Sequence:
DOUT
1111 0011
xxxx xxxx
DIN
RESET
Reset to Powerup Values
Description: Restore the registers to their power-up values.
This command will also stop the Read Continuous mode. It
does not affect the contents of RAM.
DOUT
Operands: None
SYSGCAL System Gain Calibration
Bytes:
1
Description: Starts the system gain calibration process. For a
system gain calibration, the differential input should be set to
the reference voltage and the ADS1218 computes the FSR
register value that will compensate for gain errors. The FSR is
updated after this operation.
Encoding: 1111 1110
Data Transfer Sequence:
1111 1110
xxxx xxxx
DIN
Operands: None
Bytes:
1
DOUT
Encoding: 1111 0100
Data Transfer Sequence:
1111 0100
xxxx xxxx
DIN
DOUT
ADS1218
23
SBAS187
LSB
0000
x
MSB
0000
0001
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
rdata
x
rdatac
x
x
x
x
x
x
x
x
x
x
x
stopc
rreg
0
rreg
1
rreg
2
rreg
3
rreg
4
rreg
5
rreg
6
rreg
7
rreg
8
rreg
9
rreg
A
rreg
B
rreg
C
rreg
D
rreg
E
rreg
F
0010
rram
0
rram
1
rram
2
rram
3
rram
4
rram
5
rram
6
rram
7
x
x
x
x
x
x
x
x
0011
0100
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
creg
0
creg
1
creg
2
creg
3
creg
4
creg
5
creg
6
creg
7
crega
0101
0110
wreg
0
wreg
1
wreg
2
wreg
3
wreg
4
wreg
5
wreg
6
wreg
7
wreg
8
wreg
9
wreg
A
wreg
B
wreg
C
wreg
D
wreg
E
wreg
F
wram
0
wram
1
wram
2
wram
3
wram
4
wram
5
wram
6
wram
7
x
x
x
x
x
x
x
x
0111
1000
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
rf2r
0
rf2r
1
rf2r
2
rf2r
3
rf2r
4
rf2r
5
rf2r
6
rf2r
7
rf2r
8
rf2r
9
rf2r
A
rf2r
B
rf2r
C
rf2r
D
rf2r
E
rf2r
F
1001
1010
1011
rf2r
10
rf2r
11
rf2r
12
rf2r
13
rf2r
14
rf2r
15
rf2r
16
rf2r
17
rf2r
18
rf2r
19
rf2r
1A
rf2r
1B
rf2r
1C
rf2r
1D
rf2r
1E
rf2r
1F
wr2f
0
wr2f
1
wr2f
2
wr2f
3
wr2f
4
wr2f
5
wr2f
6
wr2f
7
wr2f
8
wr2f
9
wr2f
A
wr2f
B
wr2f
C
wr2f
D
wr2f
E
wr2f
F
wr2f
10
wr2f
11
wr2f
12
wr2f
13
wr2f
14
wr2f
15
wr2f
16
wr2f
17
wr2f
18
wr2f
19
wr2f
1A
wr2f
1B
wr2f
1C
wr2f
1D
wr2f
1E
wr2f
1F
1100 cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1101
csreg
csramx csramx csramx csramx csramx csramx csramx csramx csramx
0
1
2
3
4
5
6
7
1110
1111
x
x
x
x
x
x
csfl
x
x
x
x
csram 0 csram 1 csram2 csram 3 csram 4 csram 5 csram 6 csram 7 csram
self
cal
self
ocal
self
gcal
sys
ocal
sys
gcal
x
x
x
x
dsync
sleep
reset
x = Reserved
TABLE IV. ADS1218 Command Map.
ADS1218
24
SBAS187
SERIAL PERIPHERAL INTERFACE
CS is used to select the device. It can be used to decode the
ADS1218 in systems where a number of parts are connected
to the serial bus.
The Serial Peripheral Interface (SPI), allows a controller to
communicate synchronously with the ADS1218. The
ADS1218 operates in slave only mode.
The timing specification shows the timing diagram for
interfacing to the ADS1218 with CS used to decode the part.
SPI Transfer Formats
The ADS1218 serial interface can operate in three-wire
mode by tying the CS input LOW. In this case, the SCLK,
DIN, and DOUT lines are used to communicate with the
ADS1218 and the status of DRDY can be obtained by
interrogating bit 7 of the M/DEC1 register. This scheme is
suitable for interfacing to microcontrollers. If CS is required
as a decoding signal, it can be generated from a port pin.
During an SPI transfer, data is simultaneously transmitted
and received. The SCLK signal synchronizes shifting and
sampling of the information on the two serial data lines: DIN
and DOUT. The CS signal allows individual selection of an
ADS1218 device; an ADS1218 with CS HIGH is not active
on the bus.
Clock Phase and Polarity Controls (POL)
The clock polarity is specified by the POL pin, which selects
an active HIGH or active LOW clock, and has no effect on
the transfer format.
DEFINITION OF TERMS
Analog Input Voltage—the voltage at any one analog input
relative to AGND.
Serial Clock (SCLK)
Analog Input Differential Voltage—given by the following
equation: (IN+ – IN–). Thus, a positive digital output is pro-
duced whenever the analog input differential voltage is posi-
tive, while a negative digital output is produced whenever the
differential is negative.
SCLK, a Schmitt Trigger input to the ADS1218, is gener-
ated by the master device and synchronizes data transfer on
the DIN and DOUT lines. When transferring data to or from
the ADS1218, burst mode may be used i.e., multiple bits of
data may be transferred back-to-back with no delay in
SCLKs or toggling of CS.
For example, when the converter is configured with a 2.5V
reference and placed in a gain setting of 1, the positive
full-scale output is produced when the analog input differen-
tial is 2.5V. The negative full-scale output is produced when
the differential is –2.5V. In each case, the actual input
voltages must remain within the AGND to AVDD range.
Chip Select (CS)
The chip select (CS) input of the ADS1218 must be exter-
nally asserted before a master device can exchange data with
the ADS1218. CS must be LOW before data transactions
and must stay LOW for the duration of the transaction.
Conversion Cycle—the term “conversion cycle” usually
refers to a discrete A/D conversion operation, such as that
performed by a successive approximation converter. As
used here, a conversion cycle refers to the tDATA time period.
However, each digital output is actually based on the modu-
lator results from several tDATA time periods.
DIGITAL INTERFACE
The ADS1218’s programmable functions are controlled
using a set of on-chip registers, as outlined previously. Data
is written to these registers via the part’s serial interface and
read access to the on-chip registers is also provided by this
interface.
FILTER SETTING
fast settling
sinc2
MODULATOR RESULTS
1 tDATA time period
2 tDATA time period
3 tDATA time period
The ADS1218’s serial interface consists of four signals: CS,
SCLK, DIN, and DOUT. The DIN line is used for transferring
data into the on-chip registers while the DOUT line is used for
accessing data from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on
DIN or DOUT) take place with respect to this SCLK signal.
sinc3
Data Rate—The rate at which conversions are completed.
See definition for fDATA
.
The DRDY line is used as a status signal to indicate when
data is ready to be read from the ADS1218’s data register.
DRDY goes LOW when a new data word is available in the
DOR register. It is reset HIGH when a read operation from
the data register is complete. It also goes HIGH prior to the
updating of the output register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated.
Decimation Ratio—defines the ratio between the output of
the modulator and the output Data Rate. Valid values for the
Decimation Ratio are from 20 to 2047. Larger Decimation
Ratios will have lower noise and vice-versa.
ADS1218
25
SBAS187
Effective Resolution—the effective resolution of the
ADS1218 in a particular configuration can be expressed in
two different units: bits rms (referenced to output) and Vrms
(referenced to input). Computed directly from the converter’s
output data, each is a statistical calculation. The conversion
from one to the other is shown below.
fSAMP—the frequency, or switching speed, of the input
sampling capacitor. The value is given by one of the follow-
ing equations:
PGA SETTING
SAMPLING FREQUENCY
fOSC
1, 2, 4, 8
fSAMP
fSAMP
fSAMP
=
=
=
mfactor
OSC • 2
mfactor
OSC • 4
mfactor
f
16
32
BITS rms
BIPOLAR Vrms
UNIPOLAR Vrms
2 • VREF
VREF
f
PGA
6.02•ER
PGA
6.02•ER
20
20
f
OSC • 8
10
10
64, 128
fSAMP
=
mfactor
24
22
20
18
16
14
12
298nV
1.19µV
4.77µV
19.1µV
76.4µV
505µV
1.22mV
149nV
597nV
2.39µV
9.55µV
38.2µV
152.7µV
610µV
fDATA—the frequency of the digital output data produced by
the ADS1218, fDATA is also referred to as the Data Rate.
fMOD
fOSC
fDATA
=
=
Decimation Ratio
mfactor • Decimation Ratio
Filter Selection—the ADS1218 uses a (sinx /x) filter or sinc
filter. Actually there are three different sinc filters that can
be selected. A fast settling filter will settle in one tDATA
cycle. The sinc2 filter will settle in two cycles and have
lower noise. The sinc3 will achieve the lowest noise and
highest number of effective bits, but requires three cycles to
settle. The ADS1218 will operate with any one of these
filters, or it can operate in an auto mode, where it will select
the fast settling filter after a new channel is selected and will
then switch to sinc2 followed by sinc3. This allows fast
settling response and still achieves low noise after the
necessary number of tDATA cycles.
Full-Scale Range (FSR)—as with most A/D converters, the
full-scale range of the ADS1218 is defined as the “input”,
which produces the positive full-scale digital output minus
the “input”, which produces the negative full-scale digital
output. The full-scale range changes with gain setting as
shown in Table V.
For example, when the converter is configured with a 2.5V
reference and is placed in a gain setting of 2, the full-scale
range is: [1.25V (positive full-scale) minus –1.25V (nega-
tive full-scale)] = 2.5V.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
input would have to change in order to observe a change in
the output data of one least significant bit. It is computed as
follows:
fOSC—the frequency of the crystal oscillator or CMOS
compatible input signal at the XIN input of the ADS1218.
fMOD—the frequency or speed at which the modulator of the
ADS1218 is running. This depends on the SPEED bit as
given by the following equation:
Full
−
Scale Range
2N
LSB Weight =
where N is the number of bits in the digital output.
DATA—the inverse of fDATA, or the period between each
data output.
SPEED = 0
SPEED = 1
mfactor
128
256
t
fOSC
mfactor
fMOD
=
5V SUPPLY ANALOG INPUT(1)
GENERAL EQUATIONS
DIFFERENTIAL
FULL-SCALE RANGE INPUT VOLTAGES(2)
PGA OFFSET
FULL-SCALE
RANGE
DIFFERENTIAL
INPUT VOLTAGES(2)
PGA SHIFT
RANGE
GAIN SETTING
RANGE
2 • VREF
±VREF
±VREF
1
2
5V
±2.5V
±1.25V
±0.625V
PGA
PGA
2 • PGA
2.5V
±1.25V
4
1.25V
±0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
±9.766mV
8
0.625V
±312.5mV
±156.25mV
±78.125mV
±39.0625mV
±19.531mV
16
32
64
128
312.5mV
156.25mV
78.125mV
39.0625mV
NOTES: (1) With a 2.5V reference. (2) The ADS1218 allows common-mode voltage as long as the absolute input voltage on AINP or AINN does not go below
AGND or above AVDD
.
TABLE V. Full-Scale Range versus PGA Setting.
ADS1218
26
SBAS187
TOPIC INDEX
TOPIC
PAGE
ABSOLUTE MAXIMUM RATINGS ..........................................................................................................................2
PACKAGE AND ORDERING INFORMATION........................................................................................................2
ELECTRICAL CHARACTERISTICS (AVDD = 5V) ..................................................................................................2
ELECTRICAL CHARACTERISTICS (AVDD = 3V) ..................................................................................................4
PIN CONFIGURATION ............................................................................................................................................6
TIMING SPECIFICATIONS ......................................................................................................................................7
TYPICAL CHARACTERISTICS ...............................................................................................................................8
OVERVIEW.............................................................................................................................................................12
MEMORY ................................................................................................................................................................15
REGISTER BANK TOPOLOGY ............................................................................................................................15
DETAILED REGISTER DEFINITIONS ..................................................................................................................17
COMMAND DEFINITIONS .....................................................................................................................................19
ADS1218 COMMAND MAP...................................................................................................................................24
SERIAL PERIPHERAL INTERFACE.....................................................................................................................25
DIGITAL INTERFACE ............................................................................................................................................25
DEFINITION OF TERMS........................................................................................................................................25
ADS1218
27
SBAS187
PACKAGE DRAWING
PFB (S-PQFP-G48)
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
M
0,08
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
ADS1218
28
SBAS187
PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
ADS1218Y/250
ADS1218Y/2K
ACTIVE
ACTIVE
TQFP
TQFP
PFB
PFB
48
48
250
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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相关型号：
ADS1218Y/250G4
24-Bit, 780SPS ADC w/ Flash Memory, 8 Ch, VREF, Buffer, 2 IDACs, Serial Out, Digital I/O, Low Power 48-TQFP -40 to 85
TI
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