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ADS1218Y250 [TI]

8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory; 8通道，24位模拟数字转换器与FLASH存储器
ADS1218Y250
型号： ADS1218Y250
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

8-Channel, 24-Bit ANALOG-TO-DIGITAL CONVERTER with FLASH Memory
8通道，24位模拟数字转换器与FLASH存储器

转换器 存储
文件： 总44页 (文件大小：849K)
中文：  中文翻译
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ADS1218  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
8-Channel, 24-Bit  
ANALOG-TO-DIGITAL CONVERTER with FLASH Memory  
The eight input channels are multiplexed. Internal  
FEATURES  
buffering can be selected to provide a very high input  
impedance for direct connection to transducers or  
low-level voltage signals. Burnout current sources are  
provided that allow for the detection of an open or  
shorted sensor. An 8-bit Digital-to-Analog (D/A)  
converter provides an offset correction with a range  
of 50% of the FSR (Full-Scale Range).  
•
•
•
24 BITS NO MISSING CODES  
0.0015% INL  
22 BITS EFFECTIVE RESOLUTION (PGA = 1),  
19 BITS (PGA = 128)  
•
4K BYTES OF FLASH MEMORY  
PROGRAMMABLE FROM 2.7V TO 5.25V  
The PGA (Programmable Gain Amplifier) provides  
selectable gains of 1 to 128 with an effective  
resolution of 19 bits at a gain of 128. The A/D  
conversion is accomplished with a second-order  
delta-sigma modulator and programmable sinc filter.  
The reference input is differential and can be used for  
ratiometric conversion. The on-board current DACs  
(Digital-to-Analog Converters) operate independently  
with the maximum current set by an external resistor.  
•
•
•
PGA FROM 1 TO 128  
SINGLE CYCLE SETTLING MODE  
PROGRAMMABLE DATA OUTPUT RATES UP  
TO 1kHz  
•
•
PRECISION ON-CHIP 1.25V/2.5V REFERENCE:  
ACCURACY: 0.2%  
DRIFT: 5ppm/°C  
EXTERNAL DIFFERENTIAL REFERENCE OF  
0.1V TO 2.5V  
The serial interface is SPI-compatible. Eight bits of  
digital I/O are also provided that can be used for input  
or output. The ADS1218 is designed for  
high-resolution measurement applications in smart  
transmitters, industrial process control, weight scales,  
chromatography, and portable instrumentation.  
•
•
•
•
•
ON-CHIP CALIBRATION  
PIN-COMPATIBLE WITH ADS1216  
SPI™ COMPATIBLE  
2.7V TO 5.25V  
AGND AVDD  
RDAC  
VREFOUT  
VRCAP  
VREF+  
VREF−  
XIN  
XOUT  
< 1mW POWER CONSUMPTION  
8−Bit  
IDAC  
IDAC2  
IDAC1  
Clock Generator  
1.25V or  
2.5V  
Reference  
APPLICATIONS  
8−Bit  
IDAC  
•
•
•
•
•
•
•
INDUSTRIAL PROCESS CONTROL  
LIQUID/GAS CHROMATOGRAPHY  
BLOOD ANALYSIS  
SMART TRANSMITTERS  
PORTABLE INSTRUMENTATION  
WEIGHT SCALES  
Offset  
DAC  
AIN  
AIN  
AIN  
AIN  
AIN  
AIN  
AIN  
AIN  
0
1
2
3
4
5
6
7
Registers  
RAM  
Program−  
mable  
2nd−Order  
Modulator  
MUX  
+
Controller  
BUF  
PGA  
Digital  
Filter  
4K Bytes  
FLASH  
WREN  
POL  
PRESSURE TRANSDUCERS  
AINCOM  
SCLK  
DIN  
DESCRIPTION  
Serial Interface  
RESET DRDY  
Digital I/O  
Interface  
DOUT  
CS  
The ADS1218 is a precision, wide dynamic range,  
delta-sigma, Analog-to-Digital (A/D) converter with  
24-bit resolution and Flash memory operating from  
2.7V to 5.25V supplies. The delta-sigma, A/D  
converter provides up to 24 bits of no missing code  
performance and effective resolution of 22 bits.  
DVDD  
DGND BUFEN  
D0 ... D7  
PDWN DSYNC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SPI is a trademark of Motorola.  
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2001–2005, Texas Instruments Incorporated  
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated  
circuits be handled with appropriate precautions. Failure to observe proper handling and installation  
procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision  
integrated circuits may be more susceptible to damage because very small parametric changes could  
cause the device not to meet its published specifications.  
ORDERING INFORMATION  
For the most current package and ordering information, see the Package Option Addendum at the end of this  
document, or see the TI web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS(1)  
AVDD to AGND  
–0.3V to +6V  
–0.3V to +6V  
DVDD to DGND  
Input Current  
100mA, Momentary  
10mA, Continuous  
GND – 0.5V to AVDD + 0.5V  
–6V to +6V  
Input Current  
AIN  
AVDD to DVDD  
AGND to DGND  
–0.3V to +0.3V  
Digital Input Voltage to GND  
Digital Output Voltage to GND  
Maximum Junction Temperature  
Operating Temperature Range  
Storage Temperature Range  
Lead Temperature (soldering, 10s)  
–0.3V to DVDD + 0.3V  
–0.3V to DVDD + 0.3V  
+150°C  
–40°C to +85°C  
–60°C to +100°C  
+300°C  
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute  
maximum conditions for extended periods may affect device reliability.  
2
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
ELECTRICAL CHARACTERISTICS: AVDD = 5V  
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On,  
RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified.  
ADS1218  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ANALOG INPUT (AIN0 – AIN7, AINCOM  
)
Analog Input Range  
Buffer Off  
Buffer On  
AGND – 0.1  
AVDD + 0.1  
AVDD – 1.5  
±VREF/PGA  
V
V
AGND + 0.05  
Full-Scale Input Voltage Range  
Differential Input Impedance  
Input Current  
(In+) – (In–), See Block Diagram  
Buffer Off  
V
5/PGA  
0.5  
MΩ  
nA  
Buffer On  
Bandwidth  
Fast Settling Filter  
Sinc2 Filter  
–3dB  
0.469 × fDATA  
0.318 × fDATA  
0.262 × fDATA  
Hz  
Hz  
Hz  
–3dB  
–3dB  
Sinc3 Filter  
Programmable Gain Amplifier  
Input Capacitance  
Input Leakage Current  
Burnout Current Sources  
OFFSET DAC  
User-Selectable Gain Ranges  
1
128  
9
5
2
pF  
pA  
µA  
Modulator Off, T = +25°C  
Offset DAC Range  
Offset DAC Monotonicity  
Offset DAC Gain Error  
Offset DAC Gain Error Drift  
SYSTEM PERFORMANCE  
Resolution  
±VREF/(2 × PGA)  
V
Bits  
8
±10  
1
%
ppm/°C  
24  
Bits  
sinc3  
No Missing Codes  
Integral Nonlinearity  
Offset Error(1)  
24  
Bits  
End Point Fit  
Before Calibration  
±0.0015  
% of FS  
7.5  
0.02  
0.005  
0.5  
ppm of FS  
Offset Drift(1)  
ppm of FS/°C  
Gain Error  
After Calibration  
%
ppm/°C  
dB  
Gain Error Drift(1)  
Common-Mode Rejection  
at DC  
100  
fCM = 60Hz, fDATA = 10Hz  
fCM = 50Hz, fDATA = 50Hz  
fCM = 60Hz, fDATA = 60Hz  
fSIG = 50Hz, fDATA = 50Hz  
fSIG = 60Hz, fDATA = 60Hz  
130  
120  
120  
100  
100  
dB  
dB  
dB  
Normal-Mode Rejection  
dB  
dB  
Output Noise  
See Typical Characteristics  
95  
(2)  
Power-Supply Rejection  
VOLTAGE REFERENCE INPUT  
Reference Input Range  
VREF  
at DC, dB = –20 log(∆VOUT/∆VDD  
)
80  
dB  
REF IN+, REF IN–  
0
AVDD  
2.6  
V
VREF ≡ (REF IN+) – (REF IN–)  
at DC  
0.1  
2.5  
120  
120  
1.3  
V
Common-Mode Rejection  
Common-Mode Rejection  
Bias Current(3)  
dB  
dB  
µA  
fVREFCM = 60Hz, fDATA = 60Hz  
VREF = 2.5V  
(1) Calibration can minimize these errors.  
(2) ∆VOUT is change in digital result.  
(3) 12pF switched capacitor at fSAMP clock frequency.  
3
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued)  
All specifications TMIN to TMAX, AVDD = +5V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On,  
RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and fDATA = 10Hz, unless otherwise specified.  
ADS1218  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ON-CHIP VOLTAGE REFERENCE  
Output Voltage  
REF HI = 1 at +25°C  
REF HI = 0  
2.495  
2.50  
2.505  
V
V
1.25  
Short-Circuit Current Source  
Short-Circuit Current Sink  
Short-Circuit Duration  
Drift  
8
mA  
µA  
50  
Sink or Source  
Indefinite  
5
10  
3
ppm/°C  
µVPP  
Ω
Noise  
BW = 0.1Hz to 100Hz  
Sourcing 100µA  
Output Impedance  
Startup Time  
50  
µs  
IDAC  
Full-Scale Output Current  
RDAC = 150kΩ, Range = 1  
RDAC = 150kΩ, Range = 2  
RDAC = 150kΩ, Range = 3  
RDAC = 15kΩ, Range = 3  
RDAC = 10kΩ  
0.5  
mA  
mA  
mA  
mA  
1
2
20  
Maximum Short-Circuit Current Duration  
Indefinite  
RDAC = 0Ω  
10  
Minutes  
Bits  
Monotonicity  
RDAC = 150kΩ  
8
0
Compliance Voltage  
Output Impedance  
PSRR  
AVDD – 1  
V
See Typical Characteristics  
VOUT = AVDD/2  
Individual IDAC  
400  
5
ppm/V  
%
Absolute Error  
Absolute Drift  
Individual IDAC  
75  
ppm/°C  
%
Mismatch Error  
Between IDACs, Same Range and Code  
Between IDACs, Same Range and Code  
0.25  
15  
Mismatch Drift  
ppm/°C  
POWER-SUPPLY REQUIREMENTS  
Power-Supply Voltage  
AVDD  
4.75  
5.25  
V
Analog Current (IADC + IVREF + IDAC  
)
PDWN = 0, or SLEEP  
PGA = 1, Buffer Off  
PGA = 128, Buffer Off  
PGA = 1, Buffer On  
PGA = 128, Buffer On  
1
nA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
nA  
ADC Current (IADC  
)
175  
500  
250  
900  
250  
480  
180  
150  
230  
1
275  
750  
350  
1375  
375  
675  
275  
VREF Current (IVREF  
IDAC Current (IDAC  
Digital Current  
)
)
Excludes Load Current  
Normal Mode, DVDD = 5V  
SLEEP Mode, DVDD = 5V  
Read Data Continuous Mode, DVDD = 5V  
PDWN = Low  
PGA = 1, Buffer Off, REFEN = 0,  
IDACS Off, DVDD = 5V  
Power Dissipation  
1.8  
2.8  
mW  
TEMPERATURE RANGE  
Operating  
–40  
–60  
+85  
°C  
°C  
Storage  
+100  
4
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
ELECTRICAL CHARACTERISTICS: AVDD = 3V  
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On,  
RDAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified.  
ADS1218  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ANALOG INPUT (AIN0 – AIN7, AINCOM  
)
Analog Input Range  
Buffer Off  
Buffer On  
AGND – 0.1  
AVDD + 0.1  
AVDD – 1.5  
±VREF/PGA  
V
V
AGND + 0.05  
Full-Scale Input Voltage Range  
Input Impedance  
(In+) – (In–), See Block Diagram  
Buffer Off  
V
5/PGA  
0.5  
MΩ  
nA  
Input Current  
Buffer On  
Bandwidth  
Fast Settling Filter  
Sinc2 Filter  
–3dB  
0.469 × fDATA  
0.318 × fDATA  
0.262 × fDATA  
Hz  
Hz  
Hz  
–3dB  
–3dB  
Sinc3 Filter  
Programmable Gain Amplifier  
Input Capacitance  
Input Leakage Current  
Burnout Current Sources  
OFFSET DAC  
User-Selectable Gain Ranges  
1
128  
9
5
2
pF  
pA  
µA  
Modulator Off, T = +25°C  
Offset DAC Range  
Offset DAC Monotonicity  
Offset DAC Gain Error  
Offset DAC Gain Error Drift  
SYSTEM PERFORMANCE  
Resolution  
±VREF/(2 × PGA)  
V
Bits  
8
±10  
2
%
ppm/°C  
24  
Bits  
No Missing Codes  
Integral Nonlinearity  
Offset Error(1)  
24  
Bits  
End Point Fit  
±0.0015  
% of FS  
Before Calibration  
15  
0.04  
0.010  
1.0  
ppm of FS  
Offset Drift(1)  
ppm of FS/°C  
Gain Error  
After Calibration  
%
ppm/°C  
dB  
Gain Error Drift(1)  
Common-Mode Rejection  
at DC  
100  
fCM = 60Hz, fDATA = 10Hz  
fCM = 50Hz, fDATA = 50Hz  
fCM = 60Hz, fDATA = 60Hz  
fSIG = 50Hz, fDATA = 50Hz  
fSIG = 60Hz, fDATA = 60Hz  
130  
120  
120  
100  
100  
dB  
dB  
dB  
Normal-Mode Rejection  
dB  
dB  
Output Noise  
See Typical Characteristics  
90  
(2)  
Power-Supply Rejection  
VOLTAGE REFERENCE INPUT  
Reference Input Range  
VREF  
at DC, dB = –20 log(∆VOUT/∆VDD  
)
75  
dB  
REF IN+, REF IN–  
0
AVDD  
1.25  
V
VREF ≡ (REF IN+) – (REF IN–)  
at DC  
0.1  
V
Common-Mode Rejection  
Common-Mode Rejection  
Bias Current(3)  
120  
120  
0.65  
dB  
dB  
µA  
fVREFCM = 60Hz, fDATA = 60Hz  
VREF = 1.25V  
(1) Calibration can minimize these errors.  
(2) ∆VOUT is change in digital result.  
(3) 12pF switched capacitor at fSAMP clock frequency.  
5
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
ELECTRICAL CHARACTERISTICS: AVDD = 3V (continued)  
All specifications TMIN to TMAX, AVDD = +3V, DVDD = +2.7V to 5.25V, fMOD = 19.2kHz, fOSC = 2.4576MHz, PGA = 1, Buffer On,  
RDAC = 75kΩ, VREF ≡ (REF IN+) – (REF IN–) = +1.25V, and fDATA = 10Hz, unless otherwise specified.  
ADS1218  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
ON-CHIP VOLTAGE REFERENCE  
Output Voltage  
REF HI = 0 at +25°C  
1.245  
1.25  
1.255  
V
Short-Circuit Current Source  
Short-Circuit Current Sink  
Short-Circuit Duration  
Drift  
3
mA  
µA  
50  
Sink or Source  
Indefinite  
5
10  
3
ppm/°C  
µVPP  
Ω
Noise  
BW = 0.1Hz to 100Hz  
Sourcing 100µA  
Output Impedance  
Startup Time  
50  
µs  
IDAC  
Full-Scale Output Current  
RDAC = 75kΩ, Range = 1  
RDAC = 75kΩ, Range = 2  
RDAC = 75kΩ, Range = 3  
RDAC = 15kΩ, Range = 3  
RDAC = 10kΩ  
0.5  
mA  
mA  
mA  
mA  
1
2
20  
Maximum Short-Circuit Current Duration  
Indefinite  
RDAC = 0Ω  
10  
Minutes  
Bits  
Monotonicity  
RDAC = 75kΩ  
8
0
Compliance Voltage  
Output Impedance  
PSRR  
AVDD – 1  
V
See Typical Characteristics  
VOUT = AVDD/2  
Individual IDAC  
600  
5
ppm/V  
%
Absolute Error  
Absolute Drift  
Individual IDAC  
75  
ppm/°C  
%
Mismatch Error  
Between IDACs, Same Range and Code  
Between IDACs, Same Range and Code  
0.25  
15  
Mismatch Drift  
ppm/°C  
POWER-SUPPLY REQUIREMENTS  
Power-Supply Voltage  
AVDD  
2.7  
3.3  
V
Analog Current (IADC + IVREF + IDAC  
)
PDWN = 0, or SLEEP  
PGA = 1, Buffer Off  
PGA = 128, Buffer Off  
PGA = 1, Buffer On  
PGA = 128, Buffer On  
1
nA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
nA  
ADC Current (IADC  
)
160  
450  
230  
850  
250  
480  
90  
250  
700  
325  
1325  
375  
675  
200  
VREF Current (IVREF  
IDAC Current (IDAC  
Digital Current  
)
)
Excludes Load Current  
Normal Mode, DVDD = 3V  
SLEEP Mode, DVDD = 3V  
Read Data Continuous Mode, DVDD = 3V  
PDWN = 0  
75  
113  
1
PGA = 1, Buffer Off, REFEN = 0,  
IDACS Off, DVDD = 3V  
Power Dissipation  
0.8  
1.4  
mW  
TEMPERATURE RANGE  
Operating  
–40  
–60  
+85  
°C  
°C  
Storage  
+100  
6
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
DIGITAL CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Digital Input/Output  
Logic Family  
CMOS  
Logic Level  
VIH  
0.8 × DVDD  
DGND  
DVDD  
V
V
V
V
VIL  
0.2 × DVDD  
VOH  
IOH = 1mA  
IOL = 1mA  
DVDD – 0.4  
DGND  
VOL  
DGND + 0.4  
10  
Input Leakage  
IIH  
VI = DVDD  
VI = 0  
µA  
µA  
IIL  
–10  
1
(1)  
Master Clock Rate: fOSC  
5
MHz  
ns  
(1)  
Master Clock Period: tOSC  
1/fOSC  
200  
1000  
(1) For the Write RAM to Flash operation (WR2F), the SPEED bit in the SETUP register must be set appropriately and the device operating  
frequency must be: 2.3MHz < fOSC < 4.13MHz.  
FLASH CHARACTERISTICS: TMIN to TMAX, DVDD = 2.7V to 5.25V, unless otherwise specified.  
PARAMETER  
Operating Current  
Page Write  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DVDD = 5V, During WR2F Command  
DVDD = 3V, During WR2F Command  
DVDD = 5V, During RF2R Command  
DVDD = 3V, During RF2R Command  
17  
mA  
mA  
9
Page Read  
8
2
mA  
mA  
Endurance  
100,000  
Write Cycles  
Years  
V
Data Retention  
DVDD for Erase/Write  
at +25°C  
100  
2.7  
5.25  
7
ADS1218  
www.ti.com  
SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
PIN CONFIGURATION  
Top View  
TQFP  
36 35 34 33 32 31 30 29 28 27 26 25  
D0 37  
38  
24 RESET  
23  
D1  
BUFEN  
D2 39  
D3 40  
22 DGND  
21 DGND  
41  
20  
D4  
DGND  
D5 42  
19 DGND  
ADS1218  
43  
44  
45  
18  
17  
16  
D6  
D7  
WREN  
RDAC  
AGND  
IDAC2  
VREFOUT 46  
47  
15 IDAC1  
14  
VREF+  
VREF− 48  
VRCAP  
13 AVDD  
1
2
3
4
5
6
7
8
9
10 11 12  
PIN DESCRIPTIONS  
PIN  
PIN  
NUMBER NAME DESCRIPTION  
NUMBER NAME DESCRIPTION  
1
2
3
4
AVDD  
Analog Power Supply  
24  
25  
26  
RESET Active Low, resets the entire chip.  
AGND Analog Ground  
XIN  
Clock Input  
AIN  
0
1
Analog Input 0  
Analog Input 1  
XOUT  
Clock Output, used with crystal or resonator.  
Active Low. Power Down. The power-down  
AIN  
27  
PDWN function shuts down the analog and digital  
circuits.  
5
AIN2  
Analog Input 2  
6
7
AIN  
AIN  
AIN  
AIN  
AIN  
3
4
5
6
7
Analog Input 3  
Analog Input 4  
Analog Input 5  
Analog Input 6  
Analog Input 7  
28  
29  
POL  
Serial Clock Polarity  
DSYNC Active Low, Synchronization Control  
DGND Digital Ground  
8
30  
9
31  
DVDD  
DRDY  
CS  
Digital Power Supply  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19–22  
23  
32  
Active Low, Data Ready  
Active Low, Chip Select  
Serial Clock, Schmitt Trigger  
Serial Data Input, Schmitt Trigger  
Serial Data Output  
AINCOM Analog Input Common  
AGND Analog Ground  
33  
34  
SCLK  
DIN  
AVDD  
Analog Power Supply  
VREF Bypass CAP  
35  
VRCAP  
36  
DOUT  
IDAC1 Current DAC1 Output  
IDAC2 Current DAC2 Output  
37–44  
45  
D0-D7 Digital I/O 0–7  
AGND Analog Ground  
RDAC  
Current DAC Resistor  
46  
VREFOUT Voltage Reference Output  
WREN Active High, Flash Write Enable  
DGND Digital Ground  
47  
VREF+  
VREF–  
Positive Differential Reference Input  
Negative Differential Reference Input  
48  
BUFEN Buffer Enable  
8
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
TIMING SPECIFICATIONS  
CS  
t3  
SCLK  
t1  
t2  
t10  
(POL = 0)  
SCLK  
(POL = 1)  
t4  
t2  
t6  
t5  
t11  
DIN  
MSB  
LSB  
t7  
t8  
t9  
(Command or Command and Data)  
MSB(1)  
LSB(1)  
DOUT  
NOTE: (1) Bit Order = 0.  
TIMING SPECIFICATION TABLE  
SPEC  
DESCRIPTION  
MIN  
MAX  
UNIT  
t1  
SCLK Period  
4
tOSC Periods  
3
DRDY Periods  
t2  
t3  
t4  
t5  
t6  
SCLK Pulse Width, High and Low  
CS Low to first SCLK Edge; Setup Time  
DIN Valid to SCLK Edge; Setup Time  
Valid DIN to SCLK Edge; Hold Time  
Delay between last SCLK edge for DIN and first SCLK edge for DOUT  
RDATA, RDATAC, RREG, WREG, RRAM  
CSREG, CSRAMX, CSRAM  
200  
0
ns  
ns  
ns  
ns  
50  
50  
:
50  
tOSC Periods  
tOSC Periods  
tOSC Periods  
ns  
200  
CSARAM, CSARAMX  
1100  
(1)  
t7  
SCLK Edge to Valid New DOUT  
50  
10  
(1)  
t8  
SCLK Edge to DOUT, Hold Time  
0
6
ns  
t9  
Last SCLK Edge to DOUT Tri-State  
tOSC Periods  
NOTE: DOUT goes tri-state immediately when CS goes High.  
t10  
t11  
CS Low time after final SCLK edge  
0
4
ns  
Final SCLK edge of one op code until first edge SCLK of next command:  
RREG, WREG, RRAM, WRAM, CSRAMX, CSARAMX, CSRAM, CSARAM,  
CSREG, SLEEP, RDATA, RDATAC, STOPC  
tOSC Periods  
DSYNC  
CSFL  
16  
33,000  
220  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
DRDY Periods  
DRDY Periods  
tOSC Periods  
CREG, CRAM  
RF2R  
1090  
1600  
CREGA  
WR2F  
76,850 (SPEED = 0)  
101,050 (SPEED = 1)  
4
SELFGCAL, SELFOCAL, SYSOCAL, SYSGCAL  
SELFCAL  
7
14  
RESET (Command, SCLK, or Pin)  
2640  
(1) Load = 20pF | | 10kΩ to DGND.  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
ADS1218  
Resets On Falling Edge  
SCLK Reset Waveform  
t13  
t13  
SCLK  
DRDY  
t16  
t12  
t14  
t15  
t17  
RESET, DSYNC, PDWN  
TIMING SPECIFICATION TABLE  
SPEC  
DESCRIPTION  
MIN  
300  
5
MAX  
UNIT  
t12  
SCLK Reset, First High Pulse  
SCLK Reset, Low Pulse  
SCLK Reset, Second High Pulse  
SCLK Reset, Third High Pulse  
Pulse Width  
500  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
tOSC Periods  
t13  
t14  
550  
1050  
4
750  
t15  
1250  
t16  
t17  
Data Not Valid During this Update Period  
4
10  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
TYPICAL CHARACTERISTICS  
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and  
fDATA = 10Hz, unless otherwise specified.  
EFFECTIVE NUMBER OF BITS  
vs DECIMATION RATIO  
EFFECTIVE NUMBER OF BITS  
vs DECIMATION RATIO  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
PGA1  
PGA4  
PGA2  
PGA8  
PGA1  
PGA4  
PGA2  
PGA8  
PGA16 PGA32  
PGA64  
PGA128  
PGA32  
PGA64  
PGA128  
PGA16  
Sinc3 Filter, Buffer ON  
Sinc3 Filter  
0
500  
1000  
1500  
fMOD  
2000  
0
500  
1000  
1500  
fMOD  
2000  
Decimation Ratio =  
Decimation Ratio =  
fDATA  
fDATA  
Figure 1.  
Figure 2.  
EFFECTIVE NUMBER OF BITS  
vs DECIMATION RATIO  
EFFECTIVE NUMBER OF BITS  
vs DECIMATION RATIO  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
PGA1  
PGA4  
PGA2  
PGA8  
PGA1  
PGA2  
PGA4  
PGA8  
PGA64  
PGA128  
PGA32  
PGA16  
PGA32  
PGA64  
PGA128  
Sinc3 Filter, VREF = 1.25V, Buffer OFF  
PGA16  
Sinc3 Filter, VREF = 1.25V, Buffer ON  
0
500  
1000  
1500  
fMOD  
2000  
0
500  
1000  
1500  
fMOD  
2000  
Decimation Ratio =  
Decimation Ratio =  
fDATA  
fDATA  
Figure 3.  
Figure 4.  
11  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
TYPICAL CHARACTERISTICS (continued)  
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and  
fDATA = 10Hz, unless otherwise specified.  
EFFECTIVE NUMBER OF BITS  
vs DECIMATION RATIO  
FAST SETTLING FILTER  
EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
22  
PGA1  
PGA2  
PGA4  
PGA8  
21  
20  
19  
18  
17  
16  
15  
14  
13  
12  
PGA64  
PGA128  
PGA32  
PGA16  
Sinc2 Filter  
Fast Settling Filter  
0
500  
1000  
1500  
fMOD  
2000  
0
500  
1000  
1500  
fMOD  
2000  
Decimation Ratio =  
Decimation Ratio =  
fDATA  
fDATA  
Figure 5.  
Figure 6.  
NOISE vs INPUT SIGNAL  
CMRR vs FREQUENCY  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
130  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
−
−
−
0.5  
2.5  
1.5  
0.5  
1.5  
2.5  
1
10  
100  
1k  
10k  
100k  
VIN (V)  
Frequency of CM Signal (Hz)  
Figure 7.  
PSRR vs FREQUENCY  
Figure 8.  
OFFSET vs TEMPERATURE  
50  
120  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
PGA16  
PGA1  
0
−
50  
PGA64  
−
−
−
100  
150  
200  
PGA128  
−
−
−
10  
50  
30  
10  
30  
50  
70  
90  
1
10  
100  
1k  
10k  
100k  
_
Temperature ( C)  
Frequency of Power Supply (Hz)  
Figure 9.  
Figure 10.  
12  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
TYPICAL CHARACTERISTICS (continued)  
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and  
fDATA = 10Hz, unless otherwise specified.  
GAIN vs TEMPERATURE  
INTEGRAL NONLINEARITY vs INPUT SIGNAL  
1.00010  
1.00006  
1.00002  
0.99998  
0.99994  
0.99990  
0.99986  
10  
8
_
−40 C  
6
4
_
+85  
C
2
0
−
−
−
−
2
4
6
8
_
+25  
C
−
10  
−
−
−
−
−
−
−
−
0.5  
50  
30  
10  
10  
30  
50  
70  
90  
2.5  
2
1.5  
1
0
0.5  
1
1.5  
2
2.5  
_
Temperature ( C)  
VIN (V)  
Figure 11.  
Figure 12.  
ADC CURRENT vs PGA  
CURRENT vs TEMPERATURE  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
250  
200  
150  
100  
50  
AVDD = 5V, Buffer = ON  
Buffer = OFF  
IDIGITAL  
IANALOG  
IANALOG  
AVDD = 3V, Buffer = ON  
Buffer = OFF  
IDIGITAL  
0
−
−
−
10  
50  
30  
10  
30  
50  
70  
90  
0
1
2
4
8
16  
32  
64  
128  
_
Temperature ( C)  
PGA Setting  
Figure 13.  
Figure 14.  
HISTOGRAM OF OUTPUT DATA  
DIGITAL CURRENT  
400  
350  
300  
250  
200  
150  
100  
50  
4500  
4000  
3500  
3000  
2500  
2000  
1500  
1000  
500  
Normal  
fOSC = 4.91MHz  
SPEED = 0  
Normal  
SLEEP  
fOSC = 4.91MHz  
fOSC = 2.45MHz  
Power  
Down  
SLEEP  
fOSC = 2.45MHz  
0
0
−
2
−
−
−
0.5  
1.5  
1
0
0.5  
1
1.5  
2
3.0  
4.0  
5.0  
ppm of FS  
VDD (V)  
Figure 15.  
Figure 16.  
13  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
TYPICAL CHARACTERISTICS (continued)  
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and  
fDATA = 10Hz, unless otherwise specified.  
VREFOUT vs LOAD CURRENT  
OFFSET DAC – OFFSET vs TEMPERATURE  
2.55  
2.50  
2.45  
200  
170  
140  
110  
80  
50  
20  
−
−
−
10  
40  
70  
−
100  
−
−
−
−
10  
0.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
50  
30  
10  
30  
50  
70  
90  
VREFOUT Current Load (mA)  
_
Temperature ( C)  
Figure 17.  
Figure 18.  
OFFSET DAC – GAIN vs TEMPERATURE  
IDAC ROUT vs VOUT  
1.00020  
1.00016  
1.00012  
1.00008  
1.00004  
1.00000  
0.99996  
0.99992  
0.99988  
0.99984  
0.99980  
0.99976  
1.000  
1.000  
0.999  
0.999  
0.998  
_
+85  
C
_
+25  
C
−
_
40  
C
−
−
−
10  
50  
30  
10  
30  
50  
70  
90  
0
1
2
3
4
5
_
Temperature ( C)  
−
VDD VOUT (V)  
Figure 19.  
Figure 20.  
IDAC NORMALIZED vs TEMPERATURE  
IDAC MATCHING vs TEMPERATURE  
3000  
2000  
1000  
0
1.01  
1.005  
1
−
−
−
−
−
−
1000  
2000  
3000  
4000  
5000  
6000  
0.995  
0.99  
0.985  
−
−
−
10  
50  
30  
10  
30  
50  
70  
90  
−
−
−
10  
50  
30  
10  
30  
50  
70  
90  
_
Temperature ( C)  
_
Temperature ( C)  
Figure 21.  
Figure 22.  
14  
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TYPICAL CHARACTERISTICS (continued)  
AVDD = +5V, DVDD = +5V, fOSC = 2.4576MHz, PGA = 1, RDAC = 150kΩ, VREF ≡ (REF IN+) – (REF IN–) = +2.5V, and  
fDATA = 10Hz, unless otherwise specified.  
IDAC DIFFERENTIAL NONLINEARITY  
RANGE = 1, RDAC = 150kΩ, VREF = 2.5V  
IDAC INTEGRAL NONLINEARITY  
RANGE = 1, RDAC = 150kΩ, VREF = 2.5V  
0.5  
0.4  
0.3  
0.2  
0.1  
0
0.5  
0.4  
0.3  
0.2  
0.1  
0
−
−
−
−
−
0.1  
0.2  
0.3  
0.4  
0.5  
−
−
−
−
−
0.1  
0.2  
0.3  
0.4  
0.5  
0
32  
64  
96  
128  
160  
192  
224  
255  
0
32  
64  
96  
128  
160  
192  
224  
255  
IDAC Code  
IDAC Code  
Figure 23.  
Figure 24.  
15  
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OVERVIEW  
open. The anode of the diode is connected to the  
positive input of the A/D converter, and the cathode  
of the diode is connected to negative input of the A/D  
converter. The output of IDAC1 is connected to the  
anode to bias the diode and the cathode of the diode  
is also connected to ground to complete the circuit.  
INPUT MULTIPLEXER  
The input multiplexer provides for any combination of  
differential inputs to be selected on any of the input  
channels, as shown in Figure 25. For example, if  
channel 1 is selected as the positive differential input  
channel, any other channel can be selected as the  
negative differential input channel. With this method,  
it is possible to have up to eight fully differential input  
channels.  
In this mode, the output of IDAC1 is also connected  
to the output pin, so some current may flow into an  
external load from IDAC1, rather than the diode. See  
Application Report Measuring Temperature with the  
ADS1256, ADS1217, or ADS1218 (SBAA073) for  
more information.  
In addition, current sources are supplied that will  
source or sink current to detect open or short circuits  
on the input pins.  
BURNOUT CURRENT SOURCES  
When the Burnout bit is set in the ACR configuration  
register, two current sources are enabled. The current  
source on the positive input channel sources  
approximately 2µA of current. The current source on  
the negative input channel sinks approximately 2µA.  
This allows for the detection of an open circuit  
(full-scale reading) or short circuit (0V differential  
reading) on the selected input differential pair.  
A
IN0  
AIN  
1
AVDD  
Burnout Current Source On  
AIN2  
INPUT BUFFER  
The input impedance of the ADS1218 without the  
buffer is 5MΩ/PGA. With the buffer enabled, the input  
voltage range is reduced and the analog  
power-supply current is higher. The buffer is  
controlled by ANDing the state of the BUFEN pin with  
the state of the BUFFER bit in the ACR register. See  
Application Report Input Currents for High-Resolution  
ADCs (SBAA090) for more information.  
AIN  
3
AIN4  
AIN5  
IDAC1 AND IDAC2  
Burnout Current Source On  
AIN  
6
The ADS1218 has two 8-bit current output DACs that  
can be controlled independently. The output current is  
set with RDAC, the range select bits in the ACR  
register, and the 8-bit digital value in the IDAC  
register.  
AGND  
IDAC1  
AIN7  
The output current = VREF/(8RDAC)(2RANGE–1)(DAC  
CODE). With VREFOUT = 2.5V and RDAC = 150kΩ to  
AGND the full-scale output can be selected to be  
0.5mA, 1mA, or 2mA. The compliance voltage range  
is 0V to within 1V of AVDD. When the internal voltage  
reference of the ADS1218 is used, it is the reference  
for the IDAC. An external reference may be used for  
the IDACs by disabling the internal reference and  
tying the external reference input to the VREFOUT pin.  
AINCOM  
Figure 25. Input Multiplexer Configuration  
TEMPERATURE SENSOR  
An on-chip diode provides temperature sensing  
capability. When the configuration register for the  
input MUX is set to all 1s, the diode is connected to  
the input of the A/D converter. All other channels are  
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PGA  
VRCAP PIN  
The Programmable Gain Amplifier (PGA) can be set  
to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the  
PGA can improve the effective resolution of the A/D  
converter. For instance, with a PGA of 1 on a 5V  
full-scale range, the A/D converter can resolve to  
1µV. With a PGA of 128, on a 40mV full-scale range,  
the A/D converter can resolve to 75nV.  
This pin provides a bypass cap for noise filtering on  
internal VREF circuitry only. As this is a sensitive pin,  
place the capacitor as close as possible and avoid  
any resistive loading. The recommended capacitor is  
a 1000pF ceramic cap. If an external VREF is used,  
this pin can be left unconnected.  
CLOCK GENERATOR  
PGA OFFSET DAC  
The clock source for the ADS1218 can be provided  
from a crystal, oscillator, or external clock. When the  
clock source is a crystal, external capacitors must be  
provided to ensure startup and a stable clock  
frequency; see Figure 26 and Table 1.  
The input to the PGA can be shifted by half the  
full-scale input range of the PGA by using the ODAC  
register. The ODAC (Offset DAC) register is an 8-bit  
value; the MSB is the sign and the seven LSBs  
provide the magnitude of the offset. Using the ODAC  
register does not reduce the performance of the A/D  
converter. See Application Report The Offset DAC  
(SBAA077) for more information.  
XIN  
C1  
Crystal  
XOUT  
MODULATOR  
C2  
The modulator is a single-loop second-order system.  
The modulator runs at a clock speed (fMOD) that is  
derived from the external clock (fOSC). The frequency  
division is determined by the SPEED bit in the  
SETUP register.  
Figure 26. Crystal Connection  
Table 1. Typical Clock Sources  
SPEED BIT  
fMOD  
CLOCK  
SOURCE  
FREQUENCY  
C1  
C2  
PART NUMBER  
0
1
fOSC/128  
fOSC/256  
Crystal  
Crystal  
Crystal  
Crystal  
2.4576  
4.9152  
4.9152  
4.9152  
0-20pF  
0-20pF  
0-20pF  
0-20pF  
0-20pF  
0-20pF  
0-20pF  
ECS, ECSD 2.45 - 32  
ECS, ECSL 4.91  
ECS, ECSD 4.91  
VOLTAGE REFERENCE INPUT  
0-20pF CTS, MP 042 4M9182  
The ADS1218 uses a differential voltage reference  
input. The input signal is measured against the  
differential voltage VREF ≡ (VREF+) – (VREF–). For  
AVDD = 5V, VREF is typically 2.5V. For AVDD = 3V,  
VREF is typically 1.25V. Due to the sampling nature of  
the modulator, the reference input current increases  
with higher modulator clock frequency (fMOD) and  
higher PGA settings.  
CALIBRATION  
The offset and gain errors in the ADS1218, or the  
complete system, can be reduced with calibration.  
Internal calibration of the ADS1218 is called self  
calibration. This is handled with three commands.  
One command does both offset and gain calibration.  
There is also a gain calibration command and an  
offset calibration command. Each calibration process  
takes seven tDATA periods to complete. It takes 14  
tDATA periods to complete both an offset and gain  
calibration. Self-gain calibration is optimized for PGA  
gains less than 8. When using higher gains, system  
gain calibration is recommended.  
ON-CHIP VOLTAGE REFERENCE  
A selectable voltage reference (1.25V or 2.5V) is  
available for supplying the voltage reference input. To  
use, connect VREF– to AGND and VREF+ to VREFOUT  
.
The enabling and voltage selection are controlled  
through bits REF EN and REF HI in the setup  
register. The 2.5V reference requires AVDD = 5V.  
When using the on-chip voltage reference, the  
VREFOUT pin should be bypassed with a 0.1µF  
capacitor to AGND.  
For system calibration, the appropriate signal must be  
applied to the inputs. The system offset command  
requires a zero differential input signal. It then  
computes an offset that will nullify offset in the  
system. The system gain command requires a  
positive full-scale differential input signal. It then  
computes a value to nullify gain errors in the system.  
Each of these calibrations will take seven tDATA  
periods to complete.  
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Calibration must be performed after power on, a  
change in decimation ratio, or a change of the PGA.  
For operation with a reference voltage greater than  
(AVDD– 1.5V), the buffer must also be turned off  
during calibration.  
Adjustable Digital Filter  
Sinc3  
At the completion of calibration, the DRDY signal  
goes low, which indicates the calibration is finished  
and valid data is available. See Application Report  
Calibration Routine and Register Value Generation  
for the ADS121x Series (SBAA099) for more  
information.  
Modulator  
Output  
Sinc2  
Data Out  
Fast Settling  
DIGITAL FILTER  
FILTER SETTLING TIME  
SETTLING TIME  
(Conversion Cycles)  
The Digital Filter can use either the fast settling,  
sinc2, or sinc3 filter, as shown in Figure 27. In  
addition, the Auto mode changes the sinc filter after  
the input channel or PGA is changed. When  
switching to a new channel, it will use the fast settling  
filter for the next two conversions, the first of which  
should be discarded. It will then use the sinc2  
followed by the sinc3 filter. This combines the  
low-noise advantage of the sinc3 filter with the quick  
response of the fast settling time filter. See Figure 28  
for the frequency response of each filter.  
FILTER  
3(1)  
2(1)  
1(1)  
Sinc3  
Sinc2  
Fast  
NOTE: (1) With Synchronized Channel Changes.  
AUTO MODE FILTER SELECTION  
CONVERSION CYCLE  
1
2
3
4
Fast  
Sinc2  
Sinc3  
Discard  
When using the fast setting filter, select a decimation  
value set by the DEC0 and M/DEC1 registers that is  
evenly divisible by four for the best gain accuracy.  
For example, choose 260 rather than 261.  
Figure 27. Filter Step Responses  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
SINC3 FILTER RESPONSE(1)  
SINC2 FILTER RESPONSE(1)  
−
•
( 3dB = 0.262 fDATA = 15.76Hz)  
−
•
( 3dB = 0.318 fDATA = 19.11Hz)  
0
0
20  
40  
60  
80  
−
−
−
−
20  
40  
60  
80  
−
−
−
−
−
−
100  
120  
−
−
100  
120  
0
30  
60  
90 120 150 180 210 240 270 300  
Frequency (Hz)  
0
30  
60  
90 120 150 180 210 240 270 300  
Frequency (Hz)  
FAST SETTLING FILTER RESPONSE(1)  
−
•
( 3dB = 0.469 fDATA = 28.125Hz)  
0
20  
40  
60  
80  
−
−
−
−
−
−
100  
120  
0
30  
60  
90 120 150 180 210 240 270 300  
Frequency (Hz)  
NOTE: (1) fDATA = 60Hz.  
Figure 28. Filter Frequency Responses  
DIGITAL I/O INTERFACE  
SERIAL PERIPHERAL INTERFACE  
The ADS1218 has eight pins dedicated for digital I/O.  
The default power-up condition for the digital I/O pins  
are as inputs. All of the digital I/O pins are individually  
configurable as inputs or outputs. They are  
configured through the DIR control register. The DIR  
register defines whether the pin is an input or output,  
and the DIO register defines the state of the digital  
output. When the digital I/O are configured as inputs,  
DIO is used to read the state of the pin. If the digital  
I/O are not used, either 1) configure as outputs; or 2)  
leave as inputs and tie to ground; this prevents  
excess power dissipation.  
The Serial Peripheral Interface (SPI) allows a  
controller to communicate synchronously with the  
ADS1218. The ADS1218 operates in slave-only  
mode.  
Chip Select (CS)  
The chip select (CS) input of the ADS1218 must be  
externally asserted before a master device can  
exchange data with the ADS1218. CS must be low  
for the duration of the transaction. CS can be tied  
low.  
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SBAS187C–SEPTEMBER 2001–REVISED SEPTEMBER 2005  
Serial Clock (SCLK)  
REGISTER BANK  
SCLK, a Schmitt Trigger input, clocks data transfer  
on the DIN input and DOUT output. When transferring  
data to or from the ADS1218, multiple bits of data  
may be transferred back-to-back with no delay in  
SCLKs or toggling of CS. Make sure to avoid glitches  
on SCLK because they can cause extra shifting of the  
data.  
The operation of the device is set up through  
individual registers. The set of the 16 registers  
required to configure the device is referred to as a  
Register Bank, as shown in Figure 29.  
Configuration  
Register Bank  
16 bytes  
RAM  
128 Bytes  
FLASH  
4k Bytes  
SETUP  
MUX  
ACR  
IDAC1  
IDAC2  
ODAC  
DIO  
Polarity (POL)  
The serial clock polarity is specified by the POL input.  
When SCLK is active high, set POL high. When  
SCLK is active low, set POL low.  
DIR  
Bank 0  
16 bytes  
DEC0  
M/DEC1  
OCR0  
OCR1  
OCR2  
FSR0  
FSR1  
FSR2  
DATA READY  
The DRDY output is used as a status signal to  
indicate when data is ready to be read from the  
ADS1218. DRDY goes low when new data is  
available. It is reset high when a read operation from  
the data register is complete. It also goes high prior  
to the updating of the output register to indicate when  
not to read from the device to ensure that a data read  
is not attempted while the register is being updated.  
Bank 2  
16 bytes  
Page 0  
128 bytes  
Bank 7  
16 bytes  
DSYNC OPERATION  
DSYNC is used to provide for synchronization of the  
A/D  
conversion  
with  
an  
external  
event.  
Synchronization can be achieved either through the  
DSYNC pin or the DSYNC command. When the  
DSYNC pin is used, the filter counter is reset on the  
falling edge of DSYNC. The modulator is held in reset  
until DSYNC is taken high. Synchronization occurs on  
the next rising edge of the system clock after DSYNC  
is taken high.  
Page 31  
128 bytes  
MEMORY  
Figure 29. Memory Organization  
Three types of memory are used on the ADS1218:  
registers, RAM, and Flash. 16 registers directly  
control the various functions (PGA, DAC value,  
Decimation Ratio, etc.) and can be directly read or  
written to. Collectively, the registers contain all the  
information needed to configure the part, such as  
data format, mux settings, calibration settings,  
decimation ratio, etc. Additional registers, such as  
conversion data, are accessed through dedicated  
instructions.  
RAM  
Reads and Writes to Registers and RAM occur on a  
byte basis. However, copies between registers and  
RAM occurs on  
a bank basis. The RAM is  
independent of the Registers; for example, the RAM  
can be used as general-purpose RAM.  
The ADS1218 supports any combination of eight  
analog inputs. With this flexibility, the device could  
easily support eight unique configurations—one per  
input channel. In order to facilitate this type of usage,  
eight separate register banks are available.  
Therefore, each configuration could be written once  
and recalled as needed without having to serially  
retransmit all the configuration data. Checksum  
commands are also included, which can be used to  
verify the integrity of RAM.  
The on-chip Flash can be used to store non-volatile  
data. The Flash data is separate from the  
configuration registers and therefore can be used for  
any purpose, in addition to device configuration. The  
Flash page data is read and written in 128 byte  
blocks through the RAM banks; for example, all RAM  
banks map to a single page of Flash, as shown in  
Figure 29.  
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The RAM provides eight banks, with  
a
bank  
The ADS1218 supports any combination of eight  
analog inputs and the Flash memory supports up to  
32 unique Page configurations. With this flexibility,  
the device could support 32 unique configurations for  
each of the eight analog input channels. For instance,  
the on-chip temperature sensor could be used to  
monitor temperature, then different calibration  
coefficients could be recalled for each of the eight  
analog input channels based on the change in  
temperature. This would enable the user to recall  
calibration coefficients for every 4°C change in  
temperature over the industrial temperature range,  
which could be used to correct for drift errors.  
Checksum commands are also included, which can  
be used to verify the integrity of Flash.  
consisting of 16 bytes. The total size of the RAM is  
128 bytes. Copies between the registers and RAM  
are performed on a bank basis. Also, the RAM can  
be directly read or written through the serial interface  
on power-up. The banks allow separate storage of  
settings for each input.  
The RAM address space is linear; therefore,  
accessing RAM is done using an auto-incrementing  
pointer. Access to RAM in the entire memory map  
can be done consecutively without having to address  
each bank individually. For example, if you were  
currently accessing bank 0 at offset 0xF (the last  
location of bank 0), the next access would be bank 1  
and offset 0x0. Any access after bank 7 and offset  
0xF will wrap around to bank 0 and Offset 0x0.  
The following two commands can be used to  
manipulate the Flash. First, the contents of Flash can  
be written to with the WR2F (write RAM to Flash)  
command. This command first erases the designated  
Flash page and then writes the entire content of RAM  
(all banks) into the designated Flash page. Second,  
the contents of Flash can be read with the RF2R  
(read Flash to RAM) command. This command reads  
the designated Flash page into the entire contents of  
RAM (all banks). In order to ensure maximum  
endurance and data retention, the SPEED bit in the  
SETUP register must be set for the appropriate fOSC  
frequency.  
Although the Register Bank memory is linear, the  
concept of addressing the device can also be thought  
of in terms of bank and offset addressing. Looking at  
linear and bank addressing syntax, we have the  
following comparison: in the linear memory map, the  
address 0x14 is equivalent to bank 1 and offset 0x4.  
Simply stated, the most significant four bits represent  
the bank, and the least significant four bits represent  
the offset. The offset is equivalent to the register  
address for that bank of memory.  
FLASH  
Writing to or erasing Flash can be disabled either  
through the WREN pin or the WREN register bit. If  
the WREN pin is low OR the WREN bit is cleared,  
then the WR2F command has no effect. This protects  
the integrity of the Flash data from being  
inadvertently corrupted.  
Reads and Writes to Flash occur on a Page basis.  
Therefore, the entire contents of RAM is used for  
both Read and Write operations. The Flash is  
independent of the Registers; for example, the Flash  
can be used as general-purpose Flash.  
Upon power-up or reset, the contents of Flash Page 0  
are loaded into RAM. Subsequently, the contents of  
RAM Bank 0 are loaded into the configuration  
register. Therefore, the user can customize the  
power-up configuration for the device. Care should be  
taken to ensure that data for Flash Page 0 is written  
correctly, in order to prevent unexpected operation  
upon power-up.  
Accessing the Flash data either through read, write,  
or erase may affect the accuracy of the conversion  
result. Therefore, the conversion result should be  
discarded when accesses to Flash are done.  
21  
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REGISTER MAP  
Table 2. Registers  
ADDRESS  
00H  
REGISTER  
SETUP  
MUX  
BIT 7  
ID  
BIT 6  
ID  
BIT 5  
ID  
BIT 4  
SPEED  
PSEL0  
BIT 3  
REF EN  
NSEL3  
IDAC1R0  
IDAC1_3  
IDAC2_3  
OSET_3  
DIO_3  
BIT 2  
REF HI  
NSEL2  
PGA2  
BIT 1  
BUF EN  
NSEL1  
PGA1  
BIT 0  
BIT ORDER  
01H  
PSEL3  
BOCS  
IDAC1_7  
IDAC2_7  
SIGN  
PSEL2  
IDAC2R1  
IDAC1_6  
IDAC2_6  
OSET_6  
DIO_6  
DIR_6  
PSEL1  
IDAC2R0  
IDAC1_5  
IDAC2_5  
OSET_5  
DIO_5  
NSEL0  
PGA0  
02H  
ACR  
IDAC1R1  
IDAC1_4  
IDAC2_4  
OSET_4  
DIO_4  
03H  
IDAC1  
IDAC2  
ODAC  
DIO  
IDAC1_2  
IDAC2_2  
OSET_2  
DIO_2  
IDAC1_1  
IDAC2_1  
OSET_1  
DIO_1  
IDAC1_0  
IDAC2_0  
OSET_0  
DIO_0  
04H  
05H  
06H  
DIO_7  
DIR_7  
DEC07  
DRDY  
OCR07  
OCR15  
OCR23  
FSR07  
FSR15  
FSR23  
07H  
DIR  
DIR_5  
DIR_4  
DIR_3  
DIR_2  
DIR_1  
DIR_0  
08H  
DEC0  
M/DEC1  
OCR0  
OCR1  
OCR2  
FSR0  
FSR1  
FSR2  
DEC06  
U/B  
DEC05  
SMODE1  
OCR05  
OCR13  
OCR21  
FSR05  
FSR13  
FSR21  
DEC04  
SMODE0  
OCR04  
OCR12  
OCR20  
FSR04  
DEC03  
WREN  
DEC02  
DEC10  
OCR02  
OCR10  
OCR18  
FSR02  
FSR10  
FSR18  
DEC01  
DEC9  
DEC00  
DEC8  
09H  
0AH  
0BH  
0CH  
0DH  
0EH  
0FH  
OCR06  
OCR14  
OCR22  
FSR06  
FSR14  
FSR22  
OCR03  
OCR11  
OCR19  
FSR03  
FSR11  
FSR19  
OCR01  
OCR09  
OCR17  
FSR01  
FSR09  
FSR17  
OCR00  
OCR08  
OCR16  
FSR00  
FSR08  
FSR16  
FSR12  
FSR20  
DETAILED REGISTER DEFINITIONS  
SETUP (Address 00H) Setup Register  
Reset value is set by Flash memory page 0. Factory programmed to iii01110.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
BUF EN  
bit 0  
ID  
ID  
ID  
SPEED  
REF EN  
REF HI  
BIT ORDER  
bits 7-5 Factory Programmed Bits  
bit 4  
SPEED: Modulator Clock Speed  
0 : fMOD = fOSC/128  
1 : fMOD = fOSC/256  
NOTE: When writing to Flash memory using the WR2F command, SPEED must be set as follows:  
2.30MHz < fOSC < 3.12MHz → SPEED = 0  
3.13MHz < fOSC < 4.12MHz → SPEED = 1  
bit 3  
bit 2  
bit 1  
bit 0  
REF EN: Internal Voltage Reference Enable  
0 = Internal Voltage Reference Disabled  
1 = Internal Voltage Reference Enabled  
REF HI: Internal Reference Voltage Select  
0 = Internal Reference Voltage = 1.25V  
1 = Internal Reference Voltage = 2.5V  
BUF EN: Buffer Enable  
0 = Buffer Disabled  
1 = Buffer Enabled  
BIT ORDER: Set Order Bits are Transmitted  
0 = Most Significant Bit Transmitted First  
1 = Least Significant Bit Transmitted First Data is always shifted into the part most significant bit first.  
Data is always shifted out of the part most significant byte first. This configuration bit only controls the  
bit order within the byte of data that is shifted out.  
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MUX (Address 01H) Multiplexer Control Register  
Reset value is set by Flash memory page 0. Factory programmed to 01H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
PSEL3  
PSEL2  
PSEL1  
PSEL0  
NSEL3  
NSEL2  
NSEL1  
NSEL0  
bits 7-4  
PSEL3: PSEL2: PSEL1: PSEL0: Positive Channel Select  
0000 = AIN  
0001 = AIN  
0010 = AIN  
0011 = AIN  
0
1
2
3
0100 = AIN  
0101 = AIN  
0110 = AIN  
0111 = AIN  
4
5
6
7
1xxx = AINCOM (except when all bits are 1s)  
1111 = Temperature Sensor Diode  
bits 3-0  
NSEL3: NSEL2: NSEL1: NSEL0: Negative Channel Select  
0000 = AIN  
0001 = AIN  
0010 = AIN  
0011 = AIN  
0
1
2
3
0100 = AIN  
0101 = AIN  
0110 = AIN  
0111 = AIN  
4
5
6
7
1xxx = AINCOM (except when all bits are 1s)  
1111 = Temperature Sensor Diode  
ACR (Address 02H) Analog Control Register  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
BOCS  
IDAC2R1  
IDAC2R0  
IDAC1R1  
IDAC1R0  
PGA2  
PGA1  
PGA0  
bit 7  
BOCS: Burnout Current Source  
0 = Disabled  
1 = Enabled  
VREF  
8RDAC  
RANGE*1  
ǒ
Ǔ
(
DAC Code  
IDAC Current + ǒ Ǔ2  
)
bits 6-5 IDAC2R1: IDAC2R0: Full-Scale Range Select for IDAC2  
00 = Off  
01 = Range 1  
10 = Range 2  
11 = Range 3  
bits 4-3 IDAC1R1: IDAC1R0: Full-Scale Range Select for IDAC1  
00 = Off  
01 = Range 1  
10 = Range 2  
11 = Range 3  
bits 2-0 PGA2: PGA1: PGA0: Programmable Gain Amplifier Gain Selection  
000 = 1  
001 = 2  
010 = 4  
011 = 8  
100 = 16  
101 = 32  
110 = 64  
111 = 128  
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IDAC1 (Address 03H) Current DAC 1  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
IDAC1_7  
IDAC1_6  
IDAC1_5  
IDAC1_4  
IDAC1_3  
IDAC1_2  
IDAC1_1  
IDAC1_0  
The DAC code bits set the output of DAC1 from 0 to full-scale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the  
DAC1 range bits in the ACR register.  
IDAC2 (Address 04H) Current DAC 2  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
IDAC2_7  
IDAC2_6  
IDAC2_5  
IDAC2_4  
IDAC2_3  
IDAC2_2  
IDAC2_1  
IDAC2_0  
The DAC code bits set the output of DAC2 from 0 to full-scale. The value of the full-scale current is set by this Byte, VREF, RDAC, and the  
DAC2 range bits in the ACR register.  
ODAC (Address 05H) Offset DAC Setting  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
SIGN  
OSET6  
OSET5  
OSET4  
OSET3  
OSET2  
OSET1  
OSET0  
bit 7  
Offset Sign  
0 = Positive  
1 = Negative  
bits 6-0  
NOTE:  
VREF  
2PGA  
Code  
127  
ǒ Ǔ  
Offset +  
 
The offset must be used after calibration or the calibration will notify the effects.  
DIO (Address 06H) Digital I/O  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
DIO7  
DIO6  
DIO5  
DIO4  
DIO3  
DIO2  
DIO1  
DIO0  
A value written to this register will appear on the digital I/O pins if the pin is configured as an output in the DIR register. Reading this  
register will return the value of the digital I/O pins.  
DIR (Address 07H) Direction control for digital I/O  
Reset value is set by Flash memory page 0. Factory programmed to FFH.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
DIR7  
DIR6  
DIR5  
DIR4  
DIR3  
DIR2  
DIR1  
DIR0  
Each bit controls whether the Digital I/O pin is an output (= 0) or input (= 1). The default power-up state is as  
inputs.  
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DEC0 (Address 08H) Decimation Register (least significant 8 bits)  
Reset value is set by Flash memory page 0. Factory programmed to 80H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
DEC07  
DEC06  
DEC05  
DEC04  
DEC03  
DEC02  
DEC01  
DEC00  
The decimation value is defined with 11 bits for a range of 20 to 2047. This register is the least significant 8 bits. The 3 most significant bits  
are contained in the M/DEC1 register.  
M/DEC1 (Address 09H) Mode and Decimation Register  
Reset value is set by Flash memory page 0. Factory programmed to 07H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
DRDY  
U/B  
SMODE1  
SMODE0  
WREN  
DEC10  
DEC09  
DEC08  
bit 7  
DRDY: Data Ready (Read Only)  
This bit duplicates the state of the DRDY pin.  
bit 6  
U/B: Data Format  
0 = Bipolar  
1 = Unipolar  
U/B  
ANALOG INPUT  
DIGITAL OUTPUT  
0
+FS  
Zero  
–FS  
0x7FFFFF  
0x000000  
0x800000  
1
+FS  
Zero  
–FS  
0xFFFFFF  
0x000000  
0x000000  
bits 5-4  
SMODE1: SMODE0: Settling Mode  
00 = Auto  
01 = Fast Settling filter  
10 = Sinc2 filter  
11 = Sinc3 filter  
bit 3  
WREN: Flash Write Enable  
0 = Flash Writing Disabled  
1 = Flash Writing Enabled  
This bit and the WREN pin must both be enabled in order to write to the Flash memory.  
DEC10: DEC09: DEC08: Most Significant Bits of the Decimation Value  
bits 2-0  
OCR0 (Address 0AH) Offset Calibration Coefficient (least significant byte)  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
OCR07  
OCR06  
OCR05  
OCR04  
OCR03  
OCR02  
OCR01  
OCR00  
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OCR1 (Address 0BH) Offset Calibration Coefficient (middle byte)  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
OCR15  
OCR14  
OCR13  
OCR12  
OCR11  
OCR10  
OCR09  
OCR08  
OCR2 (Address 0CH) Offset Calibration Coefficient (most significant byte)  
Reset value is set by Flash memory page 0. Factory programmed to 00H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
OCR23  
OCR22  
OCR21  
OCR20  
OCR19  
OCR18  
OCR17  
OCR16  
FSR0 (Address 0DH) Full-Scale Register (least significant byte)  
Reset value is set by Flash memory page 0. Factory programmed to 24H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
FSR07  
FSR06  
FSR05  
FSR04  
FSR03  
FSR02  
FSR01  
FSR00  
FSR1 (Address 0EH) Full-Scale Register (middle byte)  
Reset value is set by Flash memory page 0. Factory programmed to 90H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
FSR15  
FSR14  
FSR13  
FSR12  
FSR11  
FSR10  
FSR09  
FSR08  
FSR2 (Address 0FH) Full-Scale Register (most significant byte)  
Reset value is set by Flash memory page 0. Factory programmed to 67H.  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
FSR23  
FSR22  
FSR21  
FSR20  
FSR19  
FSR18  
FSR17  
FSR16  
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COMMAND DEFINITIONS  
The commands listed below control the operation of  
the ADS1218. Some of the commands are  
stand-alone commands (e.g., RESET) while others  
require additional bytes (e.g., WREG requires  
command, count, and the data bytes). Commands  
that output data require a minimum of four fOSC cycles  
before the data is ready (e.g., RDATA).  
Operands: n = count (0 to 127)  
r = register (0 to 15)  
x = don’t care  
a = RAM bank address (0 to 7)  
f = Flash memory page address (0 to 31)  
Table 3. Command Summary  
COMMANDS  
RDATA  
DESCRIPTION  
Read Data  
COMMAND BYTE(1)  
0000 0001 (01H)  
0000 0011 (03H)  
0000 1111 (0FH)  
0001 r r r r (1xH)  
0010 0aaa (2xH)  
0100 0aaa (4xH)  
0100 1000 (48H)  
0101 r r r r (5xH)  
0110 0aaa (6xH)  
100f f f f f (8, 9xH)  
101f f f f f (A, BxH)  
1100 0aaa (CxH)  
1101 0aaa (DxH)  
1101 1000 (D8H)  
1101 1111 (DFH)  
1110 0aaa (ExH)  
1110 1000 (E8H)  
1110 1100 (ECH)  
1111 0000 (F0H)  
1111 0001 (F1H)  
1111 0010 (F2H)  
1111 0011 (F3H)  
1111 0100 (F4H)  
1111 1100 (FCH)  
1111 1101 (FDH)  
1111 1110 (FEH)  
2ND COMMAND BYTE  
—
RDATAC  
STOPC  
RREG  
Read Data Continuously  
Stop Read Data Continuously  
Read from REG Bank rrrr  
Read from RAM Bank aaa  
Copy REGs to RAM Bank aaa  
Copy REGS to all RAM Banks  
Write to REG rrrr  
—
—
xxxx_nnnn (# of reg–1)  
RRAM  
xnnn_nnnn (# of bytes–1)  
CREG  
—
CREGA  
WREG  
—
xxxx_nnnn (# of reg–1)  
WRAM  
Write to RAM Bank aaa  
Read Flash page to RAM  
Write RAM to Flash page  
Copy RAM Bank aaa to REG  
Calc RAM Bank aaa Checksum  
Calc all RAM Bank Checksum  
Calc REG Checksum  
Calc RAM Bank aaa Checksum  
Calc all RAM Banks Checksum  
Calc Flash Checksum  
Self Cal Offset and Gain  
Self Cal Offset  
xnnn_nnnn (# of bytes–1)  
RF2R  
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WR2F  
CRAM  
CSRAMX  
CSARAMX  
CSREG  
CSRAM  
CSARAM  
CSFL  
SELFCAL  
SELFOCAL  
SELFGCAL  
SYSOCAL  
SYSGCAL  
DSYNC  
SLEEP  
Self Cal Gain  
Sys Cal Offset  
Sys Cal Gain  
Sync DRDY  
Put in SLEEP Mode  
RESET  
Reset to Power-Up Values  
(1) The data input received by the ADS1218 is always MSB first. The data out format is set by the BIT ORDER bit in ACR reg.  
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RDATA  
Read Data  
Description: Read a single 24-bit ADC conversion result. On completion of read back, DRDY goes high.  
Operands: None  
Bytes: 1  
Encoding: 0000 0001  
Data Transfer Sequence:  
DRDY  
• • • (1)  
0000 0001  
xxxx xxxx  
MSB  
xxxx xxxx  
Mid−Byte  
xxxx xxxx  
LSB  
DIN  
DOUT  
RDATAC  
Read Data Continuous  
Description: Read Data Continuous mode enables the continuous output of new data on each DRDY. This  
command eliminates the need to send the Read Data Command on each DRDY. This mode may be terminated  
by either the STOP Read Continuous command or the RESET command.  
Operands: None  
Bytes: 1  
Encoding: 0000 0011  
Data Transfer Sequence:  
Command terminated when uuuu uuuu equals STOPC or RESET.  
• • • (1)  
0000 0011  
uuuu uuuu  
uu uu uuu u  
u uuu uuuu  
DIN  
• • •  
MSB  
Mid−Byte  
LSB  
DOUT  
DRDY  
DIN  
• • •  
uuuu uuuu  
uuuu uu uu  
uuuu uuuu  
• • •  
MSB  
Mid−Byte  
LSB  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
28  
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STOPC  
Stop Continuous  
Description: Ends the continuous data output mode.  
Operands: None  
Bytes: 1  
Encoding: 0000 1111  
Data Transfer Sequence:  
0000 1111  
DIN  
RREG  
Read from Registers  
Description: Output the data from up to 16 registers starting with the register address specified as part of the  
instruction. The number of registers read will be one plus the second byte. If the count exceeds the remaining  
registers, the addresses will wrap back to the beginning.  
Operands: r, n  
Bytes: 2  
Encoding: 0001 rrrr xxxx nnnn  
Data Transfer Sequence:  
Read Two Registers Starting from Register 01H (MUX)  
• • • (1)  
DIN  
0001 0001  
0000 0001  
xxxx xxxx  
MUX  
xxxx xxxx  
ACR  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
RRAM  
Read from RAM  
Description: Up to 128 bytes can be read from RAM starting at the bank specified in the op code. All reads start  
at the address for the beginning of the RAM bank. The number of bytes to read will be one plus the value of the  
second byte.  
Operands: a, n  
Bytes: 2  
Encoding: 0010 0aaa xnnn nnnn  
Data Transfer Sequence:  
Read Two RAM Locations Starting from 20H  
• • • (1)  
DIN  
0010 0010  
x000 0001  
xxxx xxxx  
xxxx xxxx  
RAM Data  
20H  
RAM Data  
21H  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
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CREG  
Copy Registers to RAM Bank  
Description: Copy the 16 control registers to the RAM bank specified in the op code. Refer to timing  
specifications for command execution time.  
Operands: a  
Bytes: 1  
Encoding: 0100 0aaa  
Data Transfer Sequence:  
Copy Register Values to RAM Bank 3  
• • • (1)  
1101 1111  
xxxx xxxx  
DIN  
Checksum  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
CREGA  
Copy Registers to All RAM Banks  
Description: Duplicate the 16 control registers to all the RAM banks. Refer to timing specifications for command  
execution time.  
Operands: None  
Bytes: 1  
Encoding: 0100 1000  
Data Transfer Sequence:  
0100 1000  
DIN  
WREG  
Write to Register  
Description: Write to the registers starting with the register specified as part of the instruction. The number of  
registers that will be written is one plus the value of the second byte.  
Operands: r, n  
Bytes: 2  
Encoding: 0101 rrrr xxxx nnnn  
Data Transfer Sequence:  
Write Two Registers Starting from 06H (DIO)  
DIN  
0101 0110  
xxxx 0001 Data for DIO Data for DIR  
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WRAM  
Write to RAM  
Description: Write up to 128 RAM locations starting at the beginning of the RAM bank specified as part of the  
instruction. The number of bytes written is RAM is one plus the value of the second byte.  
Operands: a, n  
Bytes: 2  
Encoding: 0110 0aaa xnnn nnnn  
Data Transfer Sequence:  
Write to Two RAM Locations starting from 10H  
Data for  
10H  
Data for  
11H  
DIN  
0110 0001  
x000 0001  
RF2R  
Read Flash Memory Page to RAM  
Description: Read the selected Flash memory page to the RAM.  
Operands: f  
Bytes: 1  
Encoding: 100f ffff  
Data Transfer Sequence:  
Read Flash Page 2 to RAM  
1000 0010  
DIN  
WR2F  
Write RAM to Flash Memory  
Description: Write the contents of RAM to the selected Flash memory page.  
Operands: f  
Bytes: 1  
Encoding: 101f ffff  
Data Transfer Sequence:  
Write RAM to Flash Memory Page 31  
1011 1111  
DIN  
31  
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CRAM  
Copy RAM Bank to Registers  
Description: Copy the selected RAM Bank to the Configuration Registers. This will overwrite all of the registers  
with the data from the RAM bank.  
Operands: a  
Bytes: 1  
Encoding: 1100 0aaa  
Data Transfer Sequence:  
Copy RAM Bank 0 to the Registers  
1100 0000  
DIN  
CSRAMX  
Calculate RAM Bank Checksum  
Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the  
bytes with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum.  
Operands: a  
Bytes: 1  
Encoding: 1101 0aaa  
Data Transfer Sequence:  
Calculate Checksum for RAM Bank 3  
• • • (1)  
1101 0011  
xxxx xxxx  
DIN  
Checksum  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
CSARAMX  
Calculate the Checksum for all RAM Banks  
Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes  
with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum.  
Operands: None  
Bytes: 1  
Encoding: 1101 1000  
Data Transfer Sequence:  
• • • (1)  
1101 1000  
xxxx xxxx  
Checksum  
DIN  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
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CSREG  
Calculate the Checksum of Registers  
Description: Calculate the checksum of all the registers. The checksum is calculated as a sum of all the bytes  
with the carry ignored. The ID, DRDY, and DIO bits are masked so they are not included in the checksum.  
Operands: None  
Bytes: 1  
Encoding: 1101 1111  
Data Transfer Sequence:  
• • • (1)  
1101 1111  
xxxx xxxx  
DIN  
Checksum  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
CSRAM  
Calculate RAM Bank Checksum  
Description: Calculate the checksum of the selected RAM Bank. The checksum is calculated as a sum of all the  
bytes with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits.  
Operands: a  
Bytes: 1  
Encoding: 1110 0aaa  
Data Transfer Sequence:  
Calculate Checksum for RAM Bank 2  
• • • (1)  
1110 0010  
xxxx xxxx  
DIN  
DOUT  
Checksum  
NOTE: (1) For wait time, refer to timing specification.  
CSARAM  
Calculate Checksum for all RAM Banks  
Description: Calculate the checksum of all RAM Banks. The checksum is calculated as a sum of all the bytes  
with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits.  
Operands: None  
Bytes: 1  
Encoding: 1110 1000  
Data Transfer Sequence:  
• • • (1)  
DIN  
1110 1000  
xxxx xxxx  
Checksum  
DOUT  
NOTE: (1) For wait time, refer to timing specification.  
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CSFL  
Calculate Checksum for all Flash Memory Pages  
Description: Calculate the checksum for all Flash memory pages. The checksum is calculated as a sum of all  
the bytes with the carry ignored. All bits are included in the checksum calculation; there is no masking of bits.  
Operands: None  
Bytes: 1  
Encoding: 1110 1100  
Data Transfer Sequence:  
1110 1100  
DIN  
SELFCAL  
Offset and Gain Self Calibration  
Description: Starts the process of self calibration. The Offset Control Register (OCR) and the Full-Scale  
Register (FSR) are updated with new values after this operation.  
Operands: None  
Bytes: 1  
Encoding: 1111 0000  
Data Transfer Sequence:  
1111 0000  
DIN  
SELFOCAL  
Offset Self Calibration  
Description: Starts the process of self-calibration for offset. The Offset Control Register (OCR) is updated after  
this operation.  
Operands: None  
Bytes: 1  
Encoding: 1111 0001  
Data Transfer Sequence:  
1111 0001  
DIN  
SELFGCAL  
Gain Self Calibration  
Description: Starts the process of self-calibration for gain. The Full-Scale Register (FSR) is updated with new  
values after this operation.  
Operands: None  
Bytes: 1  
Encoding: 1111 0010  
Data Transfer Sequence:  
1111 0010  
DIN  
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SYSOCAL  
System Offset Calibration  
Description: Starts the system offset calibration process. For a system offset calibration, the input should be set  
to 0V differential, and the ADS1218 computes the OCR register value that will compensate for offset errors. The  
Offset Control Register (OCR) is updated after this operation.  
Operands: None  
Bytes: 1  
Encoding: 1111 0011  
Data Transfer Sequence:  
1111 0011  
DIN  
SYSGCAL  
System Gain Calibration  
Description: Starts the system gain calibration process. For a system gain calibration, the differential input  
should be set to the reference voltage and the ADS1218 computes the FSR register value that will compensate  
for gain errors. The FSR is updated after this operation.  
Operands: None  
Bytes: 1  
Encoding: 1111 0100  
Data Transfer Sequence:  
1111 0100  
DIN  
DSYNC  
Sync DRDY  
Description: Synchronizes the ADS1218 to the serial clock edge.  
Operands: None  
Bytes: 1  
Encoding: 1111 1100  
Data Transfer Sequence:  
1111 1100  
DIN  
SLEEP  
Sleep Mode  
Description: Puts the ADS1218 into a low-power sleep mode. SCLK must be inactive while in sleep mode. To  
exit this mode, issue the WAKEUP command.  
Operands: None  
Bytes: 1  
Encoding: 1111 1101  
Data Transfer Sequence:  
1111 1101  
DIN  
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WAKEUP  
Wakeup From Sleep Mode  
Description: Use this command to wake up from sleep mode.  
Operands: None  
Bytes: 1  
Encoding: 1111 1011  
Data Transfer Sequence:  
1111 1011  
DIN  
RESET  
Reset Registers  
Description: Copy the contents of Flash memory page 0 to the registers. This command will also stop the Read  
Continuous mode.  
Operands: None  
Bytes: 1  
Encoding: 1111 1110  
Data Transfer Sequence:  
1111 1110  
DIN  
Table 4. ADS1218 Command Map  
LSB  
MSB  
0000  
0001  
0010  
0011  
0100  
0101  
0000  
x(1)  
0001  
rdata  
rreg 1  
0010  
x
0011  
rdatac  
rreg 3  
0100  
x
0101  
x
0110  
x
0111  
x
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
x
rreg 8  
x
x
x
x
x
x
x
stopc  
rreg 0  
rreg 2  
rreg 4  
rreg 5  
rreg 6  
rreg 7  
rreg 9  
rreg A rreg B rreg C rreg D rreg E  
rreg F  
rram 0 rram 1 rram 2 rram 3 rram 4 rram 5 rram 6 rram 7  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
creg 0 creg 1 creg 2 creg 3 creg 4 creg 5 creg 6 creg 7  
crega  
wreg 0 wreg 1 wreg 2 wreg 3 wreg 4 wreg 5 wreg 6 wreg 7 wreg 8 wreg 9 wreg A wreg B wreg C wreg D wreg E wreg F  
0110 wram 0 wram 1 wram 2 wram 3 wram 4 wram 5 wram 6 wram 7  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0111  
1000  
1001  
1010  
x
x
x
x
x
x
x
x
rf2r 0  
rf2r 1  
rf2r 2  
rf2r 3  
rf2r 4  
rf2r 5  
rf2r 6  
rf2r 7  
rf2r 8  
rf2r 9  
rf2r A  
rf2r B  
rf2r C  
rf2r D  
rf2r E  
rf2r F  
rf2r 10 rf2r 11 rf2r 12 rf2r 13 rf2r 14 rf2r 15 rf2r 16 rf2r 17 rf2r 18 rf2r 19 rf2r 1A rf2r 1B rf2r 1C rf2r 1D rf2r 1E rf2r 1F  
wr2f 0 wr2f 1 wr2f 2 wr2f 3 wr2f 4 wr2f 5 wr2f 6 wr2f 7 wr2f 8 wr2f 9 wr2f A wr2f B wr2f C wr2f D wr2f E wr2f F  
1011 wr2f 10 wr2f 11 wr2f 12 wr2f 13 wr2f 14 wr2f 15 wr2f 16 wr2f 17 wr2f 18 wr2f 19  
wr2f  
1A  
wr2f  
1B  
wr2f  
1C  
wr2f  
1D  
wr2f  
1E  
wr2f 1F  
1100  
1101  
cram 0 cram 1 cram 2 cram 3 cram 4 cram 5 cram 6 cram 7  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
csramx csramx csramx csramx csramx csramx csramx csramx csramx  
csreg  
0
1
2
3
4
5
6
7
1110  
1111  
csram  
0
csram csram2 csram  
csram  
4
csram  
5
csram  
6
csram csramx  
7
x
x
x
x
x
x
csfl  
x
x
x
x
1
3
self cal  
self  
self  
sys  
sys  
x
x
x
x
dsync  
sleep  
reset  
ocal  
gcal  
ocal  
gcal  
(1) x = Reserved  
36  
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The data from the A/D converter is output as codes,  
which then can be easily converted to other units,  
such as ppm or volts. The equations and table below  
show the relationship between bits or codes, ppm,  
and volts.  
DEFINITION OF RULES  
Analog Input Voltage—the voltage at any one  
analog input relative to AGND.  
Analog Input Differential Voltage—given by the  
following equation: (AIN+) – (AIN–). Thus, a positive  
digital output is produced whenever the analog input  
differential voltage is positive, while a negative digital  
output is produced whenever the differential is  
negative.  
(
)
−20 log ppm  
ENOB +  
6.02  
BITS rms  
BIPOLAR Vrms  
UNIPOLAR Vrms  
2 V  
V
REF  
REF  
ǒ
Ǔ
ǒ Ǔ  
PGA  
PGA  
6.02 ER  
6.02 ER  
ǒ
Ǔ
ǒ
Ǔ
For example, when the converter is configured with a  
2.5V reference and placed in a gain setting of 1, the  
positive full-scale output is produced when the analog  
input differential is 2.5V. The negative full-scale  
output is produced when the differential is –2.5V. In  
each case, the actual input voltages must remain  
within the AGND to AVDD range.  
20  
20  
10  
10  
24  
22  
20  
18  
16  
14  
12  
298nV  
1.19µV  
4.77µV  
19.1µV  
76.4µV  
505µV  
1.22mV  
149nV  
597nV  
2.39µV  
9.55µV  
38.2µV  
152.7µV  
610µV  
Conversion Cycle—the term conversion cycle  
usually refers to a discrete A/D conversion operation,  
such as that performed by  
a
successive  
approximation converter. As used here, a conversion  
cycle refers to the tDATA time period. However, each  
digital output is actually based on the modulator  
results from several tDATA time periods.  
fDATA—the frequency of the digital output data  
produced by the ADS1218. fDATA is also referred to as  
the Data Rate.  
fMOD  
fOSC  
+ ǒ  
Ǔ+ ǒ  
Ǔ
fDATA  
FILTER SETTING  
Fast Settling  
Sinc2  
MODULATOR RESULTS  
1 tDATA Time Period  
2 tDATA Time Period  
3 tDATA Time Period  
Decimation Ratio  
mfactor   Decimation Ratio  
fMOD—the frequency or speed at which the modulator  
of the ADS1218 is running. This depends on the  
SPEED bit as shown below:  
Sinc3  
Data Rate—the rate at which conversions are  
completed. See definition for fDATA  
SPEED BIT  
fMOD  
.
0
1
fOSC/128  
fOSC/256  
Decimation Ratio—defines the ratio between the  
output of the modulator and the output Data Rate.  
Valid values for the Decimation Ratio are from 20 to  
2047. Larger Decimation Ratios will have lower noise.  
fOSC—the frequency of the crystal input signal at the  
XIN input of the ADS1218.  
Effective Resolution—the effective resolution of the  
fSAMP—the frequency, or switching speed, of the input  
sampling capacitor. The value is given by one of the  
following equations:  
ADS1218 in  
a particular configuration can be  
expressed in two different units: bits rms (referenced  
to output) and Vrms (referenced to input). Computed  
directly from the converter’s output data, each is a  
statistical calculation. The conversion from one to the  
other is shown below.  
PGA SETTING  
SAMPLING FREQUENCY  
fOSC  
mfactor  
1, 2, 4, 8  
fSAMP  
fSAMP  
fSAMP  
fSAMP  
fSAMP  
+
+
+
+
+
Effective number of bits (ENOB) or effective  
resolution is commonly used to define the usable  
resolution of the A/D converter. It is calculated from  
empirical data taken directly from the device. It is  
typically determined by applying a fixed known signal  
source to the analog input and computing the  
standard deviation of the data sample set. The rms  
noise defines the ±σ interval about the sample mean.  
2fOSC  
mfactor  
8
16  
8fOSC  
mfactor  
16fOSC  
mfactor  
32  
16fOSC  
mfactor  
64, 128  
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Filter Selection—the ADS1218 uses a (sinx/x) filter  
or sinc filter. There are three different sinc filters that  
can be selected. A fast settling filter will settle in one  
tDATA cycle. The sinc2 filter will settle in two cycles  
and have lower noise. The sinc3 will achieve lowest  
noise and higher number of effective bits, but  
requires three cycles to settle. The ADS1218 will  
operate with any one of these filters, or it can operate  
in an auto mode, where it will first select the fast  
settling filter after a new channel is selected for two  
readings and will then switch to sinc2 for one reading,  
followed by sinc3 from then on.  
For example, when the converter is configured with a  
2.5V reference and is placed in a gain setting of 2,  
the full-scale range is: [1.25V (positive full-scale) –  
(–1.25V (negative full-scale))] = 2.5V.  
Least Significant Bit (LSB) Weight—this is the  
theoretical amount of voltage that the differential  
voltage at the analog input would have to change in  
order to observe a change in the output data of one  
least significant bit. It is computed as follows:  
Full−Scale Range  
LSB Weight +  
2N  
where N is the number of bits in the digital output.  
Full-Scale Range (FSR)—as with most A/D  
converters, the full-scale range of the ADS1218 is  
defined as the input, which produces the positive  
full-scale digital output minus the input, which  
produces the negative full-scale digital output. The  
full-scale range changes with gain setting; see  
Table 5.  
tDATA—the inverse of fDATA, or the period between  
each data output.  
Table 5. Full-Scale Range versus PGA Setting  
5V SUPPLY ANALOG INPUT(1)  
GENERAL EQUATIONS  
GAIN  
SETTING  
FULL-SCALE  
DIFFERENTIAL  
INPUT  
PGA OFFSET  
FULL-SCALE  
RANGE  
DIFFERENTIAL  
INPUT  
PGA SHIFT  
RANGE  
RANGE  
RANGE  
VOLTAGES(2)  
VOLTAGES(2)  
1
2
5V  
±2.5V  
±1.25V  
±1.25V  
±0.625V  
2.5V  
4
1.25V  
±0.625V  
±312.5mV  
±156.25mV  
±312.5mV  
±156.25mV  
±78.125mV  
8
0.625V  
312.5mV  
2VREF  
PGA  
" VREF  
PGA  
" VREF  
2PGA  
16  
34  
64  
156.25mV  
78.125mV  
39.0625mV  
±78.125mV  
±39.0625mV  
±19.531mV  
±39.0625mV  
±19.531mV  
±9.766mV  
128  
(1) With a 2.5V reference.  
(2) The ADS1218 allows common-mode voltage as long as the absolute input voltage on AIN+ or AIN– does not go below AGND or above  
AVDD  
.
38  
 
PACKAGE OPTION ADDENDUM  
www.ti.com  
21-May-2010  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
ADS1218Y/250  
ACTIVE  
ACTIVE  
TQFP  
TQFP  
PFB  
PFB  
48  
48  
250  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
ADS1218Y/250G4  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Dec-2011  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
ADS1218Y/250  
TQFP  
PFB  
48  
250  
177.8  
16.4  
9.6  
9.6  
1.5  
12.0  
16.0  
Q2  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
12-Dec-2011  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
TQFP PFB 48  
SPQ  
Length (mm) Width (mm) Height (mm)  
210.0 185.0 35.0  
ADS1218Y/250  
250  
Pack Materials-Page 2  
MECHANICAL DATA  
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998  
PFB (S-PQFP-G48)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
M
0,08  
36  
25  
37  
24  
48  
13  
0,13 NOM  
1
12  
5,50 TYP  
7,20  
SQ  
Gage Plane  
6,80  
9,20  
SQ  
8,80  
0,25  
0,05 MIN  
0°–7°  
1,05  
0,95  
0,75  
0,45  
Seating Plane  
0,08  
1,20 MAX  
4073176/B 10/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,  
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