ADS1254E/2K5 [BB]

24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER; 24位20kHz ,低功耗模拟数字转换器
ADS1254E/2K5
型号: ADS1254E/2K5
厂家: BURR-BROWN CORPORATION    BURR-BROWN CORPORATION
描述:

24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER
24位20kHz ,低功耗模拟数字转换器

转换器 光电二极管
文件: 总17页 (文件大小:281K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ADS1254  
ADS1254  
SBAS213 – JUNE 2001  
24-Bit, 20kHz, Low Power  
ANALOG-TO-DIGITAL CONVERTER  
DESCRIPTION  
FEATURES  
The ADS1254 is a precision, wide dynamic range, delta-  
sigma, Analog-to-Digital (A/D) converter with 24-bit reso-  
lution. The delta-sigma architecture is used for wide dy-  
namic range and to ensure 24 bits of no missing codes  
performance. An effective resolution of 19 bits (1.8ppm of  
rms noise) is achieved for conversion rates up to 20kHz.  
24 BITS—NO MISSING CODES  
19 BITS EFFECTIVE RESOLUTION UP TO  
20kHz DATA RATE  
LOW NOISE: 1.8ppm  
FOUR DIFFERENTIAL INPUTS  
INL: 15ppm (max)  
The ADS1254 is designed for high-resolution measurement  
applications in cardiac diagnostics, smart transmitters, in-  
dustrial process control, weight scales, chromatography, and  
portable instrumentation. The converter includes a flexible,  
two-wire synchronous serial interface for low-cost isolation.  
EXTERNAL REFERENCE (0.5V to 5V)  
POWER-DOWN MODE  
SYNC MODE  
LOW POWER: 4mW at 20kHz  
The ADS1254 is a multi-channel converter and is offered in  
an SSOP-20 package.  
SEPARATE DIGITAL INTERFACE SUPPLY 1.8V  
to 3.6V  
APPLICATIONS  
CARDIAC DIAGNOSTICS  
DIRECT THERMOCOUPLE INTERFACES  
BLOOD ANALYSIS  
INFRARED PYROMETERS  
LIQUID/GAS CHROMATOGRAPHY  
PRECISION PROCESS CONTROL  
ADS1254  
VREF  
CLK  
CH1+  
CH1–  
CH2+  
4th-Order  
∆Σ  
Modulator  
CH2–  
SCLK  
Digital  
Filter  
Serial  
Interface  
Mux  
DOUT/DRDY  
CH3+  
CH3–  
CH4+  
CH4–  
AVDD  
AGND  
DVDD  
Control  
DGND  
CHSEL0 CHSEL1  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
www.ti.com  
ABSOLUTE MAXIMUM RATINGS  
ELECTROSTATIC  
DISCHARGE SENSITIVITY  
Analog Input: Current (Momentary).............................................. ±100mA  
(Continuous) ............................................... ±10mA  
Voltage ................................... GND 0.3V to VDD + 0.3V  
This integrated circuit can be damaged by ESD. Texas Instru-  
ments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling  
and installation procedures can cause damage.  
AVDD to AGND ....................................................................... 0.3V to 6V  
DVDD to AVDD .......................................................................... 6V to +6V  
DVDD to DGND ....................................................................... 0.3V to 6V  
VREF Voltage to AGND ............................................. 0.3V to VDD + 0.3V  
Digital Input Voltage to DGND ................................. 0.3V to VDD + 0.3V  
Digital Output Voltage to DGND .............................. 0.3V to VDD + 0.3V  
Lead Temperature (soldering, 10s) .............................................. +300°C  
Power Dissipation (any package) ................................................. 500mW  
ESD damage can range from subtle performance degradation  
to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric  
changes could cause the device not to meet its published  
specifications.  
PACKAGE/ORDERING INFORMATION  
PACKAGE  
DRAWING  
NUMBER  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE  
MARKING  
ORDERING  
NUMBER(1)  
TRANSPORT  
MEDIA  
PRODUCT  
PACKAGE  
ADS1254E  
SSOP-20  
349  
40°C to +85°C  
ADS1254E  
ADS1254E  
Rails  
"
"
"
"
"
ADS1254E/2K5  
Tape and Reel  
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces  
of ADS1254E/2K5will get a single 2500-piece Tape and Reel.  
ELECTRICAL CHARACTERISTICS  
All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +1.8V. CLK = 8MHz, and VREF = 4.096, unless otherwise specified.  
ADS1254E  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
ANALOG INPUT  
Input Voltage Range  
Input Impedance  
AGND  
±VREF  
V
CLK = 3,840Hz  
CLK = 1MHz  
CLK = 8MHz  
260  
1
MΩ  
MΩ  
kΩ  
pF  
125  
6
Input Capacitance  
Input Leakage  
At +25°C  
5
50  
1
pA  
nA  
At TMIN to TMAX  
DYNAMIC CHARACTERISTICS  
Data Rate  
20.8  
kHz  
kHz  
Bandwidth  
3dB  
4.24  
Serial Clock (SCLK)  
System Clock Input (CLK)  
8
8
MHz  
MHz  
ACCURACY  
Integral Non-Linearity(1)  
±0.0002  
105  
1.8  
±0.0015  
% of FSR  
THD  
Noise  
1kHz Input; 0.1dB below FS  
60Hz, AC  
dB  
ppm of FSR, rms  
Bits  
2.7  
Resolution  
24  
No Missing Codes  
Common-Mode Rejection  
Gain Error  
24  
102  
0.1  
±30  
1:1  
88  
Bits  
dB  
90  
70  
1
% of FSR  
ppm of FSR  
Offset Error  
±100  
Gain Sensitivity to VREF  
Power-Supply Rejection Ratio  
dB  
PERFORMANCE OVER TEMPERATURE  
Offset Drift  
Gain Drift  
0.07  
0.4  
ppm/°C  
ppm/°C  
VOLTAGE REFERENCE  
VREF  
0.5  
4.096  
32  
VDD  
V
Load Current  
µA  
NOTE: (1) Applies to full-differential signals.  
ADS1254  
2
SBAS213  
ELECTRICAL CHARACTERISTICS (Cont.)  
All specifications at TMIN to TMAX, AVDD = +5V, DVDD = +1.8V. CLK = 8MHz, and VREF = 4.096, unless otherwise specified.  
ADS1254E  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
DIGITAL INPUT/OUTPUT  
Logic Family  
CMOS  
Logic Level: VIH  
0.65 DVDD  
0.3  
DVDD 0.4  
DVDD + 0.3  
0.35 DVDD  
V
V
V
V
V
VIL  
VOH  
VOL  
IOH = 500µA  
IOL = 500µA  
0.4  
Input (SCLK, CLK, CHSEL0, CHSEL1) Hysteresis  
Data Format  
0.6  
Offset Binary Twos Complement  
POWER-SUPPLY REQUIREMENTS  
Power Supply Voltage  
DVDD  
AVDD  
AVDD = +5V  
DVDD = +1.8V  
1.8  
4.75  
3.6  
5.25  
1.15  
0.4  
6.5  
1
VDC  
VDC  
mA  
mA  
mW  
µA  
5
Quiescent Current  
0.8  
0.2  
4.3  
0.4  
Operating Power  
Power-Down Current  
TEMPERATURE RANGE  
Operating  
Storage  
40  
60  
+85  
+100  
°C  
°C  
PIN CONFIGURATION  
PIN DESCRIPTIONS  
PIN  
NAME  
PIN DESCRIPTION  
Top View  
SSOP-20  
1
CH1+  
Analog Input: Positive Input of the Differen-  
tial Analog Input  
2
3
4
5
6
CH1–  
CH2+  
CH2–  
CH3+  
CH3–  
Analog Input: Negative Input of the Differ-  
ential Analog Input  
Analog Input: Positive Input of the Differen-  
tial Analog Input  
Analog Input: Negative Input of the Differ-  
ential Analog Input  
Analog Input: Positive Input of the Differen-  
tial Analog Input  
CH1+  
CH1–  
CH2+  
CH4+  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
Analog Input: Negative Input of the Differ-  
ential Analog Input  
7
8
AVDD  
CLK  
Input: Analog Power Supply Voltage, +5V  
Digital Input: Device System Clock. The  
system clock is in the form of a CMOS-  
compatible clock. This is a Schmitt-Trigger  
input  
Input: Digital Power Supply Voltage  
No Connection  
No Connection  
CH4–  
VREF  
3
9
DVDD  
NC  
NC  
CH2–  
CH3+  
CH3–  
AVDD  
4
AGND  
10  
11  
12  
13  
DGND  
DOUT/DRDY  
Input: Digital Ground  
CHSEL0  
CHSEL1  
SCLK  
5
ADS1254E  
Digital Output: Serial Data Output/Data  
Ready. This output indicates that a new  
output word is available from the ADS1254  
data output register. The serial data is  
clocked out of the serial data output shift  
register using SCLK.  
6
7
14  
SCLK  
Digital Input: Serial Clock. The serial clock  
is in the form of a CMOS-compatible clock.  
The serial clock operates independently  
from the system clock, therefore, it is pos-  
sible to run SCLK at a higher frequency  
than CLK. The normal state of SCLK is  
LOW. Holding SCLK HIGH will either ini-  
tiate a modulator reset for synchronizing  
multiple converters or enter power-down  
mode. This is a Schmitt-Trigger input.  
Digital Input: Used to select analog input  
channel. This is a Schmitt-Trigger Input  
Digital Input: Used to select analog input  
channel. This is a Schmitt-Trigger Input  
Input: Analog Ground  
CLK  
DVDD  
NC  
8
DOUT/DRDY  
9
DGND  
NC  
10  
15  
16  
CHSEL1  
CHSEL0  
17  
18  
19  
AGND  
VREF  
CH4–  
Analog Input: Reference Voltage Input  
Analog Input: Negative Input of the Differ-  
ential Analog Input  
20  
CH4+  
Analog Input: Positive Input of the Differen-  
tial Analog Input  
ADS1254  
3
SBAS213  
TYPICAL CHARACTERISTICS  
At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.  
RMS NOISE vs DATA OUTPUT RATE  
EFFECTIVE RESOLUTION vs DATA OUTPUT RATE  
2.0  
1.9  
1.8  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
20.0  
19.8  
19.6  
19.4  
19.2  
19.0  
18.8  
18.6  
18.4  
18.2  
18.0  
100  
1k  
10k  
100k  
100  
1k  
10k  
100k  
Data Ouput Rate (Hz)  
Data Ouput Rate (Hz)  
RMS NOISE vs TEMPERATURE  
EFFECTIVE RESOLUTION vs TEMPERATURE  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
20  
19.8  
19.6  
19.4  
19.2  
19.0  
18.8  
18.6  
18.4  
18.2  
18.0  
40  
20  
0
20  
40  
60  
80  
100  
40  
20  
0
20  
40  
60  
80  
100  
Temperature (°C)  
Temperature (°C)  
RMS NOISE vs VREF Voltage  
RMS NOISE vs VREF Voltage  
10  
9
8
7
6
5
4
3
2
1
0
12  
10  
8
6
4
2
0
0.5  
1.0  
1.5 2.0  
2.5  
3.0 3.5  
4.0  
4.5  
5.0  
0.5 1.0  
1.5  
2.0  
2.5 3.0  
3.5  
4.0  
4.5  
5
VREF Voltage (V)  
V
REF Voltage (V)  
ADS1254  
4
SBAS213  
TYPICAL CHARACTERISTICS (Cont.)  
At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.  
RMS NOISE vs INPUT VOLTAGE  
INTEGRAL NONLINEARITY vs TEMPERATURE  
2
1.5  
1
2.5  
2.0  
1.5  
1.0  
0.5  
0
0.5  
0
5  
4  
3  
2  
1  
0
1
2
3
4
5
40  
20  
0
20  
40  
60  
80  
100  
Input Voltage (V)  
Temperature (°C)  
OFFSET vs TEMPERATURE  
INTEGRAL NON-LINEARITY vs DATA OUTPUT RATE  
20  
18  
16  
14  
12  
10  
8
6
5
4
3
2
1
0
6
4
2
0
40  
20  
0
20  
40  
60  
80  
100  
100  
1k  
10k  
100k  
Temperature (°C)  
Data Output Rate (Hz)  
GAIN ERROR vs TEMPERATURE  
PSR vs CLK FREQUENCY  
600  
580  
560  
540  
520  
500  
480  
0  
10  
20  
30  
40  
50  
60  
70  
80  
90  
100  
60  
40  
20  
0
20  
40  
60  
80  
100  
1
2
3
4
5
6
7
8
Temperature (°C)  
Clock Frequency (MHz)  
ADS1254  
5
SBAS213  
TYPICAL CHARACTERISTICS (Cont.)  
At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.  
CMR vs COMMON-MODE FREQUENCY  
CMR AT 60Hz vs CLK FREQUENCY  
70  
75  
50  
60  
80  
70  
85  
80  
90  
90  
95  
100  
110  
100  
105  
0
1
2
3
4
5
6
7
8
10  
100  
1k  
10k  
100k  
Clock Frequency (MHz)  
Common-Mode Signal Frequency (Hz)  
CURRENT vs TEMPERATURE  
POWER DISSIPATION vs CLK FREQUENCY  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
Analog (5V)  
Digital (3.3V)  
Digital (1.8V)  
AVDD (5V)  
DVDD (1.8V)  
40  
20  
0
20  
40  
60  
80  
100  
0
1
2
3
4
5
6
7
8
Temperature (°C)  
Clock Frequency (MHz)  
TYPICAL FFT  
(1kHz input at 0.1dB less than full-scale)  
V
REF CURRENT vs CLK FREQUENCY  
0
20  
35  
30  
25  
20  
15  
10  
5
40  
60  
80  
100  
120  
140  
160  
0
0
1
2
3
4
5
6
7
8
9
10 11  
0
1
2
3
4
5
6
7
8
Input Signal Frequency (kHz)  
Clock Frequency (MHz)  
ADS1254  
6
SBAS213  
20.8kHz with a –3dB frequency of 4.24kHz. The –3dB  
frequency scales with the system clock frequency.  
THEORY OF OPERATION  
The ADS1254 is a precision, high-dynamic range, 24-bit,  
delta-sigma, A/D converter capable of achieving very  
high-resolution digital results at high data rates.  
The analog-input signal is sampled at a rate determined by the  
frequency of the system clock (CLK). The sampled analog  
input is modulated by the delta-sigma A/D modulator, which  
is followed by a digital filter. A sinc5 digital low-pass filter  
processes the output of the delta-sigma modulator and writes  
the result into the data-output register. The DOUT/DRDY pin  
is pulled LOW, indicating that new data is available to be read  
by the external microcontroller/microprocessor. As shown in  
the block diagram, the main functional blocks of the ADS1254  
are the fourth-order delta-sigma modulator, a digital filter,  
control logic, and a serial interface. Each of these functional  
blocks is described below.  
To ensure the best linearity of the ADS1254, a fully differen-  
tial signal is recommended.  
INPUT MULTIPLEXER  
The CHSEL1 and CHSEL0 pins are used to select the analog  
input channel, as shown in Table I. The recommended  
method for changing channels is to change them after the  
conversion from the previous channel has been completed  
and read. When a channel is changed, internal logic senses  
the change on the falling edge of CLK and resets the  
conversion process. The conversion data from the new  
channel is valid on the first DRDY after the channel change.  
When multiplexing inputs, it is possible to achieve sample  
rates close to 4kHz. This is due to the fact that it requires five  
internal conversion cycles for the data to fully settle. The  
data also must be read before the channel is changed. The  
DRDY signal indicates a valid result after the five cycles  
have occurred.  
ANALOG INPUT  
The ADS1254 contains a fully differential analog input. In order  
to provide low system noise, common-mode rejection of 102dB,  
and excellent power-supply rejection, the design topology is  
based on a fully differential switched-capacitor architecture. The  
bipolar input voltage range is from –4.096V to +4.096V, when  
the reference input voltage equals +4.096V. The bipolar range is  
with respect to –VIN, and not with respect to GND.  
BIPOLAR INPUT  
CHSEL1  
CHSEL0  
CHANNEL  
0
0
1
1
0
1
0
1
CH1  
CH2  
CH3  
CH4  
Figure 1 shows the basic input structure of the ADS1254.  
The impedance is directly related to the sampling frequency  
of the input capacitor that is set by the CLK rate. Higher  
CLK rates result in lower impedance, and lower CLK rates  
result in higher impedance.  
TABLE I. Channel Selection.  
Each of the differential inputs of the ADS1254 must stay  
between AGND and AVDD. With a reference voltage at less  
than half of AVDD, one input can be tied to the reference  
voltage, and the other input can range from AGND to  
2 • VREF. By using a three op-amp circuit featuring a single  
amplifier and four external resistors, the ADS1254 can be  
configured to accept bipolar inputs referenced to ground.  
The conventional ±2.5V, ±5V, and ±10V input ranges can  
be interfaced to the ADS1254 using the resistor values  
shown in Figure 2.  
RSW  
(1300typical)  
Internal  
AIN  
Circuitry  
CINT  
(6pF typical)  
Modulator Frequency  
= fMOD  
VCM  
FIGURE 1. Analog-Input Structure.  
R1  
The input impedance of the analog input changes with the  
ADS1254 system clock frequency (CLK). The relationship is:  
10k  
AIN Impedance () = (8MHz/CLK) • 125,000  
+IN  
OPA4350  
20kΩ  
ADS1254  
VREF  
With regard to the analog-input signal, the overall analog  
performance of the device is affected by three items: first, the  
input impedance can affect accuracy. If the source impedance  
of the input signal is significant, or if there is passive filtering  
prior to the ADS1254, a significant portion of the signal can be  
lost across this external impedance. The magnitude of the  
effect is dependent on the desired system performance.  
Bipolar  
Input  
IN  
R
2
OPA4350  
OPA4350  
Second, the current into or out of the analog inputs must be  
limited. Under no conditions should the current into or out  
of the analog inputs exceed 10mA.  
REF  
2.5V  
BIPOLAR INPUT  
R1  
R2  
±10V  
±5V  
2.5kΩ  
5kΩ  
5kΩ  
10kΩ  
20kΩ  
Third, to prevent aliasing of the input signal, the analog-input  
signal must be band limited. The bandwidth of the A/D  
converter is a function of the system clock frequency. With a  
system clock frequency of 8MHz, the data-output rate is  
±2.5V  
10kΩ  
FIGURE 2. Level Shift Circuit for Bipolar Input Ranges.  
ADS1254  
7
SBAS213  
DELTA-SIGMA MODULATOR  
REFERENCE INPUT  
The ADS1254 operates from a nominal system clock fre-  
quency of 8MHz. The modulator frequency is fixed in  
relation to the system clock frequency. The system clock  
frequency is divided by 6 to derive the modulator frequency.  
Therefore, with a system clock frequency of 8MHz, the  
modulator frequency is 1.333MHz. Furthermore, the  
oversampling ratio of the modulator is fixed in relation to the  
modulator frequency. The oversampling ratio of the modu-  
lator is 64, and with the modulator frequency running at  
1.333MHz, the data rate is 20.8kHz. Using a slower system  
clock frequency will result in a lower data output rate, as  
shown in Table II.  
Reference input takes an average current of 32µA with a  
8MHz system clock. This current will be proportional to the  
system clock. A buffered reference is recommended for the  
ADS1254. The recommended reference circuit is shown in  
Figure 3.  
Reference voltages higher than 4.096V will increase the  
full-scale range, while the absolute internal circuit noise of  
the converter remains the same. This will decrease the noise  
in terms of ppm of full scale, which increases the effective  
resolution (see the Typical Characteristic “RMS Noise vs  
VREF Voltage”).  
DIGITAL FILTER  
CLK (MHz)  
DATA OUTPUT RATE (Hz)  
The digital filter of the ADS1254, referred to as a sinc5 filter,  
computes the digital result based on the most recent outputs  
from the delta-sigma modulator. At the most basic level, the  
digital filter can be thought of as simply averaging the  
modulator results in a weighted form and presenting this  
average as the digital output. The digital output rate, or data  
rate, scales directly with the system CLK frequency. This  
allows the data output rate to be changed over a very wide  
range (five orders of magnitude) by changing the system  
CLK frequency. However, it is important to note that the  
–3dB point of the filter is 0.2035 times the data output rate,  
so the data output rate should allow for sufficient margin to  
prevent attenuation of the signal of interest.  
8(1)  
20,833  
19,200  
16,000  
15,625  
12,800  
9,600  
8,000  
6,400  
4,800  
2,400  
1,200  
1,000  
500  
100  
60  
50  
30  
25  
20  
16.67  
15  
12.50  
10  
7.372800(1)  
6.144000(1)  
6.000000(1)  
4.915200(1)  
3.686400(1)  
3.072000(1)  
2.457600(1)  
1.843200(1)  
0.921600  
0.460800  
0.384000  
0.192000  
0.038400  
0.023040  
0.019200  
0.011520  
0.009600  
0.007680  
0.006400  
0.005760  
0.004800  
0.003840  
Since the conversion result is essentially an average, the  
data-output rate determines the location of the resulting  
notches in the digital filter (see Figure 4). Note that the first  
notch is located at the data-output rate frequency, and  
subsequent notches are located at integer multiples of the  
data-output rate to allow for rejection of not only the  
fundamental frequency, but also harmonic frequencies. In  
this manner, the data-output rate can be used to set specific  
notch frequencies in the digital filter response.  
NOTE: (1) Standard Clock Oscillator.  
TABLE II. CLK Rate versus Data Output Rate.  
For example, if the rejection of power-line frequencies is  
desired, then the data-output rate can simply be set to the  
power-line frequency. For 50Hz rejection, the system CLK  
+5V  
+5V  
0.10µF  
7
4.99kΩ  
2
3
To VREF  
Pin 18 of  
6
OPA350  
10kΩ  
the ADS1254  
1
+
10µF  
0.1µF  
+
10µF  
0.10µF  
4
LM404-4.1  
FIGURE 3. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1254.  
ADS1254  
8
SBAS213  
DIGITAL FILTER RESPONSE  
NORMALIZED DIGITAL FILTER RESPONSE  
0
20  
0
20  
40  
40  
60  
60  
80  
80  
100  
120  
140  
160  
180  
200  
100  
120  
140  
160  
180  
200  
0
50  
100  
150  
200  
250  
300  
0
1
2
3
4
5
6
7
8
9
10  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 4. Normalized Digital Filter Response.  
FIGURE 5. Digital Filter Response (50Hz).  
DIGITAL FILTER RESPONSE  
0
DIGITAL FILTER RESPONSE  
0
20  
40  
20  
40  
60  
60  
80  
80  
100  
120  
140  
160  
180  
200  
100  
120  
140  
160  
180  
200  
0
50  
100  
150  
200  
250  
300  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 6. Digital Filter Response (60Hz).  
FIGURE 7. Digital Filter Response (10Hz).  
DIGITAL FILTER RESPONSE  
0
DIGITAL FILTER RESPONSE  
0
20  
40  
20  
40  
60  
60  
80  
80  
100  
120  
140  
160  
180  
200  
100  
120  
140  
160  
180  
200  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 8. Expanded Digital Filter Response (50Hz with a  
50Hz Data Output Rate).  
FIGURE 9. Expanded Digital Filter Response (50Hz with a  
10Hz Data Output Rate).  
ADS1254  
9
SBAS213  
DIGITAL FILTER RESPONSE  
DIGITAL FILTER RESPONSE  
0
20  
0
20  
40  
40  
60  
60  
80  
80  
100  
120  
140  
160  
180  
200  
100  
120  
140  
160  
180  
200  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
Frequency (Hz)  
Frequency (Hz)  
FIGURE 10. Expanded Digital Filter Response (60Hz with  
a 60Hz Data Output Rate).  
FIGURE 11. Expanded Digital Filter Response (60Hz with  
a 10Hz Data Output Rate).  
frequency should be 19.200kHz, this will set the data-output  
rate to 50Hz (see Table I and Figure 5). For 60Hz rejection,  
the system CLK frequency should be 23.040kHz, this will set  
the data-output rate to 60Hz (see Table I and Figure 6). If both  
50Hz and 60Hz rejection is required, then the system CLK  
should be 3.840kHz; this will set the data-output rate to 10Hz  
and reject both 50Hz and 60Hz (See Table I and Figure 7).  
The digital filter is described by the following transfer func-  
tion:  
5
π • f 64  
sin  
fMOD  
H f =  
( )  
π • f  
64sin  
or  
fMOD  
There is an additional benefit in using a lower data-output  
rate. It provides better rejection of signals in the frequency  
band of interest. For example, with a 50Hz data-output rate,  
a significant signal at 75Hz may alias back into the passband  
at 25Hz. This is due to the fact that rejection at 75Hz may only  
be 66dB in the stopband—frequencies higher than the first-  
notch frequency (see Figure 5). However, setting the data-  
output rate to 10Hz will provide 135dB rejection at 75Hz (see  
Figure 7). A similar benefit is gained at frequencies near the  
data-output rate (see Figures 8, 9, 10, and 11). For example,  
with a 50Hz data-output rate, rejection at 55Hz may only be  
105dB (see Figure 8). However, with a 10Hz data-output rate,  
rejection at 55Hz will be 122dB (see Figure 9). If a slower  
data-output rate does not meet the system requirements, then  
the analog front end can be designed to provide the needed  
attenuation to prevent aliasing. Additionally, the data-output  
rate may be increased and additional digital filtering may be  
done in the processor or controller.  
5
1– z–64  
H z =  
( )  
64• 1– z–1  
(
)
The digital filter requires five conversions to fully settle. The  
modulator has an oversampling ratio of 64, therefore, it  
requires 5 • 64, or 320 modulator results, or clocks, to fully  
settle. Since the modulator clock is derived from the system  
clock (CLK) (modulator clock = CLK ÷ 6), the number of  
system clocks required for the digital filter to fully settle is  
5 • 64 • 6, or 1920 CLKs. This means that any significant  
step change at the analog input requires five full conversions  
to settle. However, if the step change at the analog input  
occurs asynchronously to the DOUT/DRDY pulse, six con-  
versions are required to ensure full settling.  
ADS1254  
10  
SBAS213  
time defined by t4. If more than 24 SCLKs were provided  
during DOUT mode, the DOUT/DRDY line would stay  
LOW until the time defined by t4.  
CONTROL LOGIC  
The control logic is used for communications and control of  
the ADS1254.  
The internal data pointer for shifting data out on  
DOUT/DRDY is reset on the falling edge of the time defined  
by t1 and t4. This ensures that the first bit of data shifted out  
of the ADS1254 after DRDY mode is always the MSB of  
new data.  
Power-Up Sequence  
Prior to power-up, all digital and analog-input pins must be  
LOW. During power-up, these signal inputs should never  
exceed +AVDD or +DVDD  
.
Once the ADS1254 powers up, the DOUT/DRDY line will  
pulse LOW on the first conversion for which the data is valid  
from the analog input signal.  
SYNCHRONIZING MULTIPLE CONVERTERS  
The normal state of SCLK is LOW, however, by holding  
SCLK HIGH, multiple ADS1254s can be synchronized. This  
is accomplished by holding SCLK HIGH for at least four, but  
less than twenty, consecutive DOUT/DRDY cycles (see Fig-  
ure 14). After the ADS1254 circuitry detects that SCLK has  
been held HIGH for four consecutive DOUT/DRDY cycles,  
the DOUT/DRDY pin will pulse LOW for 3 CLK cycles and  
then be held HIGH, and the modulator will be held in a reset  
state. The modulator will be released from reset and synchro-  
nization will occur on the falling edge of SCLK. With  
multiple converters, the falling edge transition of SCLK must  
occur simultaneously on all devices. It is important to note  
that prior to synchronization, the DOUT/DRDY pulse of  
multiple ADS1254s in the system could have a difference in  
timing up to one DRDY period. Therefore, to ensure synchro-  
nization, the SCLK should be held HIGH for at least five  
DRDY cycles. The first DOUT/DRDY pulse after the falling  
edge of SCLK will occur at t14. The first DOUT/DRDY pulse  
indicates valid data.  
DOUT/DRDY  
The DOUT/DRDY output signal alternates between two  
modes of operation. The first mode of operation is the Data  
Ready mode (DRDY) to indicate that new data has been  
loaded into the data-output register and is ready to be read.  
The second mode of operation is the Data Output (DOUT)  
mode and is used to serially shift data out of the Data Output  
Register (DOR). The time domain partitioning of the DRDY  
and DOUT function as shown in Figure 12.  
See Figure 13 for the basic timing of DOUT/DRDY. During  
the time defined by t2, t3, and t4, the DOUT/DRDY pin  
functions in DRDY mode. The state of the DOUT/DRDY  
pin would be HIGH prior to the internal transfer of new data  
to the DOR. The result of the A/D conversion would be  
written to the DOR from MSB to LSB in the time defined by  
t1 (see Figures 12 and 13). The DOUT/DRDY line would  
then pulse LOW for the time defined by t2, and then pulse  
HIGH for the time defined by t3 to indicate that new data  
was available to be read. At this point, the function of the  
DOUT/DRDY pin would change to DOUT mode. Data  
would be shifted out on the pin after t7. The device commu-  
nicating with the ADS1254 can provide SCLKs to the  
ADS1254 after the time defined by t6. The normal mode of  
reading data from the ADS1254 would be for the device  
reading the ADS1254 to latch the data on the rising edge of  
SCLK (since data is shifted out of the ADS1254 on the  
falling edge of SCLK). In order to retrieve valid data, the  
entire DOR must be read before the DOUT/DRDY pin  
reverts back to DRDY mode.  
POWER-DOWN MODE  
The normal state of SCLK is LOW, however, by holding  
SCLK HIGH, the ADS1254 will enter power-down mode.  
This is accomplished by holding SCLK HIGH for at least  
twenty consecutive DOUT/DRDY periods (see Figure 15).  
After the ADS1254 circuitry detects that SCLK has been  
held HIGH for four consecutive DOUT/DRDY cycles, the  
DOUT/DRDY pin will pulse LOW for 3 CLK cycles and  
then be held HIGH, and the modulator will be held in a  
reset state. If SCLK is held HIGH for an additional sixteen  
DOUT/DRDY periods, the ADS1254 will enter  
power-down mode. The part will be released from power-  
down mode on the falling edge of SCLK. It is important to  
note that the DOUT/DRDY pin will be held HIGH after four  
DOUT/DRDY cycles, but power-down mode will not be  
entered for an additional sixteen DOUT/DRDY periods. The  
first DOUT/DRDY pulse after the falling edge of SCLK will  
occur at t16 and will indicate valid data. Subsequent DOUT/  
DRDY pulses will occur normally.  
If SCLKs were not provided to the ADS1254 during the  
DOUT mode, the MSB of the DOR would be present on the  
DOUT/DRDY line until the time defined by t4. If an incom-  
plete read of the ADS1254 took place while in DOUT mode  
(i.e., less than 24 SCLKs were provided), the state of the last  
bit read would be present on the DOUT/DRDY line until the  
DRDY Mode  
t4  
DRDY Mode  
DOUT Mode  
DOUT Mode  
t2  
t3  
DATA  
DATA  
DATA  
DOUT/DRDY  
t1  
FIGURE 12. DOUT/DRDY Partitioning.  
ADS1254  
11  
SBAS213  
SERIAL INTERFACE  
ISOLATION  
The serial interface of the ADS1254 provides for simple  
isolation methods. The CLK signal can be local to the  
ADS1254, which then only requires two signals (SCLK and  
DOUT/DRDY) to be used for isolated data acquisition. The  
channel select signals (CHSEL0, CHSEL1) will also need to  
be isolated unless a counter is used to auto multiplex the  
channels.  
The ADS1254 includes a simple serial interface that can be  
connected to microcontrollers and digital signal processors  
in a variety of ways. Communications with the ADS1254  
can commence on the first detection of the DOUT/DRDY  
pulse after power up.  
It is important to note that the data from the ADS1254 is a  
24-bit result transmitted MSB-first in Offset Two’s Comple-  
ment format, as shown in Table IV.  
DIFFERENTIAL VOLTAGE INPUT  
DIGITAL OUTPUT (HEX)  
The data must be clocked out before the ADS1254 enters  
DRDY mode to ensure reception of valid data, as described  
in the DOUT/DRDY section of this data sheet.  
+Full Scale  
Zero  
Full Scale  
7FFFFFH  
000000H  
800000H  
TABLE IV. ADS1254 Data Format (Offset Two's Comple-  
ment).  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
tOSC  
tDRDY  
DRDY Mode  
DOUT Mode  
CLK Period  
Conversion Cycle  
DRDY Mode  
DOUT Mode  
DOR Write Time  
DOUT/DRDY LOW Time  
125  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
384 tOSC  
36 tOSC  
348 tOSC  
6 tOSC  
6 tOSC  
6 tOSC  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
t10  
t11  
t12  
t13  
t14  
t15  
t16  
t17  
t18  
DOUT/DRDY HIGH Time (Prior to Data Out)  
DOUT/DRDY HIGH Time (Prior to Data Ready)  
Rising Edge of CLK to Falling Edge of DOUT/DRDY  
End of DRDY Mode to Rising Edge of First SCLK  
End of DRDY Mode to Data Valid (Propagation Delay)  
Falling Edge of SCLK to Data Valid (Hold Time)  
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)  
SCLK Setup Time for Synchronization or Power Down  
DOUT/DRDY Pulse for Synchronization or Power Down  
Rising Edge of SCLK Until Start of Synchronization  
Synchronization Time  
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode  
Rising Edge of SCLK Until Start of Power Down  
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode  
Falling Edge of Last DOUT/DRDY to Start of Power Down  
DOUT/DRDY High Time After Mux Change.  
24 tOSC  
50  
50  
50  
30  
5
30  
3 tOSC  
1537 CLK  
0.5 CLK  
7679 CLK  
6143.5 CLK  
2042.5 tOSC  
7681 CLK  
2318.5 tOSC  
6144.5 tOSC  
2043.5 tosc  
TABLE III. Digital Timing.  
t18  
DATA  
DATA  
DOUT/DRDY  
CHSEL0, CHSEL1  
MUX CHANGE  
FIGURE 13. Multiplexer Operation.  
ADS1254  
12  
SBAS213  
ADS1254  
13  
SBAS213  
could include:  
LAYOUT  
• Multiple ADS1254s  
POWER SUPPLY  
• Extensive Analog Signal Processing  
• One or More Microcontrollers, Digital Signal Processors,  
or Microprocessors  
• Many Different Clock Sources  
• Interconnections to Various Other Systems  
The power supply should be well regulated and low noise.  
For designs requiring very high resolution from the ADS1254,  
power-supply rejection will be a concern. Avoid running  
digital lines under the device as they may couple noise onto  
the die. High-frequency noise can capacitively couple into  
the analog portion of the device and will alias back into the  
passband of the digital filter, affecting the conversion result.  
This clock noise will cause an offset error.  
High resolution will be very difficult to achieve for this  
design. The approach would be to break the system into as  
many different parts as possible. For example, each ADS1254  
may have its own “analog” processing front end.  
GROUNDING  
DEFINITION OF TERMS  
The analog and digital sections of the system design should  
be carefully and cleanly partitioned. Each section should  
have its own ground plane with no overlap between them.  
AGND should be connected to the analog ground plane, as  
well as all other analog grounds. Do not join the analog and  
digital ground planes on the board, but instead connect the  
two with a moderate signal trace. For multiple converters,  
connect the two ground planes at one location as central to  
all of the converters as possible. In some cases, experimen-  
tation may be required to find the best point to connect the  
two planes together. The printed circuit board can be de-  
signed to provide different analog/digital ground connec-  
tions via short jumpers. The initial prototype can be used to  
establish which connection works best.  
An attempt has been made to be consistent with the termi-  
nology used in this data sheet. In that regard, the definition  
of each term is given as follows:  
Analog-Input Differential Voltage—for an analog signal  
that is fully differential, the voltage range can be compared  
to that of an instrumentation amplifier. For example, if both  
analog inputs of the ADS1254 are at 2.048V, the differen-  
tial voltage is 0V. If one analog input is at 0V and the other  
analog input is at 4.096V, then the differential voltage  
magnitude is 4.096V. This is the case regardless of which  
input is at 0V and which is at 4.096V. The digital-output  
result, however, is quite different. The analog-input differ-  
ential voltage is given by the following equation:  
+VIN – (–VIN)  
DECOUPLING  
A positive digital output is produced whenever the  
analog-input differential voltage is positive, while a nega-  
tive digital output is produced whenever the differential is  
negative. For example, a positive full-scale output is pro-  
duced when the converter is configured with a 4.096V  
reference, and the analog-input differential is 4.096V. The  
negative full-scale output is produced when the differential  
voltage is –4.096V. In each case, the actual input voltages  
must remain within the –0.3V to +AVDD range.  
Good decoupling practices should be used for the ADS1254  
and for all components in the design. All decoupling capaci-  
tors, and specifically the 0.1µF ceramic capacitors, should  
be placed as close as possible to the pin being decoupled. A  
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic  
capacitor, should be used to decouple Supply to ground.  
SYSTEM CONSIDERATIONS  
Actual Analog-Input Voltage—the voltage at any one  
analog input relative to AGND.  
The recommendations for power supplies and grounding  
will change depending on the requirements and specific  
design of the overall system. Achieving 24 bits of noise  
performance is a great deal more difficult than achieving 12  
bits of noise performance. In general, a system can be  
broken up into four different stages:  
Full-Scale Range (FSR)—as with most A/D Converters,  
the full-scale range of the ADS1254 is defined as the “input”  
that produces the positive full-scale digital output minus the  
“input” that produces the negative full-scale digital output.  
For example, when the converter is configured with a 4.096V  
reference, the differential full-scale range is:  
• Analog Processing  
• Analog Portion of the ADS1254  
• Digital Portion of the ADS1254  
• Digital Processing  
[4.096V (positive full scale) – (–4.096V) (negative full scale)] =  
8.192V  
For the simplest system consisting of minimal analog signal  
processing (basic filtering and Gain), a microcontroller, and  
one clock source, one can achieve high resolution by pow-  
ering all components by a common power supply. In addi-  
tion, all components could share a common ground plane.  
Thus, there would be no distinctions between “analog”  
power and ground, and “digital” power and ground. The  
layout should still include a power plane, a ground plane,  
and careful decoupling. In a more extreme case, the design  
Least Significant Bit (LSB) Weight—this is the theoreti-  
cal amount of voltage that the differential voltage at the  
analog input would have to change in order to observe a  
change in the output data of one least significant bit. It is  
computed as follows:  
Full – Scale Range 2VREF  
LSB Weight =  
=
2N 1  
2N 1  
where N is the number of bits in the digital output.  
ADS1254  
14  
SBAS213  
Conversion Cycle—as used here, a conversion cycle refers  
to the time period between DOUT/DRDY pulses.  
Noise Reduction—for random noise, the ER can be im-  
proved with averaging. The result is the reduction in noise by  
the factor N, where N is the number of averages, as shown  
in Table V. This can be used to achieve true 24-bit perfor-  
mance at a lower data rate. To achieve 24 bits of resolution,  
more than 24 bits must be accumulated. A 36-bit accumulator  
Effective Resolution (ER)—of the ADS1254 in a particular  
configuration can be expressed in two different units:  
bits rms (referenced to output) and µVrms (referenced to  
input). Computed directly from the converter's output data,  
each is a statistical calculation based on a given number of  
results. Noise occurs randomly; the rms value represents a  
statistical measure that is one standard deviation. The ER in  
bits can be computed as follows:  
is required to achieve an ER of 24 bits. Table V uses VREF  
=
4.096V, with the ADS1254 outputting data at 20kHz, a 4096  
point average will take 204.8ms. The benefits of averaging  
will be degraded if the input signal drifts during that 200ms.  
2• VREF  
20log  
N
NOISE  
REDUCTION  
FACTOR  
ER  
IN  
Vrms  
ER  
IN  
BITS rms  
(Number  
of Averages)  
Vrms noise  
ER in bits rms =  
6.02  
1
2
1
1.414  
2
14.6µV  
10.3µV  
7.3µV  
19.1  
19.6  
20.1  
20.6  
21.1  
21.6  
22.1  
22.6  
23.1  
23.6  
24.1  
24.6  
25.1  
The 2 • VREF figure in each calculation represents the  
full-scale range of the ADS1254. This means that both units  
are absolute expressions of resolution—the performance in  
different configurations can be directly compared, regard-  
less of the units.  
4
8
2.82  
4
5.16µV  
3.65µV  
2.58µV  
1.83µV  
1.29µV  
0.91µV  
0.65µV  
0.46µV  
0.32µV  
0.23µV  
16  
32  
5.66  
8
64  
128  
256  
512  
1024  
2048  
4096  
11.3  
16  
fMODfrequency of the modulator and the frequency the  
input is sampled.  
22.6  
32  
CLK Frequency  
45.25  
64  
fMOD  
=
6
TABLE V. Averaging.  
fDATAData output rate.  
fMOD CLK Frequency  
fDATA  
=
=
64  
384  
ADS1254  
15  
SBAS213  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Dec-2004  
PACKAGING INFORMATION  
Orderable Device  
ADS1254E  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SSOP/  
QSOP  
DBQ  
20  
56  
None  
CU SNPB  
Level-3-250C-168 HR  
ADS1254E/2K5  
SSOP/  
QSOP  
DBQ  
20  
2500  
None  
CU SNPB  
Level-3-250C-168 HR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional  
product content details.  
None: Not yet available Lead (Pb-Free).  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,  
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
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