ADS1255 [BB]
Very Low Noise, 24-Bit Analog-to-Digital Converter; 极低噪声, 24位模拟数字转换器![ADS1255](http://pdffile.icpdf.com/pdf1/p00072/img/icpdf/ADS1255_377948_icpdf.jpg)
型号: | ADS1255 |
厂家: | ![]() |
描述: | Very Low Noise, 24-Bit Analog-to-Digital Converter |
文件: | 总39页 (文件大小:422K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢐ ꢕꢙ ꢚꢋ ꢛꢜ
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
ꢀꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇꢅ ꢈꢉ ꢁꢊ ꢋꢌ ꢍ ꢎꢈ ꢏ
ꢐ ꢑ ꢒꢓ ꢅꢔꢍ ꢏ ꢅꢍ ꢕ ꢈꢔ ꢈꢏ ꢒꢓꢖ ꢗ ꢅꢑ ꢘꢁꢂ ꢏ ꢁꢂ
FEATURES
DESCRIPTION
The ADS1255 and ADS1256 are extremely low-noise,
24-bit analog-to-digital (A/D) converters. They provide
complete high-resolution measurement solutions for the
most demanding applications.
D
24 Bits, No Missing Codes
− All Data Rates and PGA Settings
Up to 23 Bits Noise-Free Resolution
0.0010% Nonlinearity (max)
D
D
D
D
The converter is comprised of a 4th-order, delta-sigma
(∆Σ) modulator followed by a programmable digital filter. A
flexible input multiplexer handles differential or
single-ended signals and includes circuitry to verify the
integrity of the external sensor connected to the inputs.
The selectable input buffer greatly increases the input
impedance and the low-noise programmable gain
amplifier (PGA) provides gains from 1 to 64 in binary steps.
The programmable filter allows the user to optimize
between a resolution of up to 23 bits noise-free and a data
rate of up to 30k samples per second (SPS). The
converters offer fast channel cycling for measuring
multiplexed inputs and can also perform one-shot
conversions that settle in just a single cycle.
Data Output Rates to 30kSPS
Fast Channel Cycling
− 18.6 Bits Noise-Free (21.3 Effective Bits)
at 1.45kHz
D
D
One-Shot Conversions with Single-Cycle
Settling
Flexible Input Multiplexer with Sensor Detect
− Four Differential Inputs (ADS1256 only)
− Eight Single-Ended Inputs (ADS1256 only)
D
D
D
D
D
D
D
Chopper-Stabilized Input Buffer
Low-Noise PGA: 27nV Input-Referred Noise
Self and System Calibration for All PGA
Settings
Communication is handled over an SPI-compatible serial
interface that can operate with a 2-wire connection.
Onboard calibration supports both self and system
correction of offset and gain errors for all the PGA settings.
Bidirectional digital I/Os and a programmable clock output
driver are provided for general use. The ADS1255 is
packaged in an SSOP-20, and the ADS1256 in an
SSOP-28.
5V Tolerant SPI-Compatible Serial Interface
Analog Supply: 5V
Digital Supply: 1.8V to 3.6V
Power Dissipation
− As Low as 38mW in Normal Mode
− 0.4mW in Standby Mode
AVDD
VREFP VREFN
DVDD
APPLICATIONS
AIN0
AIN1
XTAL1/CLKIN
XTAL2
Clock
Generator
D
D
D
D
D
Weigh Scales
Scientific Instrumentation
Industrial Process Control
Medical Equipment
1:64
PGA
AIN2
AIN3
Mux
and
Sensor
Detect
RESET
4th−Order
Modulator
Programmable
Digital Filter
Buffer
Control
SYNC/PDWN
AIN4
AIN5
AIN6
AIN7
DRDY
SCLK
DIN
Test and Measurement
General
Purpose
Digital I/O
Serial
Interface
AINCOM
DOUT
CS
AGND
D3 D2
D1 D0/CLKOUT
DGND
ADS1256
Only
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢝꢞ ꢟ ꢕꢠ ꢗ ꢡꢢ ꢟꢇ ꢕ ꢐꢡꢐ ꢈꢑ ꢣꢅ ꢂ ꢤꢒ ꢏꢈꢅꢑ ꢈꢉ ꢥꢦ ꢂ ꢂ ꢁꢑꢏ ꢒꢉ ꢅꢣ ꢧꢦꢨ ꢓꢈꢥ ꢒꢏꢈ ꢅꢑ ꢩꢒ ꢏꢁꢪ ꢝꢂ ꢅꢩꢦ ꢥꢏꢉ
ꢥ ꢅꢑ ꢣꢅꢂ ꢤ ꢏꢅ ꢉ ꢧꢁ ꢥ ꢈ ꢣꢈ ꢥ ꢒ ꢏꢈ ꢅꢑꢉ ꢧ ꢁꢂ ꢏꢫꢁ ꢏꢁ ꢂ ꢤꢉ ꢅꢣ ꢡꢁꢬ ꢒꢉ ꢢꢑꢉ ꢏꢂ ꢦꢤ ꢁꢑꢏ ꢉ ꢉꢏ ꢒꢑꢩ ꢒꢂ ꢩ ꢆ ꢒꢂ ꢂ ꢒ ꢑꢏꢃꢪ
ꢝꢂ ꢅ ꢩꢦꢥ ꢏ ꢈꢅ ꢑ ꢧꢂ ꢅ ꢥ ꢁ ꢉ ꢉ ꢈꢑ ꢔ ꢩꢅ ꢁ ꢉ ꢑꢅꢏ ꢑꢁ ꢥꢁ ꢉꢉ ꢒꢂ ꢈꢓ ꢃ ꢈꢑꢥ ꢓꢦꢩ ꢁ ꢏꢁ ꢉꢏꢈ ꢑꢔ ꢅꢣ ꢒꢓ ꢓ ꢧꢒ ꢂ ꢒꢤ ꢁꢏꢁ ꢂ ꢉꢪ
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
(1)
ORDERING INFORMATION
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TRANSPORT MEDIA,
QUANTITY
PRODUCT
ADS1255
ADS1256
PACKAGE-LEAD
ORDERING NUMBER
ADS1255IDBT
ADS1255IDBR
ADS1256IDBT
ADS1256IDBR
Tape and Reel, 250
Tape and Reel, 1000
Tape and Reel, 250
Tape and Reel, 1000
SSOP-20
DB
DB
ADS1255IDB
ADS1256IDB
SSOP-28
(1)
For the most current package and ordering information, refer to our web site at www.ti.com.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
ADS1255, ADS1256 UNIT
AVDD to AGND
DVDD to DGND
AGND to DGND
−0.3 to +6
−0.3 to +3.6
V
V
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
−0.3 to +0.3
V
100, Momentary
10, Continuous
−0.3 to AVDD + 0.3
mA
mA
V
Input Current
Analog inputs to AGND
DIN, SCLK, CS, RESET,
SYNC/PDWN,
XTAL1/CLKIN to DGND
−0.3 to +6
V
Digital
inputs
D0/CLKOUT, D1, D2, D3
to DGND
−0.3 to DVDD + 0.3
V
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10s)
+150
−40 to +105
−60 to +150
+300
°C
°C
°C
°C
(1)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional
operationof the device at these or any other conditions beyond
those specified is not implied.
2
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, f
= 7.68MHz, PGA = 1, and V
= +2.5V, unless otherwise noted.
CLKIN
REF
TYP
PARAMETER
Analog Inputs
Full-scale input voltage (AIN − AIN )
TEST CONDITIONS
MIN
MAX
UNIT
2V
/PGA
REF
V
V
V
P
N
Buffer off
Buffer on
AGND − 0.1
AVDD + 0.1
AVDD − 2.0
64
Absolute input voltage
(AIN0-7, AINCOM to AGND)
AGND
1
Programmable gain amplifier
Buffer off, PGA = 1, 2, 4, 8, 16
150/PGA
kΩ
kΩ
MΩ
µA
µA
µA
Buffer off, PGA = 32, 64
(1)
4.7
80
0.5
2
Differential input impedance
Sensor detect current sources
Buffer on, f
≤ 50Hz
DATA
SDCS[1:0] = 01
SDCS[1:0] = 10
SDCS[1:0] = 11
10
System Performance
Resolution
24
24
Bit
Bit
No missing codes
All data rates and PGA settings
= 7.68MHz
(2)
SPS
Data rate (f
)
f
2.5
30,000
0.0010
DATA
CLKIN
(3)
Differential input, PGA = 1
Differential input, PGA = 64
After calibration
0.0003
0.0007
%FSR
Integral nonlinearity
Offset error
%FSR
On the level of the noise
PGA = 1
100
nV/°C
nV/°C
%
Offset drift
PGA = 64
4
After calibration, PGA = 1, Buffer on
After calibration, PGA = 64, Buffer on
PGA = 1
0.005
Gain error
Gain drift
0.03
%
0.8
ppm/°C
ppm/°C
dB
PGA = 64
0.8
(4)
(5)
= 30kSPS
Common-mode rejection
Noise
f
= 60Hz, f
DATA
95
60
110
CM
See Noise Performance Tables
AVDD power-supply rejection
DVDD power-supply rejection
Voltage Reference Inputs
5% ∆ in AVDD
10% ∆ in DVDD
70
dB
dB
100
Reference input voltage (V
)
V
≡ VREFP − VREFN
0.5
2.5
2.6
V
V
REF
REF
Buffer off
Buffer on
Buffer off
Buffer on
AGND − 0.1
AGND
VREFP − 0.5
VREFP − 0.5
AVDD + 0.1
AVDD − 2.0
Negative reference input (VREFN)
Positive reference input (VREFP)
(6)
V
VREFN + 0.5
VREFN + 0.5
V
(6)
V
Voltage reference impedance
f
= 7.68MHz
18.5
kΩ
CLKIN
Digital Input/Output
DIN, SCLK, XTAL1/CLKIN,
SYNC/PDWN, CS, RESET
0.8 DVDD
5.25
V
V
IH
D0/CLKOUT, D1, D2, D3
0.8 DVDD
DGND
DVDD
V
V
V
V
V
0.2 DVDD
IL
I
I
= 5mA
= 5mA
0.8 DVDD
V
OH
OL
OH
OL
0.2 DVDD
V
Input hysteresis
Input leakage
0.5
V
0 < V
DIGITAL INPUT
External crystal between XTAL1 and
XTAL2
< DVDD
10
10
10
µA
2
7.68
7.68
MHz
MHz
Master clock rate
External oscillator driving CLKIN
0.1
3
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS (continued)
All specifications at −40°C to +85°C, AVDD = +5V, DVDD = +1.8V, f
= 7.68MHz, PGA = 1, and V
= +2.5V, unless otherwise noted.
CLKIN
REF
TYP
PARAMETER
Power-Supply
TEST CONDITIONS
MIN
MAX
UNIT
AVDD
DVDD
4.75
1.8
5.25
3.6
2
V
V
Power-down mode
Standby mode
µA
µA
mA
mA
mA
mA
µA
20
7
Normal mode, PGA = 1, Buffer off
Normal mode, PGA = 64, Buffer off
Normal mode, PGA = 1, Buffer on
Normal mode, PGA = 64, Buffer on
Power-down mode
10
22
19
50
2
AVDD current
16
13
36
Standby mode, CLKOUT off,
DVDD = 3.3V
95
µA
DVDD current
Normal mode, CLKOUT off,
DVDD = 3.3V
0.9
2
mA
Normal mode, PGA = 1, Buffer off,
DVDD = 3.3V
38
57
mW
mW
Power dissipation
Standby mode, DVDD = 3.3V
0.4
Temperature Range
Specified
−40
−40
−60
+85
+105
+150
°C
°C
°C
Operating
Storage
(1)
(2)
(3)
(4)
(5)
See text for more information on input impedance.
SPS = samples per second.
FSR = full-scale range = 4V
/PGA.
REF
is the frequency of the common-mode input signal.
f
CM
Placing a notch of the digital filter at 60Hz (setting f
common-moderejection of this frequency.
= 60SPS, 30SPS, 15SPS, 10SPS, 5SPS, or 2.5SPS) will further improve the
DATA
(6)
The reference input range with Buffer on is restricted only if self-calibration or gain self-calibration is to be used. If using system calibration or
writing calibration values directly to the registers, the entire Buffer off range can be used.
4
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PIN ASSIGNMENTS
SSOP PACKAGE
(TOP VIEW)
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
D3
D2
1
2
3
4
5
6
28
27
26
25
24
AVDD
AGND
1
2
3
4
20 D1
D1
D0/CLKOUT
19
18
17
D0/CLKOUT
SCLK
VREFN
SCLK
DIN
VREFP
AINCOM
AIN0
23 DIN
AIN1
16 DOUT
5
6
DOUT
7
8
9
22
21
20
ADS1255
ADS1256
15
AIN2
DRDY
CS
DRDY
AIN1
7
8
9
AIN3
14 CS
XTAL1/CLKIN
SYNC, PDWN
RESET
13
AIN4
AIN5
AIN6
10
19 XTAL1/CLKIN
XTAL2
18
12 XTAL2
11
12
DVDD 10
11
DGND
17 DGND
16 DVDD
AIN7 13
SYNC, PDWN
RESET
15
14
Terminal Functions
TERMINAL NO.
ANALOG/DIGITAL
INPUT/OUTPUT
NAME
AVDD
AGND
VREFN
VREFP
AINCOM
AIN0
ADS1255 ADS1256
DESCRIPTION
1
2
1
2
Analog
Analog power supply
Analog ground
Analog
3
3
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
Negative reference input
Positive reference input
Analog input common
Analog input 0
4
4
5
5
6
6
AIN1
7
7
Analog input 1
AIN2
—
—
—
—
—
—
8
8
Analog input 2
AIN3
9
Analog input 3
AIN4
10
11
12
13
14
15
16
17
18
19
20
Analog input 4
AIN5
Analog input 5
AIN6
Analog input 6
AIN7
Analog input 7
(1)(2)
SYNC/PDWN
RESET
Digital input
Digital input
: active low Synchronization / power down input
: active low Reset input
Digital power supply
Digital ground
(1)(2)
9
DVDD
10
11
12
13
14
Digital
Digital
DGND
(3)
Digital
XTAL2
Crystal oscillator connection
Crystal oscillator connection / external clock input
(2)
XTAL1/CLKIN
CS
Digital/Digital input
(1)(2)
Digital input : active low Chip select
DRDY
DOUT
DIN
15
16
17
18
19
20
—
—
21
22
23
24
25
26
27
28
Digital output: active low
Digital output
Data ready output
Serial data output
Serial data input
Serial clock input
Digital I/O 0 / clock output
Digital I/O 1
(1)(2)
(1)(2)
(4)
Digital input
Digital input
Digital IO
Digital IO
Digital IO
Digital IO
SCLK
D0/CLKOUT
D1
(4)
(4)
D2
Digital I/O 2
(4)
D3
Digital I/O 3
(1)
(2)
(3)
(4)
Schmitt-Trigger digital input.
5V tolerant digital input.
Leave disconnected if external clock input is applied to XTAL1/CLKIN.
Schmitt-Trigger digital input when the digital I/O is configured as an input.
5
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
CS
t3
t2H
t10
t1
SCLK
DIN
t4
t5
t6
t2L
t11
t7
t8
t9
DOUT
Figure 1. Serial Interface Timing
TIMING CHARACTERISTICS FOR FIGURE 1
SYMBOL DESCRIPTION
MIN
MAX
UNIT
(1)
4
τ
CLKIN
t
1
SCLK period
(2)
10
9
τ
DATA
ns
200
t
SCLK pulse width: high
2H
τ
DATA
t
200
0
ns
SCLK pulse width: low
2L
(3)
t
ns
ns
ns
CS low to first SCLK: setup time
3
t
50
50
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
4
t
5
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands
t
50
τ
τ
6
CLKIN
(4)
t
t
50
10
ns
ns
SCLK rising edge to valid new DOUT: propagation delay
7
0
6
SCLK rising edge to DOUT invalid: hold time
8
Last SCLK falling edge to DOUT high impedance
NOTE: DOUT goes high impedance immediately when CS goes high
t
9
CLKIN
ns
t
10
0
4
CS low after final SCLK falling edge
RREG, WREG, RDATA
τ
τ
CLKIN
24
RDATAC, RESET, SYNC
CLKIN
Final SCLK falling edge of command to first SCLK
t
11
RDATAC, STANDBY, SELFOCAL, SY-
SOCAL, SELFGCAL,
rising edge of next command.
Wait for DRDY to go low
SYSGCAL, SELFCAL
(1)
(2)
(3)
(4)
τ
= master clock period = 1/f .
CLKIN
= output data period 1/f .
DATA
CLKIN
τ
DATA
CS can be tied low.
DOUT load = 20pF 100kΩ to DGND.
6
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
t13
t13
SCLK
t12
t14
t15
Figure 2. SCLK Reset Timing
TIMING CHARACTERISTICS FOR FIGURE 2
SYMBOL DESCRIPTION
MIN
MAX
UNIT
(1)
t
12
t
13
t
14
t
15
300
500
τ
SCLK reset pattern, first high pulse
SCLK reset pattern, low pulse
CLKIN
5
550
τ
CLKIN
750
τ
SCLK reset pattern, second high pulse
SCLK reset pattern, third high pulse
CLKIN
1050
1250
τ
CLKIN
(1)
τ
= master clock period = 1/f .
CLKIN
CLKIN
t16
RESET, SYNC/PDWN
Figure 3. RESET and SYNC/PDWN Timing
TIMING CHARACTERISTICS FOR FIGURE 3
SYMBOL DESCRIPTION
MIN
MAX
UNIT
(1)
τ
CLKIN
t
16
4
RESET, SYNC/PDWN, pulse width
(1)
τ
= master clock period = 1/f .
CLKIN
CLKIN
t17
DRDY
Figure 4. DRDY Update Timing
TIMING CHARACTERISTICS FOR FIGURE 4
SYMBOL DESCRIPTION
MIN
MAX
UNIT
(1)
τ
CLKIN
t
17
16
Conversion data invalid while being updated (DRDY shown with no data retrieval)
(1)
τ
= master clock period = 1/f .
CLKIN
CLKIN
7
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
T
A
= +25°C, AVDD = 5V, DVDD = 1.8V, f
CLKIN
= 7.68MHz, PGA = 1, and V = 2.5V, unless otherwise noted.
REF
OFFSET DRIFT HISTOGRAM
90 Units from 3 Production Lots
OFFSET DRIFT HISTOGRAM
25
20
15
10
5
30
25
20
15
10
5
PGA = 1
PGA = 1
PGA = 1
PGA = 64
PGA = 64
PGA = 64
90 Units from 3 Production Lots
0
0
_
Offset Drift (nV/ C)
_
Offset Drift (nV/ C)
GAIN ERROR HISTOGRAM
GAIN ERROR HISTOGRAM
90 Units from 3 Production Lots
30
25
20
15
10
5
25
20
15
10
5
90 Units from 3 Production Lots
0
0
Gain Error (%)
Gain Error (%)
GAIN DRIFT HISTOGRAM
GAIN DRIFT HISTOGRAM
25
20
15
10
5
25
20
15
10
5
90 Units from 3 Production Lots
90 Units from 3 Production Lots
0
0
_
_
Gain Drift (ppm/ C)
Gain Drift (ppm/ C)
8
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (continued)
T
A
= +25°C, AVDD = 5V, DVDD = 1.8V, f
CLKIN
= 7.68MHz, PGA = 1, and V = 2.5V, unless otherwise noted.
REF
NOISE HISTOGRAM
NOISE HISTOGRAM
100
80
60
40
20
0
25
20
15
10
5
PGA = 1
Data Rate = 2.5SPS
Buffer = Off
256 Readings
Buffer = Off
256 Readings
PGA = 64
Data Rate = 2.5SPS
0
−
−
−
−
−
1
5
4
3
2
0
1
2
3
4
5
Output Code (LSB)
Output Code (LSB)
NOISE HISTOGRAM
NOISE HISTOGRAM
25
20
15
10
5
25
20
15
10
5
Buffer = Off
4096 Readings
PGA = 1
Data Rate = 1kSPS
PGA = 64
Data Rate = 1kSPS
Buffer = Off
4096 Readings
0
0
Output Code (LSB)
Output Code (LSB)
NOISE HISTOGRAM
NOISE HISTOGRAM
25
20
15
10
5
25
20
15
10
5
PGA = 64
Data Rate = 30kSPS
Buffer = Off
4096 Readings
PGA = 1
Data Rate = 30kSPS
Buffer = Off
4096 Readings
0
0
Output Code (LSB)
Output Code (LSB)
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TYPICAL CHARACTERISTICS (continued)
T
A
= +25°C, AVDD = 5V, DVDD = 1.8V, f
CLKIN
= 7.68MHz, PGA = 1, and V = 2.5V, unless otherwise noted.
REF
EFFECTIVE NUMBER OF BITS
vs INPUT VOLTAGE
EFFECTIVE NUMBER OF BITS
vs TEMPERATURE
23
22
21
20
19
18
23
22
21
20
19
18
PGA = 1
PGA = 1
Data Rate = 1kSPS
Data Rate = 1kSPS
Data Rate = 30kSPS
Data Rate = 30kSPS
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Input Voltage, VIN (V)
−
−
−
10
50
30
10
30
50
70
90
110
_
Temperature ( C)
INTEGRAL NONLINEARITY vs INPUT SIGNAL
INTEGRAL NONLINEARITY vs PGA
0.0006
0.0004
0.0002
0
0.0009
0.0008
0.0007
0.0006
0.0005
0.0004
0.0003
0.0002
0.0001
0
−
_
40 C
_
+125 C
Buffer Off
_
_
+85 C
+25 C
Buffer On
−
−
−
0.0002
0.0004
0.0006
PGA = 1
−
−
−
−
−
1
5
4
3
2
0
1
2
3
4
5
1
2
4
8
16
32
64
Input Voltage, VIN (V)
PGA Setting
ANALOG SUPPLY CURRENT vs TEMPERATURE
PGA = 64, Buffer On
ANALOG SUPPLY CURRENT vs PGA
Buffer On
50
45
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
Buffer Off
PGA = 64, Buffer Off
PGA = 1, Buffer On
PGA = 1, Buffer Off
0
0
−
−
−
10
50
30
10
30
50
70
90
110
1
2
4
8
16
32
64
_
Temperature ( C)
PGA Setting
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The modulator measures the amplified differential input
signal, VIN = (AINP – AINN), against the differential
reference, VREF = (VREFP − VREFN). The differential
reference is scaled internally by a factor of two so that the
full-scale input range is 2VREF (for PGA = 1).
OVERVIEW
The ADS1255 and ADS1256 are very low-noise A/D
converters. The ADS1255 supports one differential or two
single-ended inputs and has two general-purpose digital
I/Os. The ADS1256 supports four differential or eight
single-ended inputs and has four general-purpose digital
I/Os. Otherwise, the two units are identical and are
referred to together in this data sheet as the ADS1255/6.
The digital filter receives the modulator signal and
provides a low-noise digital output. The data rate of the
filter is programmable from 2.5SPS to 30kSPS and allows
tradeoffs between resolution and speed.
Figure 5 shows a block diagram of the ADS1256. The
input multiplexer selects which input pins are connected to
the A/D converter. Selectable current sources within the
input multiplexer can check for open- or short-circuit
conditions on the external sensor. A selectable onboard
input buffer greatly reduces the input circuitry loading by
providing up to 80MΩ of impedance. A low-noise PGA
provides a gain of 1, 2, 4, 8, 16, 32, or 64. The ADS1255/6
converter is comprised of a 4th-order, delta-sigma
modulator followed by a programmable digital filter.
Communication is done over an SPI-compatible serial
interface with a set of simple commands providing control of
the ADS1255/6. Onboard registers store the various settings
for the input multiplexer, sensor detect current sources, input
buffer enable, PGA setting, data rate, etc. Either an external
crystal or clock oscillator can be used to provide the clock
source. General-purpose digital I/Os provide static read/write
control of up to four pins. One of the pins can also be used
to supply a programmable clock output.
VREFP VREFN
Σ
A/D
Converter
VREF
XTAL1/CLKIN
XTAL2
Clock
Generator
AIN0
AIN1
2
2VREF
AIN2
Input
AIN3
AIN4
AIN5
AIN6
AINP
AINN
Multiplexer
and
Sensor
Detect
•
VIN PGA
RESET
4th−Order
Modulator
PGA
1:64
Programmable
Digital Filter
Buffer
Σ
Control
SYNC/PDWN
AIN7
DRDY
SCLK
DIN
AINCOM
SPI
Serial
Interface
General
Purpose
Digital I/O
DOUT
CS
D3 D2
D1 D0/CLKOUT
ADS1256
Only
Figure 5. Block Diagram
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Table 2. Effective Number of Bits (ENOB, rms)
with Buffer On
NOISE PERFORMANCE
The ADS1255/6 offer outstanding noise performance that
can be optimized by adjusting the data rate or PGA setting.
As the averaging is increased by reducing the data rate,
the noise drops correspondingly. The PGA reduces the
input-referred noise when measuring lower level signals.
Table 1 through Table 6 summarize the typical noise
performance with the inputs shorted externally. In all six
tables, the following conditions apply: T = +25°C,
DATA
RATE
(SPS)
PGA
8
1
2
4
16
32
64
2.5
5
25.3
25.0
24.8
24.6
24.3
24.2
23.9
23.8
23.4
22.3
21.7
21.2
20.8
20.4
20.1
19.8
24.9
24.8
24.5
24.2
24.0
23.8
23.6
23.4
23.0
21.9
21.3
20.9
20.5
20.1
19.7
19.5
24.9
24.5
24.1
23.8
23.4
23.3
23.0
22.9
22.5
21.5
20.8
20.4
20.0
19.6
19.3
19.1
24.4
24.0
23.5
23.2
23.0
22.8
22.5
22.4
22.0
20.9
20.2
19.7
19.4
19.0
18.7
18.5
23.8
23.3
22.9
22.5
22.2
22.1
21.8
21.7
21.4
20.3
19.8
19.3
19.0
18.5
18.2
18.0
23.0
22.7
22.3
21.8
21.5
21.5
21.1
21.0
20.8
19.6
19.2
18.8
18.4
17.9
17.7
17.4
22.2
21.8
21.3
21.0
20.7
20.5
20.3
20.2
19.8
18.7
18.3
17.9
17.4
17.0
16.7
16.5
10
15
AVDD = 5V, DVDD = 1.8V, VREF = 2.5V, and fCLKIN
=
25
7.68MHz. Table 1 to Table 3 reflect the device input buffer
enabled. Table 1 shows the rms value of the input-referred
noise in volts. Table 2 shows the effective number of bits
of resolution (ENOB), using the noise data from Table 1.
ENOB is defined as:
30
50
60
100
500
1000
2000
3750
7500
15,000
30,000
ǒ
Ǔ
ln FSRńRMS Noise
ENOB +
( )
ln 2
where FSR is the full-scale range. Table 3 shows the
noise-free bits of resolution. It is calculated with the same
formula as ENOB except the peak-to-peak noise value is
used instead of rms noise. Table 4 through Table 6 show
the same noise data, but with the input buffer disabled.
Table 3. Noise-Free Resolution (bits)
with Buffer On
DATA
RATE
(SPS)
PGA
Table 1. Input Referred Noise (µV, rms)
with Buffer On
1
2
4
8
16
32
64
DATA
RATE
(SPS)
PGA
8
2.5
5
23.0
22.3
22.3
22.0
21.7
21.8
21.3
21.3
20.9
20.1
19.0
18.5
18.1
17.7
17.3
17.1
22.6
22.4
22.0
21.7
21.4
21.3
21.1
20.9
20.7
19.6
18.6
18.1
17.8
17.3
17.0
16.7
22.1
21.9
21.6
21.3
21.1
20.8
20.4
20.5
20.2
19.1
18.1
17.8
17.3
16.9
16.5
16.4
21.7
21.3
21.0
20.7
20.5
20.4
19.9
19.8
19.6
18.6
17.5
17.0
16.6
16.2
15.9
15.9
21.3
20.7
20.4
20.1
19.7
19.8
19.4
19.3
19.1
18.0
17.2
16.6
16.2
15.8
15.5
15.4
20.8
20.3
19.9
19.3
19.2
19.0
18.8
18.8
18.5
17.3
16.5
16.1
15.7
15.3
14.9
14.6
19.7
19.3
18.9
18.7
18.5
18.1
17.9
17.8
17.4
16.3
15.6
15.3
14.7
14.4
13.9
13.8
1
2
4
16
32
64
10
2.5
5
0.247 0.156 0.080 0.056 0.043 0.037 0.033
0.301 0.175 0.102 0.076 0.061 0.045 0.044
0.339 0.214 0.138 0.106 0.082 0.061 0.061
0.401 0.264 0.169 0.126 0.107 0.085 0.073
0.494 0.305 0.224 0.149 0.134 0.102 0.093
0.533 0.335 0.245 0.176 0.138 0.104 0.106
0.629 0.393 0.292 0.216 0.168 0.136 0.122
0.692 0.438 0.321 0.233 0.184 0.146 0.131
0.875 0.589 0.409 0.305 0.229 0.170 0.169
1.946 1.250 0.630 0.648 0.497 0.390 0.367
2.931 1.891 1.325 1.070 0.689 0.512 0.486
4.173 2.589 1.827 1.492 0.943 0.692 0.654
5.394 3.460 2.376 1.865 1.224 0.912 0.906
7.249 4.593 3.149 2.436 1.691 1.234 1.187
15
25
10
30
15
50
25
60
30
100
500
1000
2000
3750
7500
15,000
30,000
50
60
100
500
1000
2000
3750
7500
15,000 9.074 5.921 3.961 2.984 2.125 1.517 1.515
30,000 10.728 6.705 4.446 3.280 2.416 1.785 1.742
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Table 4. Input Referred Noise (µV, rms)
Table 6. Noise-Free Resolution (bits)
with Buffer Off
with Buffer Off
DATA
RATE
(SPS)
DATA
RATE
(SPS)
PGA
8
PGA
1
2
4
16
32
64
1
2
4
8
16
32
64
2.5
5
0.247 0.149 0.097 0.058 0.036 0.031 0.027
0.275 0.176 0.109 0.070 0.046 0.039 0.038
0.338 0.201 0.129 0.084 0.063 0.048 0.047
0.401 0.221 0.150 0.109 0.070 0.063 0.057
0.485 0.279 0.177 0.136 0.093 0.076 0.076
0.559 0.315 0.202 0.142 0.107 0.093 0.082
0.644 0.390 0.238 0.187 0.129 0.108 0.103
0.688 0.417 0.281 0.204 0.134 0.109 0.111
0.815 0.530 0.360 0.233 0.169 0.123 0.122
1.957 1.148 0.772 0.531 0.375 0.276 0.259
2.803 1.797 1.191 0.940 0.518 0.392 0.365
4.025 2.444 1.615 1.310 0.700 0.526 0.461
5.413 3.250 2.061 1.578 0.914 0.693 0.625
7.017 4.143 2.722 1.998 1.241 0.914 0.857
2.5
5
23.0
22.4
22.3
22.0
21.8
21.6
21.3
21.2
21.1
20.0
19.0
18.5
18.1
17.7
17.4
17.1
22.4
22.1
22.1
21.8
21.7
21.4
21.3
21.0
20.5
19.7
18.7
18.3
17.8
17.6
17.1
17.0
22.0
21.9
21.7
21.4
21.1
21.1
20.7
20.6
20.3
19.3
18.4
17.9
17.5
17.0
16.8
16.6
21.9
21.5
21.5
20.8
20.7
20.4
20.1
20.1
19.9
18.9
17.7
17.4
17.0
16.6
16.3
16.0
21.3
21.2
20.8
20.6
20.3
20.0
19.8
19.8
19.5
18.3
17.5
17.0
16.7
16.2
15.9
15.6
21.1
20.4
20.3
19.9
19.5
16.4
19.1
19.1
19.0
17.8
16.9
16.4
16.1
15.7
15.3
15.0
20.0
19.4
19.2
19.0
18.6
18.5
18.2
18.1
17.9
16.9
15.9
15.6
15.2
14.8
14.4
14.4
10
10
15
15
25
25
30
30
50
50
60
60
100
500
1000
2000
3750
7500
100
500
1000
2000
3750
7500
15,000
30,000
15,000 8.862 5.432 3.378 2.411 1.569 1.149 1.051
30,000 10.341 6.137 3.873 2.775 1.805 1.313 1.211
Table 5. Effective Number of Bits (ENOB, rms)
with Buffer Off
DATA
RATE
(SPS)
PGA
8
1
2
4
16
32
64
2.5
5
25.3
25.1
24.8
24.6
24.3
24.1
23.9
23.8
23.5
22.3
21.8
21.2
20.8
20.4
20.1
19.9
25.0
24.8
24.6
24.4
24.1
23.9
23.6
23.5
23.2
22.1
21.4
21.0
20.6
20.2
19.8
19.6
24.6
24.5
24.2
24.0
23.8
23.6
23.3
23.1
22.7
21.6
21.0
20.6
20.2
19.8
19.5
19.3
24.4
24.1
23.8
23.4
23.1
23.1
22.7
22.5
22.4
21.2
20.3
19.9
19.6
19.3
19.0
18.8
24.0
23.7
23.2
23.1
22.7
22.5
22.2
22.1
21.8
20.7
20.2
19.8
19.4
18.9
18.6
18.4
23.2
22.9
22.6
22.2
22.0
21.7
21.5
21.5
21.3
20.1
19.6
19.2
18.8
18.4
18.1
17.9
22.5
22.0
21.7
21.4
21.0
20.9
20.5
20.4
20.3
19.2
18.7
18.4
17.9
17.5
17.2
17.0
10
15
25
30
50
60
100
500
1000
2000
3750
7500
15,000
30,000
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However, for optimum analog performance, the following
recommendations are made:
INPUT MULTIPLEXER
Figure 6 shows a simplified diagram of the input
multiplexer. This flexible block allows any analog input pin
to be connected to either of the converter differential
inputs. That is, any pin can be selected as the positive
input (AINP); likewise, any pin can be selected as the
negative input (AINN). The pin selection is controlled by
the multiplexer register.
1. For differential measurements use AIN0 through
AIN7, preferably adjacent inputs. For example, use
AIN0 and AIN1. Do not use AINCOM.
2. For single-ended measurements use AINCOM as
common input and AIN0 through AIN7 as
single-ended inputs.
3. Leave any unused analog inputs floating. This
minimizes the input leakage current.
ESD diodes protect the analog inputs. To keep these
diodes from turning on, make sure the voltages on the
input pins do not go below AGND by more than 100mV,
and likewise do not exceed AVDD by more than 100mV:
−100mV < (AIN0 − 7 and AINCOM) < AVDD + 100mV.
The ADS1256 offers nine analog inputs, which can be
configured as four independent differential inputs, eight
single-ended inputs, or a combination of differential and
single-ended inputs.
The ADS1255 offers three analog inputs, which can be
configured as one differential input or two single-ended
inputs. When using the ADS1255 and programming the
input, make sure to select only the available inputs when
programming the input multiplexer register.
When using ADS1255/6 for single-ended measurements,
it is important to note that common input AINCOM does not
need to be tied to ground. For example, AINCOM can be
tied to a midpoint reference such as +2.5V or even AVDD.
In general, there are no restrictions on input pin selection.
AVDD
AIN0
AVDD
AIN1
AVDD
AVDD
Sensor Detect
Current
Source
AIN2
AVDD
AIN3
AVDD
AINP
Input
Buffer
AINN
AIN4
AVDD
AIN5
AVDD
Sensor Detect
Current
AIN6
Source
AVDD
AGND
AIN7
ADS1256 Only
AINCOM
Input Multiplexer
AVDD AGND
Figure 6. Simplified Diagram of the Input Multiplexer
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OPEN/SHORT SENSOR DETECTION
ANALOG INPUT BUFFER
The sensor detect current sources (SDCS) provide a
means to verify the integrity of the external sensor
connected to the ADS1255/6. When enabled, the SDCS
supply a current (ISDC) of approximately 0.5µA, 2µA, or
10µA to the sensor through the input multiplexer. The
SDCS bits in the ADCON register enable the SDCS and
To dramatically increase the input impedance presented
by the ADS1255/6, the low-drift chopper-stabilized buffer
can be enabled via the BUFEN bit in the STATUS register.
The input impedance with the buffer enabled can be
modeled by a resistor, as shown in Figure 8. Table 7 lists
the values of ZEFF for the different data rate settings. The
input impedance scales inversely with the frequency of
CLKIN. For example, if fCLKIN is reduced by half to
3.84MHz, ZEFF for a data rate of 50SPS will double from
80MΩ to 160MΩ.
set the value of ISDC
.
When the SDCS are enabled, the ADS1255/6
automatically turns on the analog input buffer regardless
of the BUFEN bit setting. This is done to prevent the input
circuitry from loading the SDCS. AINP must stay below 3V
to be within the absolute input range of the buffer. To
ensure this condition is met, a 3V clamp will start sinking
current from AINP to AGND if AINP exceeds 3V. Note that
this clamp is activated only when the SDCS are enabled.
AIN0
AIN1
AIN2
Figure 7 shows a simplified diagram of ADS1255/6 input
structure with the external sensor modeled as resistance
RSENS between two input pins. When the SDCS are
enabled, they source ISDC to the input pin connected to
AINP and sink ISDC from the input pin connected to AINN.
The two 25Ω series resistors, RMUX, model the
ADS1255/6 internal resistances. The signal measured
with the SDCS enabled equals the total IR drop:
ISDC × (2RMUX + RSENS). Note that when the sensor is a
direct short (that is, RSENS = 0), there will still be a small
signal measured by the ADS1255/6 when the SDCS are
AIN
P
AIN3
AIN4
Input
Z
EFF
Multiplexer
AIN5
AIN
N
AIN6
AIN7
AINCOM
Figure 8. Effective Impedance with Buffer On
Table 7. Input Impedance with Buffer On
enabled: ISDC × 2RMUX
.
DATA RATE
(SPS)
Z
EFF
AVDD
(MΩ)
10
10
10
10
10
20
40
40
40
80
30,000
15,000
7,500
3,750
2,000
1,000
500
Sensor Detect
Current Source
RMUX
Ω
25
AINP
3V
Clamp
Input
Buffer
RSENS
100
RMUX
60
Ω
25
≤ 50
AINN
NOTE: f
CLKIN
= 7.68MHz.
Sensor Detect
Current Source
With the buffer enabled, the voltage on the analog inputs
with respect to ground (listed in the Electrical
Characteristics as Absolute Input Voltage) must remain
between AGND and AVDD − 2.0V. Exceeding this range
reduces performance, in particular the linearity of the
ADS1255/6. This same voltage range, AGND to
AVDD − 2.0V, applies to the reference inputs when
performing a self gain calibration with the buffer enabled.
NOTE: Arrows indicate switch positions when the SDCS are enabled.
Figure 7. Sensor Detect Circuitry
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repeats with a period of τSAMPLE. This time is a function of
the PGA setting as shown in Table 9 along with the values
of the capacitor CA1 = CA2 = CA and CB.
PROGRAMMABLE GAIN AMPLIFIER (PGA)
The ADS1255/6 is a very high resolution converter. To
further complement its performance, the low-noise PGA
provides even more resolution when measuring smaller
input signals. For the best resolution, set the PGA to the
highest possible setting. This will depend on the largest
input signal to be measured. The ADS1255/6 full-scale
input voltage equals 2VREF/PGA. Table 8 shows the
full-scale input voltage for the different PGA settings for
VREF = 2.5V. For example, if the largest signal to be
measured is 1.0V, the optimum PGA setting would be 4,
which gives a full-scale input voltage of 1.25V. Higher
PGAs cannot be used since they cannot handle a 1.0V
input signal.
AVDD/2
AIN0
AIN1
AIN2
AIN3
S2
C
A1
AIN
P
S1
S1
Input
C
AIN4
AIN5
B
Multiplexer
AIN
N
AIN6
C
S2
AIN7
A2
Table 8. Full-Scale Input Voltage vs
PGA Setting
AINCOM
AVDD/2
PGA SETTING FULL-SCALE INPUT VOLTAGE (V
REF
= 2.5V)
1
2
5V
2.5V
Figure 9. Simplified Input Structure
with Buffer Off
4
1.25V
8
0.625V
312.5mV
156.25mV
78.125mV
16
32
64
τ SAMPLE
ON
S1
S2
OFF
ON
The PGA is controlled by the ADCON register.
Recalibrating the A/D converter after changing the PGA
setting is recommended. The time required for
self-calibration is dependent on the PGA setting. See the
Calibration section for more details. The analog current
and input impedance (when the buffer is disabled) vary as
a function of PGA setting.
OFF
Figure 10. S1 and S2 Switch Timing for Figure 9
Table 9. Input Sampling Time, τ
, and
SAMPLE
C and C vs PGA
A
B
MODULATOR INPUT CIRCUITRY
PGA
The ADS1255/6 modulator measures the input signal
using internal capacitors that are continuously charged
and discharged. Figure 9 shows a simplified schematic of
the ADS1255/6 input circuitry with the input buffer
disabled. Figure 10 shows the on/off timings of the
switches of Figure 9. S1 switches close during the input
sampling phase. With S1 closed, CA1 charges to AINP,CA2
charges to AINN, and CB charges to (AINP – AINN). For the
discharge phase, S1 opens first and then S2 closes. CA1
and CA2 discharge to approximately AVDD/2 and CB
discharges to 0V. This two-phase sample/discharge cycle
(1)
SETTING
τ
C
C
B
SAMPLE
A
1
2
f
f
f
f
f
f
f
/4 (521ns)
/4 (521ns)
/4 (521ns)
/4 (521ns)
/4 (521ns)
/2 (260ns)
/2 (260ns)
2.1pF
4.2pF
8.3pF
17pF
33pF
33pF
33pF
2.4pF
4.9pF
9.7pF
19pF
39pF
39pF
39pF
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
CLKIN
4
8
16
32
64
(1)
τ
for f = 7.68MHz.
CLKIN
SAMPLE
16
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The charging of the input capacitors draws a transient
current from the sensor driving the ADS1255/6 inputs. The
average value of this current can be used to calculate an
VREFP
VREFN
effective impedance ZEFF where ZEFF = VIN / IAVERAGE
Figure 11 shows the input circuitry with the capacitors and
switches of Figure 9 replaced by their effective
impedances. These impedances scale inversely with the
CLKIN frequency. For example, if fCLKIN is reduced by a
factor of two, the impedances will double. They also
change with the PGA setting. Table 10 lists the effective
impedances with the buffer off for fCLKIN = 7.68MHz.
.
AVDD
AVDD
ESD
Protection
Self Gain
Calibration
(1)
Ω
ZEFF = 18.5k
AINP AINN
AVDD/2
AIN0
AIN1
τ
τ
τ
ZeffA
ZeffB
ZeffA
=
=
=
SAMPLE/CA
SAMPLE/CB
SAMPLE/CA
AIN2
AIN3
AINP
AINN
(1) fCLKIN = 7.68MHz
Input
Multiplexer
AIN4
AIN5
AIN6
AIN7
Figure 12. Simplified Reference Input Circuitry
AINCOM
AVDD/2
ESD diodes protect the reference inputs. To keep these
diodes from turning on, make sure the voltages on the
reference pins do not go below AGND by more than
100mV, and likewise do not exceed AVDD by 100mV:
Figure 11. Analog Input Effective Impedances
with Buffer Off
−100mV < (VREFP or VREFN) < AVDD + 100mV
Table 10. Analog Input Impedances with Buffer Off
During self gain calibration, all the switches in the input
multiplexer are opened, VREFN is internally connected to
AINN, and VREFP is connected to AINP. The input buffer
may be disabled or enabled during calibration. When the
buffer is disabled, the reference pins will be driving the
circuitry shown in Figure 9 during self gain calibration,
resulting in increased loading. To prevent this additional
loading from introducing gain errors, make sure the
circuitry driving the reference pins has adequate drive
capability. When the buffer is enabled, the loading on the
reference pins will be much less, but the buffer will limit the
allowable voltage range on VREFP and VREFN during
self or self gain calibration as the reference pins must
remain within the specified input range of the buffer in
order to establish proper gain calibration.
PGA
SETTING
Zeff
Zeff
B
A
(kΩ)
260
130
65
33
16
8
(kΩ)
220
110
55
28
14
7
1
2
4
8
16
32
64
8
7
NOTE: f
CLKIN
= 7.68MHz.
VOLTAGE REFERENCE INPUTS (VREFP, VREFN)
The voltage reference for the ADS1255/6 A/D converter is
the differential voltage between VREFP and VREFN:
VREF = VREFP − VREFN. The reference inputs use a
structure similar to that of the analog inputs with the
circuitry on the reference inputs of Figure 12. The load
presented by the switched capacitor can be modeled with
A high-quality reference voltage is essential for achieving
the best performance from the ADS1255/6. Noise and drift
on the reference degrade overall system performance. It
is especially critical that special care be given to the
circuitry generating the reference voltages and their layout
when operating in the low-noise settings (that is, with low
data rates) to prevent the voltage reference from limiting
performance.
an effective impedance (ZEFF
)
of 18.5kΩ for
fCLKIN = 7.68MHz. The temperature coefficient of the
effective impedance of the voltage reference inputs is
approximately 35ppm/°C.
17
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Table 11 shows the averaging and corresponding data rate
for each of the 16 valid DRATE register settings when
fCLKIN = 7.68MHz. Note that the data rate scales directly
with the CLKIN frequency. For example, reducing fCLKIN
from 7.68MHz to 3.84MHz reduces the data rate for
DR[7:0] = 11110000 from 30,000SPS to 15,000SPS.
DIGITAL FILTER
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution digital
output. By adjusting the amount of filtering, tradeoffs can
be made between resolution and data rate: filter more for
higher resolution, filter less for higher data rate. The filter
is comprised of two sections, a fixed filter followed by a
programmable filter. Figure 13 shows the block diagram of
the analog modulator and digital filter. Data is supplied to
the filter from the analog modulator at a rate of fCLKIN/4.
The fixed filter is a 5th-order sinc filter with a decimation
value of 64 that outputs data at a rate of fCLKIN/256. The
second stage of the filter is a programmable averager
(1st-order sinc filter) with the number of averages set by
the DRATE register. The data rate is a function of the
number of averages (Num_Ave) and is given by
Equation 1.
Table 11. Number of Averages and Data Rate for
Each Valid DRATE Register Setting
NUMBER OF AVERAGES FOR
(1)
DRATE
DR[7:0]
DATA RATE
(SPS)
PROGRAMMABLE FILTER
(Num_Ave)
11110000
11100000
11010000
11000000
10110000
10100001
10010010
10000010
01110010
01100011
01010011
01000011
00110011
00100011
00010011
00000011
1 (averager bypassed)
30,000
15,000
7500
3750
2000
1000
500
100
60
2
4
8
15
fCLKIN
Data Rate + ǒ Ǔǒ
256
1
Ǔ
30
60
Num_Ave
(1)
300
500
Modulator Rate =
/4
f
600
50
f
CLKIN
1
CLKIN
256
ǒ
Ǔ
+ ǒ Ǔ
f
DataRate
CLKIN
DataRate +
256
Num_Ave
1000
30
1200
25
5
Analog
Modulator
sinc
Programmable
Averager
2000
15
Filter
3000
10
6000
5
Num_Ave
12,000
= 7.68MHz.
2.5
(set by DRATE)
(1)
for f
CLKIN
Digital Filter
Figure 13. Block Diagram of the Analog
Modulator and Digital Filter
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FREQUENCY RESPONSE
0
6
The low-pass digital filter sets the overall frequency
response for the ADS1255/6. The filter response is the
product of the responses of the fixed and programmable
filter sections and is given by Equation 2.
−
fDATA = 2.5SPS
−
−
−
−
−
−
−
−
−
12
18
24
30
36
42
48
54
60
Ť
( )Ť
Ť
f
Ť
( )
| ( )|
H f + Hsinc
·
HAverager f +
5
5
256p · Num_Ave f
256p · f
sinǒ Ǔ
sinǒ
Ǔ
ȧ
ȧ
ȧ
ȧ
ȧ ȧ
ȧ ȧ
(2)
f
f
CLKIN
CLKIN
ȧ
·
4p · f ȧ ȧ
256p · f ȧ
64 · sinǒ Ǔ Num_Ave · sinǒ Ǔ
f
f
ȧ
ȧ ȧ
ȧ
CLKIN
CLKIN
0
5
10 15 20 25 30 35 40 45 50 55 60
Frequency (Hz)
The digital filter attenuates noise on the modulator output,
including noise from within the ADS1255/6 and external
noise present on the ADS1255/6 input signal. Adjusting
the filtering by changing the number of averages used in
the programmable filter changes the filter bandwidth. With
a higher number of averages, bandwidth is reduced and
more noise is attenuated.
Figure 15. Frequency Response for
Data Rate = 2.5SPS
Table 12. First Notch Frequency and
−3dB Filter Bandwidth
The low-pass filter has notches (or zeros) at the data
output rate and multiples thereof. At these frequencies, the
filter has zero gain. This feature can be useful when trying
to eliminate a particular interference signal. For example,
to eliminate 60Hz (and the harmonics) pickup, set the data
rate equal to 2.5SPS, 5SPS, 10SPS, 15SPS, 30SPS, or
60SPS. To help illustrate the filter characteristics,
Figure 14 and Figure 15 show the responses at the data
rate extremes of 30kSPS and 2.5SPS respectively.
Table 12 summarizes the first-notch frequency and −3dB
bandwidth for the different data rate settings.
DATA RATE
(SPS)
FIRST NOTCH
(Hz)
−3dB BANDWIDTH
(Hz)
30,000
15,000
7500
3750
2000
1000
500
30,000
15,000
7500
3750
2000
1000
500
100
60
6106
4807
3003
1615
878
441
221
100
44.2
26.5
22.1
13.3
11.1
6.63
4.42
2.21
1.1
(1)
60
(2)
50
(1)
30
(2)
25
(1)
15
(3)
10
50
0
30
fDATA = 30kSPS
25
−
−
−
−
20
40
60
80
15
10
(3)
5
5
(3)
2.5
2.5
NOTE: f
(1)
= 7.68MHz.
Notch at 60Hz.
Notch at 50Hz.
CLKIN
−
−
−
100
120
140
(2)
(3)
Notch at 50Hz and 60Hz.
The digital filter low-pass characteristic repeats at
multiples of the modulator rate of fCLKIN/4. Figure 16 and
Figure 17 show the responses plotted out to 7.68MHz at
the data rate extremes of 30kSPS and 2.5SPS. Notice
how the responses near DC, 1.92MHz, 3.84MHz,
0
15
30
45
60
75
90
105
120
Frequency (kHz)
Figure 14. Frequency Response for
Data Rate = 30kSPS
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5.76MHz, 7.68MHz, are the same. The digital filter will
attenuate high-frequency noise on the ADS1255/6 inputs
up to the frequency where the response repeats. If
significant noise on the inputs is present above this
frequency, make sure to remove with external filtering.
Fortunately, this can be done on the ADS1255/6 with a
simple RC filter, as shown in the Applications Section (see
Figure 25).
Table 13. Settling Time vs Data Rate
DATA RATE
(SPS)
SETTLING TIME (t
)
18
(ms)
30,000
15,000
7500
3750
2000
1000
500
100
60
0.21
0.25
0.31
0.44
0.68
1.18
0
2.18
−
−
−
−
20
40
60
80
10.18
16.84
20.18
33.51
40.18
66.84
100.18
200.18
400.18
50
30
25
15
−
−
−
100
120
140
10
5
2.5
0
1.92
3.84
5.76
7.68
NOTE: f
CLKIN
= 7.68MHz.
Frequency (MHz)
Settling Time Using Synchronization
Figure 16. Frequency Response Out to 7.68MHz
for Data Rate = 30kSPS
The SYNC/PDWN pin allows direct control of conversion
timing. Simply issue a Sync command or strobe the
SYNC/PDWN pin after changing the analog inputs (see
the Synchronization section for more information). The
conversion begins when SYNC/PDWN is taken high,
stopping the current conversion and restarting the digital
filter. As soon as SYNC/PDWN goes low, the DRDY
output goes high and remains high during the conversion.
After the settling time (t18), DRDY goes low, indicating that
data is available. The ADS1255/6 settles in a single
cycle—there is no need to ignore or discard data after
synchronization. Figure 18 shows the data retrieval
sequence following synchronization.
0
−
−
−
−
20
40
60
80
−
−
−
100
120
140
0
1.92
3.84
5.76
7.68
AINP −AINN
SYNC/PDWN
t18
Frequency (MHz)
Figure 17. Frequency Response Out to 7.68MHz
for Data Rate = 2.5SPS
DRDY
SETTLING TIME
The ADS1255/6 features a digital filter optimized for fast
settling. The settling time (time required for a step change
on the analog inputs to propagate through the filter) for the
different data rates is shown in Table 13. The following
sections highlight the single-cycle settling ability of the
filter and show various ways to control the conversion
process.
RDATA
DIN
Settled
Data
DOUT
Figure 18. Data Retrieval After Synchronization
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Table 14gives the effective overall throughput (1/t19) when
cycling the input multiplexer. The values for throughput
(1/t19) assume the multiplexer was changed with a 3-byte
WREG command and fSCLK = fCLKIN/4.
Settling Time Using the Input Multiplexer
The most efficient way to cycle through the inputs is to
change the multiplexer setting (using a WREG command
to the multiplexer register MUX) immediately after DRDY
goes low. Then, after changing the multiplexer, restart the
conversion process by issuing the SYNC and WAKEUP
commands, and retrieve the data with the RDATA
command. Changing the multiplexer before reading the
data allows the ADS1256 to start measuring the new input
channel sooner. Figure 19 demonstrates efficient input
cycling. There is no need to ignore or discard data while
cycling through the channels of the input multiplexer
because the ADS1256 fully settles before DRDY goes low,
indicating data is ready.
Table 14. Multiplexer Cycling Throughput
DATA RATE
(SPS)
CYCLING THROUGHPUT (1/t
)
19
(Hz)
30,000
15,000
7500
3750
2000
1000
500
100
60
4374
3817
3043
2165
1438
837
456
98
Step 1: When DRDY goes low, indicating that data is ready
for retrieval, update the multiplexer register MUX using the
WREG command. For example, setting MUX to 23h gives
AINP = AIN2, AINN = AIN3.
59
Step 2: Restart the conversion process by issuing a SYNC
command immediately followed by a WAKEUP command.
Make sure to follow timing specification t11 between
commands.
50
50
30
30
25
25
15
15
Step 3: Read the data from the previous conversion using
the RDATA command.
10
10
5
5
Step 4: When DRDY goes low again, repeat the cycle by
first updating the multiplexer register, then reading the
previous data.
2.5
2.5
NOTE: f
CLKIN
= 7.68MHz.
t
t
19
18
DRDY
WREG 45h
to MUX reg
WREG 23h
to MUX reg
DIN
SYNC
WAKEUP
RDATA
SYNC
WAKEUP
RDATA
Data from
Data from
DOUT
MUX = 01h
MUX = 23h
23h
AIN = AIN2, AIN = AIN3
45h
AIN = AIN4, AIN = AIN5
01h
AIN = AIN0, AIN = AIN
1
MUX
Register
P
N
P
N
P
N
Figure 19. Cycling the ADS1256 Input Multiplexer
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the previous and current input signal and should therefore
be discarded. Figure 21 shows an example of readback in
this situation.
Settling Time Using One-Shot Mode
A dramatic reduction in power consumption can be achieved
in the ADS1255/6 by performing one-shot conversions using
the STANDBY command; the sequence for this is shown in
Figure 20. Issue the WAKEUP command from Standby
mode to begin a one-shot conversion. Following the settling
time (t18), DRDY will go low, indicating that the conversion is
complete and data can be read using the RDATA command.
The ADs1255/6 settles in a single cycle—there is no need to
ignore or discard data. Following the data read cycle, issue
another STANDBY command to reduce power consumption.
When ready for the next measurement, repeat the cycle
starting with another WAKEUP command.
Table 15. Data Settling Delay vs Data Rate
DATA RATE
(SPS)
SETTLING TIME
(DRDY Periods)
30,000
15,000
7500
3750
2000
1000
500
100
60
5
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
Settling Time while Continuously Converting
After a synchronization, input multiplexer change, or
wakeup from Standby mode, the ADS1255/6 will
continuously convert the analog input. The conversions
coincide with the falling edge of DRDY. While continuously
converting, it is often more convenient to consider settling
times in terms of DRDY periods, as shown in Table 15.
The DRDY period equals the inverse of the data rate.
50
30
25
15
If there is a step change on the input signal while
continuously converting, performing a synchronization
operation to start a new conversion is recommended.
Otherwise, the next data will represent a combination of
10
5
2.5
Standby
Mode
Standby
Mode
ADS1255/6
Status
Performing One−Shot Conversion
t18
DRDY
DIN
STANDBY
RDATA
WAKEUP
STANDBY
DOUT
Settled
Data
Figure 20. One-Shot Conversions Using the STANDBY Command
New VIN
−
V
IN = AINP AINN
Old VIN
Mix of
Old and New
VIN Data
Fully Settled
New VIN Data
Old VIN Data
DRDY
RDATA
DIN
Settled
Data
DOUT
Figure 21. Step Change on V while Continuously Converting for Data Rates ≤ 3750SPS
IN
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DATA FORMAT
CLOCK OUTPUT (D0/CLKOUT)
The ADS1255/6 output 24 bits of data in Binary Two’s
The clock output pin can be used to clock another device,
such as a microcontroller. This clock can be configured to
operate at frequencies of fCLKIN, fCLKIN/2, or fCLKIN/4 using
CLK1 and CLK0 in the ADCON register. Note that enabling
the output clock and driving an external load will increase
the digital power dissipation. Standby mode does not
affect the clock output status. That is, if Standby is
enabled, the clock output will continue to run during
Standby mode. If the clock output function is not needed,
it should be disabled by writing to the ADCON register after
power-up or reset.
Complement format. The LSB has
a weight of
2VREF/(PGA(223 − 1)). A positive full-scale input produces
an output code of 7FFFFFh and the negative full-scale
input produces an output code of 800000h. The output
clips at these codes for signals exceeding full-scale.
Table 16 summarizes the ideal output codes for different
input signals.
Table 16. Ideal Output Code vs Input Signal
INPUT SIGNAL V
IN
(1)
IDEAL OUTPUT CODE
(AIN − AIN )
P
N
CLOCK GENERATION
) 2VREF
7FFFFFh
The master clock source for the ADS1255/6 can be
provided using an external crystal or clock generator.
When the clock is generated using a crystal, external
capacitors must be provided to ensure start-up and a
stable clock frequency, as shown in Figure 22. Table 17
lists two recommended crystals. Long leads should be
minimized with the crystal placed close to the ADS1255/6
pins. For information on ceramic resonators, see
application note SBAA104, Using Ceramic Resonators
with the ADS1255/6, available for download at
www.ti.com.
w
PGA
) 2VREF
000001h
000000h
FFFFFFh
23
(
)
PGA 2 * 1
0
* 2VREF
23
(
)
PGA 2 * 1
* 2VREF
223
223 * 1
800000h
ǒ
Ǔ
v
PGA
(1)
Excludes effects of noise, INL, offset, and gain errors.
XTAL1/CLKIN
C1
GENERAL-PURPOSE DIGITAL I/O (D0-D3)
Crystal
The ADS1256 has 4 pins dedicated for digital I/O and the
ADS1255 has 2 digital I/O pins. All of the digital I/O pins are
individually configurable as either inputs or outputs
through the IO register. The DIR bits of the IO register
define whether each pin is an input or output, and the DIO
bits control the status of the pins. Reading back the DIO
register shows the state of the digital I/O pins, whether they
are configured as inputs or outputs by the DIR bits. When
digital I/O pins are configured as inputs, the DIO register
is used to read the state of these pins. When configured as
outputs, DIO sets the output value. On the ADS1255, the
digital I/O pins D2 and D3 do not exist and the settings of
the IO register bits that control operation of D2 and D3
have no effect on that device.
XTAL2
C2
C1, C2: 5pF to 20pF
Figure 22. Crystal Connection
Table 17. Recommended Crystals
PART
NUMBER
MANUFACTURER
FREQUENCY
Citizen
ECS
7.68MHz
8.0MHz
CIA/53383
ECS-80-5-4
During Standby and Power-Down modes, the GPIO
remain active. If configured as outputs, they continue to
drive the pins. If configured as inputs, they must be driven
(not left floating) to prevent excess power dissipation.
When using a crystal, neither the XTAL1/CLKIN nor
XTAL2 pins can be used to drive any other logic. If other
devices need a clock source, the D0/CLKOUT pin is
available for this function. When using an external clock
generator, supply the clock signal to XTAL1/CLKIN and
leave XTAL2 floating. Make sure the external clock
generator supplies a clean clock waveform. Overshoot
and glitches on the clock will degrade overall performance.
The digital I/O pins are set as inputs after power-up or a
reset, except for D0/CLKOUT, which is enabled as a clock
output. If the digital I/O pins are not used, either leave them
as inputs tied to ground or configure them as outputs. This
prevents excess power dissipation.
23
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CALIBRATION
PGA · VIN
2VREF
OFC
Output + ǒ
ǓFSC
*
·
b
a
Offset and gain errors can be minimized using the
ADS1255/6 onboard calibration circuitry. Figure 23 shows
the calibration block diagram. Offset errors are corrected
with the Offset Calibration (OFC) register and, likewise,
full-scale errors are corrected with the Full-Scale
Calibration (FSC) register. Each of these registers is
24-bits and can be read from or written to.
(3)
where α and β vary with data rate settings shown in
Table 18 along with the ideal values (assumes perfect
analog performance) for OFC and FSC. OFC is a Binary
Two’s Complement number that can range from
−8,388,608 to 8,388,607, while FSC is unipolar ranging
from 0 to 16,777,215.
The ADS1255/6 supports both self-calibration and system
calibration for any PGA setting using a set of five
commands: SELFOCAL, SELFGCAL, SELFCAL,
SYSOCAL, and SYSGCAL. Calibration can be done at
any time, though in many applications the ADS1255/6 drift
performance is low enough that a single calibration is all
that is needed. DRDY goes high when calibration begins
and remains so until settled data is ready afterwards.
There is no need to discard data after a calibration. It is
VREFP VREFN
AINP
AINN
Analog
Modulator
Digital
Filter
PGA
Output
Σ
X
OFC
Register
FSC
Register
strongly recommended to issue
a
self-calibration
Figure 23. Calibration Block Diagram
command after power-up when the reference has
stabilized. After a reset, the ADS1255/6 performs
self-calibration. Calibration must be performed whenever
the data rate changes and should be performed when the
buffer configuration or PGA changes.
The output of the ADS1255/6 after calibration is shown in
Equation 3.
Table 18. Calibration Values for Different Data Rate Settings
DATA RATE
(SPS)
α
β
IDEAL OFC
000000
IDEAL FSC
44AC08
30,000
15,000
7500
3750
2000
1000
500
100
60
400000
1.8639
1.8639
1.8639
1.8639
1.7474
1.7474
1.7474
2.1843
1.8202
2.1843
1.8202
2.1843
1.8202
2.7304
2.7304
2.7304
H
H
H
400000
000000
44AC08
H
44AC08
H
44AC08
H
494008
H
494008
H
494008
H
3A99A0
H
4651F3
H
3A99A0
H
4651F3
H
3A99A0
H
4651F3
H
2EE14C
H
2EE14C
H
2EE14C
H
H
H
400000
000000
H
H
400000
000000
H
H
3C0000
000000
H
H
3C0000
000000
H
H
3C0000
000000
H
H
4B0000
000000
H
H
3E8000
000000
H
H
50
4B0000
000000
H
H
30
3E8000
000000
H
H
25
4B0000
000000
H
H
15
3E8000
000000
H
H
10
5DC000
000000
H
H
5
5DC000
000000
H
H
2.5
5DC000
000000
H
H
24
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Self-Calibration
Table 20. Self Gain Calibration Timing
Self-calibration corrects internal offset and gain errors.
During self-calibration, the appropriate calibration signals
are applied internally to the analog inputs.
PGA SETTING
4
DATA RATE
(SPS)
1
2
8
16, 32, 64
651µs
30,000
15,000
7500
3750
2000
1000
500
100
60
417µs
484µs
617µs
417µs
484µs
617µs
451µs
517µs
551µs
617µs
SELFOCAL performs a self offset calibration. The analog
inputs AINP and AINN are disconnected from the signal
source and connected to AVDD/2. See Table 19 for the
time required for self offset calibration for the different data
rate settings. As with most of the ADS1255/6 timings, the
calibration time scales directly with fCLKIN. Self offset
calibration updates the OFC register.
484µs
551µs
617µs
751µs
884
1.4ms
2.4ms
4.5ms
21.0ms
34.1ms
41.7ms
67.8ms
83.0ms
135.3ms
207.0ms
413.7ms
827.0ms
Table 19. Self Offset and System Offset
Calibration Timing
50
30
DATA RATE
(SPS)
SELF OFFSET CALIBRATION AND
SYSTEM OFFSET CALIBRATION TIME
25
15
30,000
15,000
7500
3750
2000
1000
500
100
60
387µs
453µs
10
5
587µs
2.5
853µs
NOTE: For f
= 7.68MHz.
CLKIN
1.3ms
2.3ms
SELFCAL performs first a self offset and then a self gain
calibration. The analog inputs are disconnected from the
from the signal source during self-calibration. When using
the input buffer with self-calibration, make sure to observe
the common-mode range of the reference inputs as
described above. Table 21 shows the time required for
self-calibration for the different data rate settings.
Self-calibration updates both the OFC and FSC registers.
4.3ms
20.3ms
33.7ms
40.3ms
67.0ms
80.3ms
133.7ms
200.3ms
400.3ms
800.3ms
50
30
25
15
10
Table 21. Self-Calibration Timing
5
2.5
PGA SETTING
4
DATA RATE
(SPS)
1
2
8
16, 32, 64
892µs
NOTE: For f
CLKIN
= 7.68MHz.
30,000
15,000
7500
3750
2000
1000
500
100
60
596µs
696µs
896µs
596µs
696µs
896µs
692µs
696µs
762µs
896µs
696µs
896µs
SELFGCAL performs a self gain calibration. The analog
inputs AINP and AINN are disconnected from the signal
source and AINP is connected internally to VREFP while
AINN is connected to VREFN. Self gain calibration can be
used with any PGA setting, and the ADS1255/6 has
excellent gain calibration even for the higher PGA settings,
as shown in the Typical Characteristics section. Using the
buffer will limit the common-mode range of the reference
inputs during self gain calibration since they will be
connected to the buffer inputs and must be within the
specified analog input range. When the voltage on VREFP
or VREFN exceeds the buffer analog input range
(AVDD – 2.0V), the buffer must be turned off during self
gain calibration. Otherwise, use system gain calibration or
write the gain coefficients directly to the FSC register.
Table 20 shows the time required for self gain calibration
for the different data rate and PGA settings. Self gain
calibration updates the FSC register.
896µs
1029µs
1.3ms
2.0ms
3.6ms
6.6ms
31.2ms
50.9ms
61.8ms
101.3ms
123.2ms
202.1ms
307.2ms
613.8ms
1227.2ms
50
30
25
15
10
5
2.5
NOTE: For f
= 7.68MHz.
CLKIN
25
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System Calibration
SERIAL INTERFACE
System calibration corrects both internal and external
offset and gain errors using the SYSOCAL and SYSGCAL
commands. During system calibration, the appropriate
calibration signals must be applied by the user to the
inputs.
The SPI-compatible serial interface consists of four
signals: CS, SCLK, DIN, and DOUT, and allows a
controller to communicate with the ADS1255/6. The
programmable functions are controlled using a set of
on-chip registers. Data is written to and read from these
registers via the serial interface
SYSOCAL performs a system offset calibration. The user
must supply a zero input differential signal. The
ADS1255/6 then computes a value that will nullify the
offset in the system. Table 22 shows the time required for
system offset calibration for the different data rate settings.
Note this timing is the same for the self offset calibration.
System offset calibration updates the OFC register.
The DRDY output line is used as a status signal to indicate
when a conversion has been completed. DRDY goes low
when new data is available. The Timing Specification
shows the timing diagram for interfacing to the
ADS1255/6.
SYSGCAL performs a system gain calibration. The user
must supply a full-scale input signal to the ADS1255/6.
The ADS1255/6 then computes a value to nullify the gain
error in the system. System gain calibration can correct
inputs that are 80% of the full-scale input voltage and
larger. Make sure not to exceed the full-scale input voltage
when using system gain calibration. Table 22 shows the
time required for system gain calibration for the different
data rate settings. System gain calibration updates the
FSC register.
CHIP SELECT (CS)
The chip select (CS) input allows individual selection of a
ADS1255/6 device when multiple devices share the serial
bus. CS must remain low for the duration of the serial
communication. When CS is taken high, the serial
interface is reset and DOUT enters a high impedance
state. CS may be permanently tied low.
SERIAL CLOCK (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input
and is used to clock data on the DIN and DOUT pins into
and out of the ADS1255/6. Even though the input has
hysteresis, it is recommended to keep SCLK as clean as
possible to prevent glitches from accidentally shifting the
data. If SCLK is held low for 32 DRDY periods, the serial
interface will reset and the next SCLK pulse will start a new
communication cycle. This timeout feature can be used to
recover communication when a serial interface transmis-
sion is interrupted. A special pattern on SCLK will reset the
chip; see the RESET section for more details on this
procedure.
Table 22. System Gain Calibration Timing
DATA RATE
SYSTEM GAIN CALIBRATION TIME
(SPS)
30,000
15,000
7500
3750
2000
1000
500
100
60
417µs
484µs
617µs
884µs
1.4ms
2.4ms
4.4ms
20.4ms
33.7ms
40.4ms
67.0ms
80.4ms
133.7ms
200.4ms
400.4ms
800.4ms
DATA INPUT (DIN) AND DATA OUTPUT (DOUT)
The data input pin (DIN) is used along with SCLK to send
data to the ADS1255/6. The data output pin (DOUT) along
with SCLK is used to read data from the ADS1255/6. Data
on DIN is shifted into the part on the falling edge of SCLK
while data is shifted out on DOUT on the rising edge of
SCLK. DOUT is high impedance when not in use to allow
DIN and DOUT to be connected together and be driven by
a bi-directional bus. Note: the RDATAC command must
not be issued while DIN and DOUT are connected
together.
50
30
25
15
10
5
2.5
NOTE: For f
= 7.68MHz.
CLKIN
Auto-Calibration
Auto-calibration can be enabled (ACAL bit in ADCON
register) to have the ADS1255/6 automatically initiate a
self-calibration at the completion of a write command
(WREG) that changes the data rate, PGA setting, or Buffer
status.
26
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DATA READY (DRDY)
STANDBY MODE
The DRDY output is used as a status signal to indicate
when conversion data is ready to be read. DRDY goes low
when new conversion data is available. It is reset high
when all 24 bits have been read back using Read Data
(RDATA) or Read Data Continuous (RDATAC) command.
It also goes high when the new conversion data is being
updated. Do not retrieve during this update period as the
data is invalid. If data is not retrieved, DRDY will only be
high during the update time as shown in Figure 24.
The standby mode shuts down all of the analog circuitry
and most of the digital features. The oscillator continues to
run to allow for fast wakeup. If enabled, clock output
D0/CLKOUT will also continue to run during during
Standby mode. To enter Standby mode, issue the
STANDBY command. To exit Standby mode, issue the
WAKEUP command. DRDY will stay high after exiting
Standby mode until valid data is ready. Standby mode can
be used to perform one-shot conversions; see Settling
Time Using One-Shot Mode section for more details.
Data Updating
POWER-DOWN MODE
Holding the SYNC/PDWN pin low for 20 DRDY cycles
activates the Power-Down mode. During Power-Down
mode, all circuitry is disabled including the oscillator and
the clock output.
DRDY
Figure 24. DRDY with No Data Retreival
To exit Power-Down mode, take the SYNC/PDWN pin
high. Upon exiting from Power-Down mode, the
ADS1255/6 crystal oscillator typically requires 30ms to
wake up. If using an external clock source, 8192 CLKIN
cycles are needed before conversions begin.
After changing the PGA, data rate, buffer status, writing to
the OFC or FSC registers, and enabling or disabling the
sensor detect circuitry, perform
a synchronization
operation to force DRDY high. It will stay high until valid
data is ready. If auto-calibration is enabled (by setting the
ACAL bit in the ADCON register), DRDY will go low after
the self-calibration is complete and new data is valid.
Exiting from Reset, Synchronization, Standby or
Power-Down mode will also force DRDY high. DRDY will
go low as soon as valid data is ready.
RESET
There are three methods to reset the ADS1255/6: the
RESET input pin, RESET command, and a special SCLK
reset pattern.
When using the RESET pin, take it low to force a reset.
Make sure to follow the minimum pulse width timing
specifications before taking the RESET pin back high.
SYNCHRONIZATION
The RESET command takes effect after all eight bits have
been shifted into DIN. Afterwards, the reset releases
automatically.
Synchronization of the ADS1255/6 is available to
coordinate the A/D conversion with an external event and
also to speed settling after an instantaneous change on
the analog inputs (see Conversion Time using
Synchronization section).
The ADS1255/6 can also be reset with a special pattern on
SCLK (see Figure 2). Reset occurs on the falling edge of
the last SCLK edge in the pattern. After performing the
operation, the reset releases automatically.
Synchronization can be achieved either using the
SYNC/PDWN pin or with the SYNC command. To use the
SYNC/PDWN pin, take it low and then high, making sure
to meet timing specification t16. Synchronization occurs on
the first rising edge of the master clock after SYNC/PDWN
is taken high. No communication is possible on the serial
interface while SYNC/PDWN is low. If the SYNC/PDWN
pin is held low for 20 DRDY periods the ADS1255/6 will
enter Power-Down mode.
On reset, the configuration registers are initialized to their
default state except for the CLK0 and CLK1 bits in the
ADCON register that control the D0/CLKOUT pin. These
bits are only initialized to the default state when RESET is
performed using the RESET pin. After releasing from
RESET, self-calibration is performed, regardless of the
reset method or the state of the ACAL bit before RESET.
To synchronize using the SYNC command, first shift in all
eight bits of the SYNC command. This stops the operation
of the ADS1255/6. When ready to synchronize, issue the
WAKEUP command. Synchronization occurs on the first
rising edge of the master clock after the first SCLK used to
shift in the WAKEUP command. After a synchronization
operation, either with the SYNC/PDWN pin or the SYNC
command, DRDY stays high until valid data is ready.
POWER-UP
All of the configuration registers are initialized to their
default state at power-up. A self-calibration is then
performed automatically. For the best performance, it is
strongly recommended to perform an additional
self-calibration by issuing the SELFCAL command after
the power supplies and voltage reference have had time
to settle to their final values.
27
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the digital pins can help by controlling the trace
impedance. When not using the RESET or SYNC/PDWN
inputs, tie directly to the ADS1255/6 DVDD pin.
APPLICATIONS INFORMATION
GENERAL RECOMMENDATIONS
The ADS1255 and ADS1256 are very high-resolution A/D
converters. Getting the optimal performance from them
requires careful attention to their support circuitry and
printed circuit board (PCB) design. Figure 25 shows the
basic connections for the ADS1255. It is recommended to
use a single ground plane for both the analog and digital
supplies. This ground plane should be shared with the
bypass capacitors and analog conditioning circuits.
However, avoid using this ground plane for noisy digital
components such as microprocessors. If a split ground
plane is used with the ADS1255/6, make sure the analog
and digital planes are tied together. There should not be a
voltage difference between the ADS1255/6 analog and
digital ground pins (AGND and DGND).
Pay special attention to the reference and analog inputs.
These are the most critical circuits. On the voltage
reference inputs, bypass with low equivalent series
resistance (ESR) capacitors. Make these capacitors as
large as possible to maximize the filtering on the reference.
With the outstanding performance of the ADS1255/6, it is
easy for the voltage reference to limit overall performance
if not carefully selected. When using a stand-alone
reference, make sure it is very low noise and very low drift.
Ratiometric measurements, where the input signal and
reference track each other, are somewhat less sensitive,
but verify the reference signal is clean.
Often times, only a simple RC filter (as shown in Figure 25)
is needed on the inputs. This circuit limits the
high-frequency noise near the modulator frequency; see
the Frequency Response section. Avoid low-grade
dielectrics for the capacitors to minimize temperature
variations and leakage. Keep the input traces as short as
possible and place the components close to the input pins.
When using the ADS1256, make sure to filter all the input
channels being used.
As with any precision circuit, use good supply bypassing
techniques. A smaller value ceramic capacitor in parallel
with a larger value tantalum or a larger value low-voltage
ceramic capacitor works well. Place the capacitors, in
particular the ceramic ones, close to the supply pins. Run
the digital logic off as low of voltage as possible. This helps
reduce coupling back to the analog inputs. Avoid ringing
on the digital inputs. Small resistors (≈100Ω) in series with
+5V
ADS1255
µ
µ
0.1 F
10 F
1
2
3
4
5
6
7
8
9
AVDD
D1 20
19
18
17
AGND
D0/CLKOUT
SCLK
Ω
Ω
Ω
49.9
100
VREFN
VREFP
AINCOM
AIN0
µ
µ
47 F
0.1 F
100pF
100pF
DIN
2.5V
Ω
Ω
100
100
49.9
DOUT 16
Ω
301
301
15
14
13
DRDY
CS
VINP
VINN
µ
0.1 F
AIN1
Ω
SYNC/PDWN
RESET
XTAL1/CLKIN
18pF
18pF
7.68MHz
XTAL2 12
DGND 11
10 DVDD
+3.3V
µ
10 F
µ
0.1 F
Figure 25. ADS1255 Basic Connections
28
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DIGITAL INTERFACE CONNECTIONS
ADS1255
ADS1256
MSC12xx or
68HC11
The ADS1255/6 5V tolerant SPI-, QSPI, and
MICROWIRE-compatible interface easily connects to a
wide variety of microcontrollers. Figure 26 shows the basic
connection to TI’s MSP430 family of low-power
microcontrollers. Figure 27 shows the connection to
microcontrollers with an SPI interface like TI’s MSC12xx
family or the 68HC11 family. Note that the MSC12xx
includes a high-resolution A/D converter; the ADS1255/6
can be used to add additional channels of measurement
or provide higher-speed conversions. Finally, Figure 28
shows how to connect the ADS1255/6 to an 8xC51 UART
in serial mode 0 in a 2-wire configuration. Avoid using the
continuous read mode (RDATAC) when DIN and DOUT
are connected together.
DIN
MOSI
MISO
INT
DOUT
DRDY
SCLK
CS(1)
SCK
IO
(1) CS may be tied low.
Figure 27. Connection to Microcontrollers with
an SPI Interface
ADS1255
ADS1256
MSP430
ADS1255
ADS1256
8xC51
DIN
P1.3
P1.2
P1.0
P1.6
P1.4
DOUT
DRDY
SCLK
CS(1)
DIN
P3.0/RXD
DOUT
DRDY
SCLK
CS
P3.1xTXD
(1) CS may be tied low.
DGND
Figure 26. Connection to MSP430
Microcontroller
Figure 28. Connection to 8xC51 Microcontroller
UART with a 2-Wire Interface
29
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REGISTER MAP
The operation of the ADS1255/6 is controlled through a set of registers. Collectively, the registers contain all the information
needed to configure the part, such as data rate, multiplexer settings, PGA setting, calibration, etc., and are listed in
Table 23.
Table 23. Register Map
RESET
VALUE
ADDRESS
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
STATUS
MUX
x1
01
20
ID3
ID2
ID1
ID0
ORDER
NSEL3
SDCS0
DR3
ACAL
NSEL2
PGA2
DR2
BUFEN
NSEL1
PGA1
DRDY
NSEL0
PGA0
DR0
H
H
H
PSEL3
0
PSEL2
CLK1
PSEL1
CLK0
PSEL0
SDCS1
DR4
ADCON
DRATE
IO
F0
H
DR7
DR6
DR5
DR1
E0
DIR3
DIR2
DIR1
DIR0
DIO3
DIO2
DIO1
DIO0
H
H
H
H
H
H
H
OFC0
OFC1
OFC2
FSC0
FSC1
FSC2
xx
xx
xx
xx
xx
xx
OFC07
OFC15
OFC23
FSC07
FSC15
FSC23
OFC06
OFC14
OFC22
FSC06
FSC14
FSC22
OFC05
OFC13
OFC21
FSC05
FSC13
FSC21
OFC04
OFC12
OFC20
FSC04
FSC12
FSC20
OFC03
OFC11
OFC19
FSC03
FSC11
FSC19
OFC02
OFC10
OFC18
FSC02
FSC10
FSC18
OFC01
OFC09
OFC17
FSC01
FSC09
FSC17
OFC00
OFC08
OFC16
FSC00
FSC08
FSC16
STATUS : STATUS REGISTER (ADDRESS 00h)
Reset Value = x1h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
ORDER
BIT 2
ACAL
BIT 1
BUFEN
BIT 0
DRDY
ID
ID
ID
ID
Bits 7-4 ID3, ID2, ID1, ID0 Factory Programmed Identification Bits (Read Only)
Bit 3
ORDER: Data Output Bit Order
0 = Most Significant Bit First (default)
1 = Least Significant Bit First
Input data is always shifted in most significant byte and bit first. Output data is always shifted out most significant
byte first. The ORDER bit only controls the bit order of the output data within the byte.
Bit 2
ACAL: Auto-Calibration
0 = Auto-Calibration Disabled (default)
1 = Auto-Calibration Enabled
When Auto-Calibration is enabled, self-calibration begins at the completion of the WREG command that changes
the PGA (bits 0-2 of ADCON register), DR (bits 7-0 in the DRATE register) or BUFEN (bit 1 in the STATUS register)
values.
Bit 1
Bit 0
BUFEN: Analog Input Buffer Enable
0 = Buffer Disabled (default)
1 = Buffer Enabled
DRDY: Data Ready (Read Only)
This bit duplicates the state of the DRDY pin.
30
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MUX : Input Multiplexer Control Register (Address 01h)
Reset Value = 01h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PSEL3
PSEL2
PSEL1
PSEL0
NSEL3
NSEL2
NSEL1
NSEL0
Bits 7-4 PSEL3, PSEL2, PSEL1, PSEL0: Positive Input Channel (AINP) Select
0000 = AIN0 (default)
0001 = AIN1
0010 = AIN2 (ADS1256 only)
0011 = AIN3 (ADS1256 only)
0100 = AIN4 (ADS1256 only)
0101 = AIN5 (ADS1256 only)
0110 = AIN6 (ADS1256 only)
0111 = AIN7 (ADS1256 only)
1xxx = AINCOM (when PSEL3 = 1, PSEL2, PSEL1, PSEL0 are “don’t care”)
NOTE: When using an ADS1255 make sure to only select the available inputs.
Bits 3-0 NSEL3, NSEL2, NSEL1, NSEL0: Negative Input Channel (AINN)Select
0000 = AIN0
0001 = AIN1 (default)
0010 = AIN2 (ADS1256 only)
0011 = AIN3 (ADS1256 only)
0100 = AIN4 (ADS1256 only)
0101 = AIN5 (ADS1256 only)
0110 = AIN6 (ADS1256 only)
0111 = AIN7 (ADS1256 only)
1xxx = AINCOM (when NSEL3 = 1, NSEL2, NSEL1, NSEL0 are “don’t care”)
NOTE: When using an ADS1255 make sure to only select the available inputs.
ADCON: A/D Control Register (Address 02h)
Reset Value = 20h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
CLK1
CLK0
SDCS1
SDCS0
PGA2
PGA1
PGA0
Bit 7
Reserved, always 0 (Read Only)
Bits 6-5 CLK1, CLK0: D0/CLKOUT Clock Out Rate Setting
00 = Clock Out OFF
01 = Clock Out Frequency = fCLKIN (default)
10 = Clock Out Frequency = fCLKIN/2
11 = Clock Out Frequency = fCLKIN/4
When not using CLKOUT, it is recommended that it be turned off. These bits can only be reset using the RESET pin.
Bits 4-2 SDCS1, SCDS0: Sensor Detect Current Sources
00 = Sensor Detect OFF (default)
01 = Sensor Detect Current = 0.5µA
10 = Sensor Detect Current = 2µA
11 = Sensor Detect Current = 10µA
The Sensor Detect Current Sources can be activated to verify the integrity of an external sensor supplying a signal to the
ADS1255/6. A shorted sensor produces a very small signal while an open-circuit sensor produces a very large signal.
Bits 2-0 PGA2, PGA1, PGA0: Programmable Gain Amplifier Setting
000 = 1 (default)
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 64
31
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DRATE: A/D Data Rate (Address 03h)
Reset Value = F0h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
The 16 valid Data Rate settings are shown below. Make sure to select a valid setting as the invalid settings may produce
unpredictable results.
Bits 7-0 DR[7: 0]: Data Rate Setting(1)
11110000 = 30,000SPS (default)
11100000 = 15,000SPS
11010000 = 7,500SPS
11000000 = 3,750SPS
10110000 = 2,000SPS
10100001 = 1,000SPS
10010010 = 500SPS
10000010 = 100SPS
01110010 = 60SPS
01100011 = 50SPS
01010011 = 30SPS
01000011 = 25SPS
00110011 = 15SPS
00100011 = 10SPS
00010011 = 5SPS
00000011 = 2.5SPS
(1)
for f
= 7.68MHz. Data rates scale linearly with f .
CLKIN
CLKIN
I/O: GPIO Control Register (Address 04 )
H
Reset Value = E0h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DIR3
DIR2
DIR1
DIR0
DIO3
DIO2
DIO1
DIO0
The states of these bits control the operation of the general-purpose digital I/O pins. The ADS1256 has 4 I/O pins: D3, D2,
D1, and D0/CLKOUT. The ADS1255 has two digital I/O pins: D1 and D0/CLKOUT. When using an ADS1255, the register
bits DIR3, DIR2, DIO3, and DIO2 can be read from and written to but have no effect.
Bit 7
Bit 6
Bit 5
Bit 4
DIR3, Digital I/O Direction for Digital I/O Pin D3 (used on ADS1256 only)
0 = D3 is an output
1 = D3 is an input (default)
DIR2, Digital I/O Direction for Digital I/O Pin D2 (used on ADS1256 only)
0 = D2 is an output
1 = D2 is an input (default)
DIR1, Digital I/O Direction for Digital I/O Pin D1
0 = D1 is an output
1 = D1 is an input (default)
DIR0, Digital I/O Direction for Digital I/O Pin D0/CLKOUT
0 = D0/CLKOUT is an output (default)
1 = D0/CLKOUT is an input
Bits 3-0 DI0[3:0]: Status of Digital I/O Pins D3, D2, D1, D0/CLKOUT
Reading these bits will show the state of the corresponding digital I/O pin, whether if the pin is configured as an
input or output by DIR3-DIR0. When the digital I/O pin is configured as an output by the DIR bit, writing to the
corresponding DIO bit will set the output state. When the digital I/O pin is configured as an input by the DIR bit,
writing to the corresponding DIO bit will have no effect. When DO/CLKOUT is configured as an output and
CLKOUT is enabled (using CLK1, CLK0 bits in the ADCON register), writing to DIO0 will have no effect.
32
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OFC0: Offset Calibration Byte 0, least significant byte (Address 05h)
Reset value depends on calibration results.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC07
OFC06
OFC05
OFC04
OFC03
OFC02
OFC01
OFC00
OFC1: Offset Calibration Byte 1 (Address 06h)
Reset value depends on calibration results.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC15
OFC14
OFC13
OFC12
OFC11
OFC10
OFC09
OFC08
OFC2: Offset Calibration Byte 2, most significant byte (Address 07h)
Reset value depends on calibration results.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OFC23
OFC22
OFC21
OFC20
OFC19
OFC18
OFC17
OFC16
FSC0: Full−scale Calibration Byte 0, least significant byte (Address 08h)
Reset value depends on calibration results.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC07
FSC06
FSC05
FSC04
FSC03
FSC02
FSC01
FSC00
FSC1: Full−scale Calibration Byte 1 (Address 09h)
Reset value depends on calibration results.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC09
FSC08
FSC2: Full−scale Calibration Byte 2, most significant byte (Address 0Ah)
Reset value depends on calibration results.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
33
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COMMAND DEFINITIONS
The commands summarized in Table 24 control the operation of the ADS1255/6. All of the commands are stand-alone
except for the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional
command and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUS
register sets the order of the bits within the output data. CS must stay low during the entire command sequence.
Table 24. Command Definitions
COMMAND
WAKEUP
RDATA
DESCRIPTION
Completes SYNC and Exits Standby Mode
Read Data
1ST COMMAND BYTE
2ND COMMAND BYTE
0000 0000
0000 0001
0000 0011
0000 1111
0001 rrrr
(00h)
(01h)
(03h)
(0Fh)
(1xh)
(5xh)
(F0h)
(F1h)
(F2h)
(F3h)
(F4h)
(FCh)
(FDh)
(FEh)
(FFh)
RDATAC
SDATAC
RREG
Read Data Continuously
Stop Read Data Continuously
Read from REG rrr
0000 nnnn
0000 nnnn
WREG
Write to REG rrr
0101 rrrr
SELFCAL
SELFOCAL
SELFGCAL
SYSOCAL
SYSGCAL
SYNC
Offset and Gain Self-Calibration
Offset Self-Calibration
1111 0000
1111 0001
1111 0010
1111 0011
1111 0100
1111 1100
1111 1101
1111 1110
1111 1111
Gain Self-Calibration
System Offset Calibration
System Gain Calibration
Synchronize the A/D Conversion
Begin Standby Mode
STANDBY
RESET
Reset to Power-Up Values
Completes SYNC and Exits Standby Mode
WAKEUP
NOTE: n = number of registers to be read/written − 1. For example, to read/write three registers, set nnnn = 2 (0010).
r = starting register address for read/write commands.
RDATA: Read Data
Description: Issue this command after DRDY goes low to read a single conversion result. After all 24 bits have been shifted
out on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new
data is being updated. See the Timing Characteristics for the required delay between the end of the RDATA command and
the beginning of shifting data on DOUT: t6.
DRDY
DIN
0000 0001
DOUT
SCLK
MSB
Mid−Byte
LSB
t6
• • •
• • •
Figure 29. RDATA Command Sequence
34
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RDATAC: Read Data Continuous
Description: Issue command after DRDY goes low to enter the Read Data Continuous mode. This mode enables the
continuous output of new data on each DRDY without the need to issue subsequent read commands. After all 24 bits have
been read, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY will then not return high until new data
is being updated. This mode may be terminated by the Stop Read Data Continuous command (STOPC). Because DIN
is constantly being monitored during the Read Data Continuous mode for the STOPC or RESET command, do not use
this mode if DIN and DOUT are connected together. See the Timing Characteristics for the required delay between the end
of the RDATAC command and the beginning of shifting data on DOUT: t6.
DRDY
DIN
0000 0011
t6
DOUT
24 Bits
24 Bits
Figure 30. RDATAC Command Sequence
On the following DRDY, shift out data by applying SCLKs. The Read Data Continuous mode terminates if input_data equals
the STOPC or RESET command in any of the three bytes on DIN.
DRDY
DIN
input_data
MSB
input_data
Mid−Byte
input_data
LSB
DOUT
Figure 31. DIN and DOUT Command Sequence During Read Continuous Mode
STOPC: Stop Read Data Continuous
Description: Ends the continuous data output mode. (see RDATAC). The command must be issued after DRDY goes low
and completed before DRDY goes high.
DRDY
DIN
000 1111
Figure 32. STOPC Command Sequence
35
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RREG: Read from Registers
Description: Output the data from up to 11 registers starting with the register address specified as part of the command.
The number of registers read will be one plus the second byte of the command. If the count exceeds the remaining registers,
the addresses will wrap back to the beginning.
1st Command Byte: 0001 rrrr where rrrr is the address of the first register to read.
2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to read – 1. See the Timing Characteristics for the
required delay between the end of the RREG command and the beginning of shifting data on DOUT: t6.
DIN
0001 0001
0000 0001
1st Command 2nd Command
Byte Byte
t6
DOUT
MUX
ADCON
Data
Byte
Data
Byte
Figure 33. RREG Command Example: Read Two Registers Starting from Register 01h (multiplexer)
WREG: Write to Register
Description: Write to the registers starting with the register specified as part of the command. The number of registers that
will be written is one plus the value of the second byte in the command.
1st Command Byte: 0101 rrrr where rrrr is the address to the first register to be written.
2nd Command Byte: 0000 nnnn where nnnn is the number of bytes to be written – 1.
Data Byte(s): data to be written to the registers.
DIN
0101 0011
0000 0001 DRATE Data
IO Data
1st Command 2nd Command
Byte Byte
Data
Byte
Data
Byte
Figure 34. WREG Command Example: Write Two Registers Starting from 03h (DRATE)
SELFCAL: Self Offset and Gain Calibration
Description: Performs a self offset and self gain calibration. The Offset Calibration Register (OFC) and Full-Scale
Calibration Register (FSC) are updated after this operation. DRDY goes high at the beginning of the calibration. It goes
low after the calibration completes and settled data is ready. Do not send additional commands after issuing this command
until DRDY goes low indicating that the calibration is complete.
SELFOCAL: Self Offset Calibration
Description: Performs a self offset calibration. The Offset Calibration Register (OFC) is updated after this operation. DRDY
goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready. Do not
send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete.
SELFGCAL: Self Gain Calibration
Description: Performs a self gain calibration. The Full-Scale Calibration Register (FSC) is updated with new values after
this operation. DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled
data is ready. Do not send additional commands after issuing this command until DRDY goes low indicating that the
calibration is complete.
36
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SYSOCAL: System Offset Calibration
Description: Performs a system offset calibration. The Offset Calibration Register (OFC) is updated after this operation.
DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready.
Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is
complete.
SYSGCAL: System Gain Calibration
Description: Performs a system gain calibration. The Full-Scale Calibration Register (FSC) is updated after this operation.
DRDY goes high at the beginning of the calibration. It goes low after the calibration completes and settled data is ready.
Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is
complete.
SYNC: Synchronize the A/D Conversion
Description: This command synchronizes the A/D conversion. To use, first shift in the command. Then shift in the
WAKEUP command. Synchronization occurs on the first CLKIN rising edge after the first SCLK used to shift in the
WAKEUP command.
1111 1100
(SYNC)
0000 0000
(WAKEUP)
DIN
•••
• ••
•••
SCLK
•• •
CLKIN
Synchronization Occurs Here
Figure 35. SYNC Command Sequence
STANDBY: Standby Mode / One-Shot Mode
Description: This command puts the ADS1255/6 into a low-power Standby mode. After issuing the STANDBY command,
make sure there is no more activity on SCLK while CS is low, as this will interrupt Standby mode. If CS is high, SCLK activity
is allowed during Standby mode. To exit Standby mode, issue the WAKEUP command. This command can also be used
to perform single conversions (see One-Shot Mode section) .
1111 1101
(STANDBY)
0000 0000
(WAKEUP)
DIN
SCLK
Normal Mode
Standby Mode
Normal Mode
Figure 36. STANDBY Command Sequence
WAKEUP: Complete Synchronization or Exit Standby Mode
Description: Used in conjunction with the SYNC and STANDBY commands. Two values (all zeros or all ones) are
available for this command.
RESET: Reset Registers to Default Values
Description: Returns all registers except the CLK0 and CLK1 bits in the ADCON register to their default values.
This command will also stop the Read Continuous mode: in this case, issue the RESET command after DRDY goes low.
37
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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