ADS774KU [BB]
Microprocessor-Compatible Sampling CMOS ANALOG-to-DIGITAL CONVERTER; 微处理器兼容采样CMOS模拟数字转换器
| 型号： | ADS774KU |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Microprocessor-Compatible Sampling CMOS ANALOG-to-DIGITAL CONVERTER |
| 文件： | 总13页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS774
®
ADS774
ADS774
ADS774
Microprocessor-Compatible Sampling
CMOS ANALOG-to-DIGITAL CONVERTER
FEATURES
DESCRIPTION
● REPLACES ADC574, ADC674 AND ADC774
The ADS774 is a 12-bit successive approximation
analog-to-digital converter using an innovative
capacitor array (CDAC) implemented in low-power
CMOS technology. This is a drop-in replacement for
ADC574, ADC674, and ADC774 models in most
applications, with internal sampling, much lower power
consumption, and the ability to operate from a single
+5V supply.
FOR NEW DESIGNS
● COMPLETE SAMPLING A/D WITH
REFERENCE, CLOCK AND
MICROPROCESSOR INTERFACE
● FAST ACQUISITION AND CONVERSION:
8.5µs max OVER TEMPERATURE
● ELIMINATES EXTERNAL SAMPLE/HOLD
The ADS774 is complete with internal clock, micro-
processor interface, three-state outputs, and internal
scaling resistors for input ranges of 0V to +10V, 0V to
+20V, ±5V, or ±10V. The maximum throughput time
is 8.5µs over the full operating temperature range,
including both acquisition and conversion.
IN MOST APPLICATIONS
● GUARANTEED AC AND DC PERFOR-
MANCE
● SINGLE +5V SUPPLY OPERATION
● LOW POWER: 120mW max
Complete user control over the internal sampling func-
tion facilitates elimination of external sample/hold
amplifiers in most existing designs.
● PACKAGE OPTIONS: 0.6" and 0.3" DIPs,
SOIC
The ADS774 requires +5V, with –15V optional. No
+15V supply is required. Available packages include
0.3" or 0.6" wide 28-pin plastic DIP and 28-pin SOICs.
Status
Control
Inputs
Control Logic
Bipolar Offset
CDAC
Clock
Parallel
Data
Output
–
20V Range
10V Range
Successive
Approximation
Register
+
2.5V Reference
Input
Comparator
2.5V Reference
Output
2.5V
Reference
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
FAXLine: (800) 548-6133 (US/Canada Only)
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1991 Burr-Brown Corporation
PDS-1109F
Printed in U.S.A. July, 1995
SPECIFICATIONS
ELECTRICAL
At TA = TMIN to TMAX , VDD = +5V, VEE = –15V to +5V, sampling frequency of 117kHz, fIN = 10kHz; unless otherwise specified.
ADS774JE, JP, JU
TYP
ADS774KE, KP, KU
TYP
PARAMETER
MIN
MAX
MIN
MAX
UNITS
RESOLUTION
INPUTS
12
✻
Bits
ANALOG
Voltage Ranges: Unipolar
Bipolar
0 to +10, 0 to +20
V
V
±5, ±10
Impedance:
0 to +10V, ±5V
±10V, 0V to +20V
8.5
35
12
50
✻
✻
✻
✻
kΩ
kΩ
DIGITAL (CE, CS, R/C, AO, 12/8)
Voltages: Logic 1
Logic 0
Current
Capacitance
+2.0
–0.5
–5
+5.5
+0.8
+5
✻
✻
✻
✻
✻
✻
V
V
µA
pF
0.1
5
✻
✻
TRANSFER CHARACTERISTICS
DC ACCURACY
At +25°C
Linearity Error
Unipolar Offset Error (adjustable to zero)
Bipolar Offset Error (adjustable to zero)
±1
±2
±10
±0.25
±1/2
✻
±4
✻
LSB
LSB
LSB
(1)
(2)
Full-Scale Calibration Error
% of FS
(adjustable to zero)
No Missing Codes Resolution
TMIN to TMAX
12
12
Bits
(3)
Linearity Error
Full-Scale Calibration Error
Unipolar Offset
±1
±0.47
±4
±1/2
±0.37
±3
LSB
% of FS
LSB
Bipolar Offset
±12
±5
LSB
No Missing Codes Resolution
12
73
12
76
Bits
(4)
AC ACCURACY
Spurious Free Dynamic Range
Total Harmonic Distortion
Signal-to-Noise Ratio
Signal-to-(Noise + Distortion) Ratio
Intermodulation Distortion
(FIN1 = 20kHz, FIN2 = 23kHz)
78
–77
72
71
–75
✻
✻
✻
✻
✻
dB
dB
dB
dB
–72
–75
69
68
71
70
(5)
TEMPERATURE COEFFICIENTS
Unipolar Offset
Bipolar Offset
Full-Scale Calibration
±1
±2
±12
✻
✻
✻
ppm/°C
ppm/°C
ppm/°C
POWER SUPPLY SENSITIVITY
Change in Full-Scale Calibration(6)
+4.75V < VDD < +5.25V
Max Change
±1/2
✻
LSB
CONVERSION TIME (Including Acquisition Time)
tAQ + tC at 25°C:
8-Bit Cycle
12-Bit Cycle
5.5
7.5
8
5.9
8
8.5
✻
✻
✻
✻
✻
✻
µs
µs
µs
12-Bit Cycle, TMIN to TMAX
:
SAMPLING DYNAMICS
Sampling Rate at 25°C
125
117
✻
✻
kHz
kHz
T
MIN to TMAX
Aperture Delay, tAP
With VEE = +5V
With VEE = 0V to –15V
20
1.6
✻
✻
ns
µs
Aperture Uncertainty (Jitter)
With VEE = +5V
With VEE = 0V to –15V
Settling time to 0.01% for
Full-Scale Input Change
300
10
1.4
✻
✻
✻
ps, rms
ns, r ms
µs
®
ADS774
2
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = TMIN to TMAX , VDD = +5V, VEE = –15V to +5V, sampling frequency of 117kHz, fIN = 10kHz; unless otherwise specified.
ADS774JE, JP, JU
TYP
ADS774KE, KP, KU
PARAMETER
OUTPUTS
MIN
MAX
MIN
TYP
MAX
UNITS
DIGITAL (DB11 - DB0, STATUS)
Output Codes: Unipolar
Bipolar
Unipolar Straight Binary (USB)
Bipolar Offset Binary (BOB)
Logic Levels: Logic 0 (ISINK = 1.6mA)
Logic 1 (ISOURCE = 500µA)
Leakage, Data Bits Only, High-Z State
Capacitance
+0.4
✻
✻
V
V
µA
pF
+2.4
–5
✻
✻
0.1
5
+5
✻
✻
INTERNAL REFERENCE VOLTAGE
Voltage
Source Current Available for External Loads
+2.4
0.5
+2.5
+2.6
✻
✻
✻
✻
V
mA
POWER SUPPLY REQUIREMENTS
(7)
Voltage: VEE
–16.5
+4.5
VDD
+5.5
✻
✻
✻
✻
V
V
mA
mA
VDD
Current: IEE
IDD
(7)
(VEE = –15V)
–1
+15
✻
✻
+24
120
✻
✻
Power Dissipation (TMIN to TMAX
(VEE = 0V to +5V)
)
75
✻
mW
TEMPERATURE RANGE
Specification
Operating:
0
–40
–65
+70
+85
+150
✻
✻
✻
✻
✻
✻
°C
°C
°C
Storage Temperature Range
✻ Same specification as ADS774JE, JP, JU.
NOTES: (1) With fixed 50Ω resistor from REF OUT to REF IN. This parameter is also adjustable to zero at +25°C. (2) FS in this specification table means Full Scale
Range. That is, for a ±10V input range, FS means 20V; for a 0 to +10V range, FS means 10V. (3) Maximum error at TMIN and TMAX. (4) Based on using VEE
=
+5V, which is the Control Mode. See the section "S/H Control Mode and ADC774 Emulation Mode." (5) Using internal reference. (6) This is worst case change
in accuracy from accuracy with a +5V supply. (7) VEE is optional, and is only used to set the mode for the internal sample/hold. When VEE = –15V, IEE = –1mA
typ; when VEE = 0V, IEE = ±5µA typ; when VEE = +5V, IEE = +167µA typ.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
ADS774
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
VEE to Digital Common....................................................... +VDD to –16.5V
VDD to Digital Common .............................................................. 0V to +7V
Analog Common to Digital Common .................................................... ±1V
Control Inputs (CE, CS, AO, 12/8, R/C)
to Digital Common .................................................. –0.5V to VDD +0.5V
Analog Inputs (Ref In, Bipolar Offset, 10VIN
)
to Analog Common ...................................................................... ±16.5V
20VIN to Analog Common .................................................................. ±24V
Ref Out.......................................................... Indefinite Short to Common,
Momentary Short to VDD
Max Junction Temperature ............................................................ +165°C
Power Dissipation ........................................................................ 1000mW
Lead Temperature (soldering,10s) ................................................. +300°C
Thermal Resistance, θJA : Plastic DIPs ........................................ 100°C/W
SOIC ................................................... 100°C/W
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
TEMPERATURE
LINEARITY
ERROR
PACKAGE DRAWING
NUMBER(2)
PRODUCT
SINAD(1)
RANGE
PACKAGE
ADS774JE
ADS774KE
ADS774JP
ADS774KP
ADS774JU
ADS774KU
68dB
70dB
68dB
70dB
68dB
70dB
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
±1LSB
±1/2LSB
±1LSB
±1/2LSB
±1LSB
28-Pin 0.3" Plastic DIP
28-Pin 0.3" Plastic DIP
28-Pin 0.6" Plastic DIP
28-Pin 0.6" Plastic DIP
28-Lead SOIC
246
246
215
215
217
217
±1/2LSB
28-Lead SOIC
NOTES: (1) SINAD is Signal-to-(Noise + Distortion) expressed in dB. (2) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-
Brown IC Data Book.
CONNECTION DIAGRAM
+5VDC Supply
(VDD
Power-Up Reset
1
28
27
STATUS
)
–
12/8
2
3
4
5
6
DB11 (MSB)
Control
Logic
CS
AO
26 DB10
Clock
25
24
DB9
DB8
–
R/C
CE
23
DB7
22 DB6
21 DB5
NC*
7
8
12
Bits
2.5V Ref
Out
2.5V
Reference
12 Bits
Analog
Common
20
19 DB3
18
9
DB4
2.5V Ref
In
10
VEE 11
DB2
17 DB1
Bipolar 12
Offset
–
+
10V Range 13
16 DB0 (LSB)
CDAC
20V Range
14
15 Digital
Common
*Not Internally Connected
®
ADS774
4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = VEE = +5V; Bipolar ±10V Input Range; sampling frequency of 110kHz; unless otherwise specified. All plots use 4096 point FFTs.
SIGNAL/(NOISE + DISTORTION) vs
FREQUENCY SPECTRUM (±10V, 2kHz Input)
INPUT FREQUENCY AND AMBIENT TEMPERATURE
0
–20
–40
–60
–80
75
S/(N + D) = 72.6dB
THD = –93.5dB
SNR = 72.6dB
–55°C
70
65
+25°C
+125°C
–100
–120
0
10
20
30
40
50 55
0.1
1
10
100
Input Frequency (kHz)
Input Frequency (kHz)
FREQUENCY SPECTRUM (±10V, 20kHz Input)
FREQUENCY SPECTRUM (±1V, 20kHz Input)
0
–20
–40
–60
–80
0
S/(N + D) = 70.6dB
THD = –77.5dB
SNR = 71.5dB
S/(N + D) = 53.1dB
THD = –74.2dB
–20
–40
–60
–80
–100
–120
–100
–120
0
10
20
30
40
50 55
0
10
20
30
40
50 55
Input Frequency (kHz)
Input Frequency (kHz)
POWER SUPPLY REJECTION
vs SUPPLY RIPPLE FREQUENCY
SPURIOUS FREE DYNAMIC RANGE, SNR AND THD
vs INPUT FREQUENCY
80
60
40
100
90
Spurious Free Dynamic Range
Total Harmonic Distortion (THD)
Signal-to-Noise Ratio (SNR)
80
70
60
20
10
10
100
1k
10k
100k
1M
10M
0.1
1
10
100
Supply Ripple Frequency (Hz)
Input Frequency (kHz)
®
5
ADS774
latch S1 in position “R” or “G”. Similarly, the second
approximation is made by connecting S2 to the reference and
S3 to GND, and latching S2 according to the output of the
comparator. After three successive approximation steps have
been made the voltage level at the comparator will be within
1/2LSB of GND, and a digital word which represents the
analog input can be determined from the positions of S1, S2
and S3.
THEORY OF OPERATION
In the ADS774, the advantages of advanced CMOS technol-
ogy—high logic density, stable capacitors, precision analog
switches—and Burr-Brown’s state of the art laser trimming
techniques are combined to produce a fast, low power
analog-to-digital converter with internal sample/hold.
The charge-redistribution successive-approximation circuitry
converts analog input voltages into digital words.
A simple example of a charge-redistribution A/D converter
with only 3 bits is shown in Figure 1.
OPERATION
BASIC OPERATION
Figure 2 shows the minimum connections required to oper-
ate the ADS774 in a basic ±10V range in the Control Mode
(discussed in detail in a later section.) The falling edge of a
Convert Command (a pulse taking pin 5 LOW for a mini-
mum of 25ns) both switches the ADS774 input to the hold
state and initiates the conversion. Pin 28 (STATUS) will
output a HIGH during the conversion, and falls only after the
conversion is completed and the data has been latched on the
data output pins (pins 16 to 27.) Thus, the falling edge of
STATUS on pin 28 can be used to read the data from the
conversion. Also, during conversion, the STATUS signal
puts the data output pins in a High-Z state and inhibits the
input lines. This means that pulses on pin 5 are ignored, so
that new conversions cannot be initiated during the conver-
sion, either as a result of spurious signals or to short-cycle
the ADS774.
Analog
Input
Comparator
SC
L
o
g
i
4C
2C
C
Out
Signal
S
c
S1
G
S2
G
S3
G
R
R
R
+
–
Reference
Input
FIGURE 1. 3-Bit Charge Redistribution A/D.
INPUT SCALING
Precision laser-trimmed scaling resistors at the input divide
standard input ranges (0V to +10V, 0V to +20V, ±5V or
±10V) into levels compatible with the CMOS characteristics
of the internal capacitor array.
The ADS774 will begin acquiring a new sample as soon as
the conversion is completed, even before the STATUS
output falls, and will track the input signal until the next
conversion is started. The ADS774 is designed to complete
a conversion and accurately acquire a new signal in 8.5µs
max over the full operating temperature range, so that
conversions can take place at a full 117kHz.
SAMPLING
While sampling, the capacitor array switch for the MSB
capacitor (S1) is in position “S”, so that the charge on the
MSB capacitor is proportional to the voltage level of the
analog input signal. The remaining array switches (S2 and
S3) are set to position “G”. Switch SC is closed, setting the
comparator input offset to zero.
CONTROLLING THE ADS774
The Burr-Brown ADS774 can be easily interfaced to most
microprocessor systems and other digital systems. The
microprocessor may take full control of each conversion, or
the converter may operate in a stand-alone mode, controlled
only by the R/C input. Full control consists of selecting an
8- or 12-bit conversion cycle, initiating the conversion, and
reading the output data when ready—choosing either 12 bits
all at once, or the 8 MSB bits followed by the 4 LSB bits in
a left-justified format. The five control inputs (12/8, CS, A0,
R/C, and CE) are all TTL/CMOS-compatible. The functions
of the control inputs are described in Table II. The control
function truth table is shown in Table III.
CONVERSION
When a conversion command is received, switch S1 is
opened to trap a charge on the MSB capacitor proportional
to the analog input level at the time of the sampling com-
mand, and switch SC is opened to float the comparator input.
The charge trapped in the capacitor array can now be moved
between the three capacitors in the array by connecting
switches S1, S2, and S3 to positions “R” (to connect to the
reference) or “G” (to connect to GND), thus changing the
voltage generated at the comparator input.
STAND-ALONE OPERATION
For stand-alone operation, control of the converter is accom-
plished by a single control line connected to R/C. In this
mode CS and A0 are connected to digital common and CE
and 12/8 are connected to +5V. The output data are
During the first approximation, the MSB capacitor is con-
nected through switch S1 to the reference, while switches S2
and S3 are connected to GND. Depending on whether the
comparator output is HIGH or LOW, the logic will then
®
ADS774
6
Status
Output
+5V
10µF
1
2
28
27 DB11 (MSB)
26 DB10
25 DB9
24 DB8
23 DB7
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
16 DB0 (LSB)
15
3
4
Convert Command
5
+5V
6
7
NC*
ADS774
8
9
50Ω
10
11
12
13
14
(1)
50Ω
Leave Unconnected
±10V
Analog
Input
*Not internally connected
NOTE: (1) Connect to GND or VEE for
Emulation Mode. Connect to +5V for
Control Mode.
FIGURE 2. Basic ±10V Operation.
presented as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do not
require full bus interface capability.
following an 8-bit conversion, the 4LSBs (DB0-DB3) will
be LOW (logic 0). A0 is latched because it is also involved
in enabling the output buffers. No other control inputs are
latched.
Conversion is initiated by a HIGH-to-LOW transition of
R/C. The three-state data output buffers are enabled when
R/C is HIGH and STATUS is LOW. Thus, there are two
possible modes of operation; data can be read with either a
positive pulse on R/C, or a negative pulse on STATUS. In
either case the R/C pulse must remain LOW for a minimum
of 25ns.
CONVERSION START
The converter initiates a conversion based on a transition
occurring on any of three logic inputs (CE, CS, and R/C) as
shown in Table III. Conversion is initiated by the last of the
three to reach the required state and thus all three may be
dynamically controlled. If necessary, all three may change
state simultaneously, and the nominal delay time is the same
regardless of which input actually starts the conversion. If it
is desired that a particular input establish the actual start of
conversion, the other two should be stable a minimum of
50ns prior to the transition of the critical input. Timing
relationships for start of conversion timing are illustrated in
Figure 5. The specifications for timing are contained in
Table V.
Figure 3 illustrates timing with an R/C pulse which goes
LOW and returns HIGH during the conversion. In this case,
the three-state outputs go to the high-impedance state in
response to the falling edge of R/C and are enabled for
external access of the data after completion of the conver-
sion.
Figure 4 illustrates the timing when a positive R/C pulse is
used. In this mode the output data from the previous conver-
sion is enabled during the time R/C is HIGH. A new
conversion is started on the falling edge of R/C, and the
three-state outputs return to the high-impedance state until
the next occurrence of a HIGH R/C pulse. Timing specifica-
tions for stand-alone operation are listed in Table IV.
The STATUS output indicates the current state of the con-
verter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely termi-
nated or restarted. However, if A0 changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of A0, possibly resulting in
an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the A0 input, which is latched upon receipt of a conver-
sion start transition (described below). If A0 is latched
HIGH, the conversion continues for 8 bits. The full 12-bit
conversion will occur if A0 is LOW. If all 12 bits are read
®
7
ADS774
Binary (BIN) Output
Input Voltage Range and LSB Values
Analog Input Voltage Range
Defined As:
±10V
±5V
0V to +10V
0V to +20V
One Least Significant Bit
(LSB)
FSR
2n
20V
2n
10V
2n
10V
2n
20V
2n
n = 8
n = 12
78.13mV
4.88mV
39.06mV
2.44mV
39.06mV
2.44mV
78.13mV
4.88mV
Output Transition Values
FFEH to FFFH
7FFFH to 800H
+ Full-Scale Calibration
Midscale Calibration (Bipolar Offset)
Zero Calibration ( – Full-Scale Calibration)
+10V – 3/2LSB
0V – 1/2LSB
–10V + 1/2LSB
+5V – 3/2LSB
0V – 1/2LSB
–5V + 1/2LSB
+10V – 3/2LSB
+5V – 1/2LSB
0V +1/2LSB
+20V – 3/2LSB
+10V – 1/2LSB
0V +1/2LSB
000H to 001H
TABLE I. Input Voltages, Transition Values, and LSB Values.
DESIGNATION
DEFINITION
FUNCTION
CE (Pin 6)
Chip Enable
(active high)
Must be HIGH (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
conversion.
CS (Pin 3)
R/C (Pin 5)
Chip Select
(active low)
Must be LOW (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a
conversion.
Read/Convert
(“1” = read)
Must be LOW (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion.
Must be HIGH (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
(“0” = convert)
AO (Pin 4)
Byte Address
Short Cycle
In the start-convert mode, AO selects 8-bit (AO = “1”) or 12-bit (AO = “0”) conversion mode. When reading
output data in two 8-bit bytes, AO = “0” accesses 8 MSBs (high byte) and AO = “1” accesses 4 LSBs and
trailing “0s” (low byte).
12/8 (Pin 2)
Data Mode Select
(“1” = 12 bits)
(“0” = 8 bits)
When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the
MSBs or LSBs as determined by the AO line.
TABLE II. Control Line Functions.
CE
CS
R/C
12/8
AO
OPERATION
0
X
↑
X
1
0
0
↓
X
X
0
0
0
0
↓
↓
X
X
X
X
X
X
X
X
1
X
X
0
1
0
1
0
1
X
0
1
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable 8 MSBs only
Enable 4 LSBs plus 4
trailing zeroes
↑
1
1
1
1
1
1
1
↓
0
0
0
0
0
1
1
1
0
0
TABLE III. Control Input Truth Table.
READING OUTPUT DATA
When 12/8 is LOW, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of A0 during the read cycle. When A0 is
LOW, the byte addressed contains the 8MSBs. When A0 is
HIGH, the byte addressed contains the 4LSBs from the
conversion followed by four logic zeros which have been
forced by the control logic. The left-justified formats of the
two 8-bit bytes are shown in Figure 7. Connection of the
ADS774 to an 8-bit bus for transfer of the data is illustrated
in Figure 8. The design of the ADS774 guarantees that the
A0 input may be toggled at any time with no damage to the
converter; the outputs which are tied together in Figure 8
cannot be enabled at the same time. The A0 input is usually
driven by the least significant bit of the address bus, allow-
ing storage of the output data word in two consecutive
memory locations.
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C HIGH, STATUS
LOW, CE HIGH, and CS LOW. Upon satisfaction of these
conditions the data lines are enabled according to the state of
inputs 12/8 and A0. See Figure 6 and Table V for timing
relationships and specifications.
In most applications the 12/8 input will be hard-wired in
either the HIGH or LOW condition, although it is fully TTL
and CMOS-compatible and may be actively driven if de-
sired. When 12/8 is HIGH, all 12 output lines (DB0-DB11)
are enabled simultaneously for full data word transfer to a
12-bit or 16-bit bus. In this situation the A0 state is ignored
when reading the data.
®
ADS774
8
tHRL
R/C
R/C
tHRH
tDS
tDS
STATUS
tCONVERSION
tDDR
tHDR
STATUS
tCONVERSION
tHDR
tHS
High-Z
DB11-DB0
High-Z-State
Data Valid
High-Z-State
DB11-DB0
Data Valid
Data Valid
FIGURE 3. R/C Pulse Low—OutputsEnabled AfterConver-
sion.
FIGURE 4. R/C Pulse High — Outputs Enabled Only While
R/C Is High.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tHRL
tDS
tHDR
tHRH
tDDR
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
High R/C Pulse Width
Data Access Time
25
ns
ns
ns
ns
ns
200
25
100
150
TABLE IV. Stand-Alone Mode Timing. (TA = TMIN to TMAX ).
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
tDSC
STS delay from CE
CE Pulse width
CS to CE setup
CS low during CE high
R/C to CE setup
R/C low during CE high
AO to CE setup
60
30
20
20
0
200
ns
ns
ns
ns
ns
ns
ns
ns
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
50
50
50
50
50
0
20
AO valid during CE high
50
20
Read Mode
tDD
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
75
35
100
0
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
25
50
0
50
0
0
50
75
AO to CE setup
25
CS valid after CE low
R/C high after CE low
AO valid after CE low
STATUS delay after data valid
150
375
TABLE V. Timing Specifications, Fully Controlled Operation. (TA = TMIN to TMAX ).
CE
tHEC
CE
CS
tSSR
tHSR
tSSC
CS
tHRR
tHSC
R/C
R/C
tSSR
tHRC
tSRC
A
0
A
0
tSAC
tSAR
tHAR
Status
tHAC
tDSC
Status
tX*
tHS
tHD
High Impedance
DB11-DB0
DB11-DB0
High-Z
tDD
Data Valid
* tX includes tAQ + tC in ADC774 Emulation Mode,
tC only in S/H Control Mode.
tHL
FIGURE 5. Conversion Cycle Timing.
FIGURE 6. Read Cycle Timing.
®
9
ADS774
Word 1
Word 2
DB4 DB3
DB0
Processor
Converter
DB7
DB6
DB5
DB9
DB4
DB8
DB3
DB7
DB2
DB6
DB1
DB5
DB0
DB4
DB7
DB3
DB6
DB2
DB5
DB1
DB2
0
DB1
0
DB0
0
DB11 DB10
0
FIGURE 7. 12-Bit Data Format for 8-Bit Systems.
STATUS 28
2
4
12/8
AO
DB11 (MSB) 27
26
25
24
23
22
AO
Address
Bus
Data
Bus
ADS774
21
20
19
18
17
DB0 (LSB) 16
Digital Common 15
FIGURE 8. Connection to an 8-Bit Bus.
S/H CONTROL MODE
AND ADC774 EMULATION MODE
tion is made about the input level after the convert command
arrives, since the input signal is sampled and conversion
begins immediately after the convert command. This means
that a convert command can also be used to switch an input
multiplexer or change gains on a programmable gain ampli-
fier, allowing the input signal to settle before the next
acquisition at the end of the conversion. Because aperture
jitter is minimized in the Control Mode, a high input fre-
quency can be converted without an external sample/hold.
The Emulation Mode allows the ADS774 to be dropped into
most existing ADC774 sockets without changes to other
system hardware or software. In existing sockets, the analog
input is held stable during the conversion period so that
accurate conversions can proceed, but the input can change
rapidly at any time before the conversion starts. The Emula-
tion Mode uses the stability of the analog input during the
conversion period to both acquire and convert in a maximum
of 8µs (8.5µs over temperature.) In fact, system throughput
can be increased, since the input to the ADS774 can start
slewing before the end of a conversion (after the acquisition
time), which is not possible with existing ADC774s.
In the Emulation Mode, a delay time is introduced between
the convert command and the start of conversion to allow the
ADS774 enough time to acquire the input signal before
converting. This increases the effective aperture delay time
from 0.02µs to 1.6µs, but allows the ADS774 to replace the
ADC774 in most circuits without additional changes. In
designs where the input to the ADS774 is changing rapidly
in the 200ns prior to a convert command, system perfor-
mance may be enhanced by delaying the convert command
by 200ns.
The Control Mode is provided to allow full use of the
internal sample/hold, eliminating the need for an external
sample/hold in most applications. As compared with sys-
tems using separate sample/hold and A/D, the ADS774 in
the Control Mode also eliminates the need for one of the
control signals, usually the convert command. The com-
mand that puts the internal sample/hold in the hold state
also initiates a conversion, reducing timing constraints in
many systems.
When using the ADS774 in the Emulation Mode to replace
existing converters in current designs, a sample/hold ampli-
fier often precedes the converter. In these cases, no addi-
tional delay in the convert command will be needed. The
existing sample/hold will not be slewing excessively when
going from the sample mode to the hold mode prior to a
conversion.
The basic difference between these two modes is the
assumptions about the state of the input signal both before
and during the conversion. The differences are shown in
Figure 9 and Table VI. In the Control Mode, it is assumed
that during the required 1.4µs acquisition time the signal is
not changing faster than the ADS774 can track. No assump-
In both modes, as soon as the conversion is completed the
internal sample/hold circuit immediately begins slewing to
track the input signal.
®
ADS774
10
In particular, the unused input pin should not be connected
to any capacitive load, including high impedance switches.
Even a few pF on the unused pin can degrade acquisition
time.
INSTALLATION
LAYOUT PRECAUTIONS
Analog (pin 9) and digital (pin 15) commons are not con-
nected together internally in the ADS774, but should be
connected together as close to the unit as possible and to an
analog common ground plane beneath the converter on the
component side of the board. In addition, a wide conductor
pattern should run directly from pin 9 to the analog supply
common, and a separate wide conductor pattern from pin 15
to the digital supply common.
Coupling between analog input and digital lines should be
minimized by careful layout. For instance, if the lines must
cross, they should do so at right angles. Parallel analog and
digital lines should be separated from each other by a pattern
connected to common.
If external full scale and offset potentiometers are used, the
potentiometers and associated resistors should be as close as
possible to the ADS774.
If the single-point system common cannot be established
directly at the converter, pin 9 and pin 15 should still be
connected together at the converter. A single wide conductor
pattern then connects these two pins to the system common.
In either case, the common return of the analog input signal
should be referenced to pin 9 of the ADC. This prevents any
voltage drops that might occur in the power supply common
returns from appearing in series with the input signal.
POWER SUPPLY DECOUPLING
On the ADS774, +5V (to Pin 1) is the only power supply
required for correct operation. Pin 7 is not connected inter-
nally, so there is no problem in existing ADC774 sockets
where this is connected to +15V. Pin 11 (VEE) is only used
as a logic input to select modes of control over the sampling
function as described above. When used in an existing
ADC774 socket, the –15V on pin 11 selects the ADC774
Emulation Mode. Since pin 11 is used as a logic input, it is
immune to typical supply variations.
The speed of the ADS774 requires special caution regarding
whichever input pin is unused. For 10V input ranges, pin 14
(20V Range) must be unconnected, and for 20V input
ranges, pin 13 (10V Range) must be unconnected. In both
cases, the unconnected input should be shielded with ground
plane to reduce noise pickup.
S/H CONTROL MODE
(Pin 11 Connected to +5V)
ADC774 EMULATION MODE
(Pin 11 Connected to 0V to –15V)
SYMBOL
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
tAQ + tC
Throughput Time:
12-bit Conversions
8-bit Conversions
8
6
8.5
6.3
8
6
8.5
6.3
µs
µs
tC
Conversion Time:
12-bit Conversions
8-bit Conversions
Acquisition Time
Aperture Delay
6.4
4.4
1.4
20
6.4
4.4
1.4
1600
10
µs
µs
µs
ns
ns
tAQ
tAP
tJ
Aperture Uncertainty
0.3
TABLE VI. Conversion Timing, TMIN to TMAX
.
R/C
tC
tAP
Signal
Acquisition
Signal
Acquisition
S/H Control Mode
Pin 11 connected to +5V.
Conversion
tC
tAQ
tAP
ADC774 Emulation Mode*
Pin 11 connected to VEE or ground.
Signal
Acquisition
Signal
Acquisition
Conversion
tAQ
*In the ADC774 Emulation Mode, a convert command triggers a delay that
allows the ADS774 enough time to acquire the input signal before converting.
FIGURE 9. Signal Acquisition and Conversion Timing.
®
11
ADS774
connected either to Pin 9 (Analog Common) for unipolar
operation, or to Pin 8 (2.5V Ref Out), or the external
reference, for bipolar operation. Full-scale and offset adjust-
ments are described below.
+VCC
Unipolar
Offset
Adjust
Full-Scale
Adjust
R1
R2
100Ω
100kΩ
The input impedance of the ADS774 is typically 50kΩ in the
20V ranges and 12kΩ in the 10V ranges. This is signifi-
cantly higher than that of traditional ADC774 architectures,
reducing the load on the input source in most applications.
10 Ref In
ADS774
100kΩ
–VCC
2.5V
8
Ref Out
100Ω
R3
12 Bipolar Offset
INPUT STRUCTURE
10V
Range
Figure 12 shows the resistor divider input structure of the
ADS774. Since the input is driving a capacitor in the CDAC
during acquisition, the input is looking into a high imped-
ance node as compared with traditional ADC774 architec-
tures, where the resistor divider network looks into a com-
parator input node at virtual ground.
13
14
9
Analog
Input
20V
Range
To understand how this circuit works, it is necessary to
know that the input range on the internal sampling capacitor
is from 0V to +3.33V, and the analog input to the ADS774
must be converted to this range. Unipolar 20V range can be
used as an example of how the divider network functions. In
20V operation, the analog input goes into pin 14. Pin 13 is
left unconnected and pin 12 is connected to pin 9, analog
common. From Figure 12, it is clear that the input to the
capacitor array will be the analog input voltage on pin 14
divided by the resistor network (42kΩ + 42kΩ || 10.5kΩ). A
20V input at pin 14 is divided to 3.33V at the capacitor
array, while a 0V input at pin 14 gives 0V at the capacitor
array.
Analog
Common
FIGURE 10. Unipolar Configuration.
Full-Scale Adjust
R2
10 Ref In
100Ω
ADS774
2.5V
8
Ref Out
100Ω
R1
Bipolar
Offset
Adjust
12 Bipolar Offset
The main effect of the 10kΩ internal resistor on pin 12 is to
provide the same offset adjust response as that of traditional
ADC774 architectures without changing the external trimpot
values.
13
14
9
Analog
Input
10V
Range
20V
Range
SINGLE SUPPLY OPERATION
The ADS774 is designed to operate from a single +5V
supply, and handle all of the unipolar and bipolar input
ranges, in either the Control Mode or the Emulation Mode as
described above. Pin 7 is not connected internally. This is
Analog
Common
FIGURE 11. Bipolar Configuration.
The +5V supply should be bypassed with a 10µF tantalum
capacitor located close to the converter to promote noise-
free operations, as shown in Figure 2. Noise on the power
supply lines can degrade the converter’s performance. Noise
and spikes from a switching power supply are especially
troublesome.
42kΩ
Pin 14
20V Range
21kΩ
Pin 13
Capacitor
Array*
10V Range
21kΩ
RANGE CONNECTIONS
The ADS774 offers four standard input ranges: 0V to +10V,
0V to +20V, ±5V, or ±10V. Figures 10 and 11 show the
necessary connections for each of these ranges, along with
the optional gain and offset trim circuits. If a 10V input
range is required, the analog input signal should be con-
nected to pin 13 of the converter. A signal requiring a 20V
range is connected to pin 14. In either case the other pin of
the two is left unconnected. Pin 12 (Bipolar Offset) is
10.5kΩ
Pin 12
Bipolar
Offset
10kΩ
*10pF when sampling
FIGURE 12. ADS774 Input Structure.
®
ADS774
12
where +12V or +15V is supplied on traditional ADC774s.
Pin 11, the –12V or –15V supply input on traditional
ADC774s, is used only as a logic input on the ADS774.
There is a resistor divider internally on pin 11 to reduce that
input to a correct logic level within the ADS774, and this
resistor will add 10mW to 15mW to the power consumption
of the ADS774 when –15V is supplied to pin 11. To
minimize power consumption in a system, pin 11 can be
simply grounded (for Emulation Mode) or tied to +5V (for
Control Mode.)
If adjustment is required, connect the converter as shown in
Figure 10. Sweep the input through the end-point transition
voltage (0V + 1/2LSB; +1.22mV for the 10V range, +2.44mV
for the 20V range) that causes the output code to be DB0 ON
(HIGH). Adjust potentiometer R1 until DB0 is alternately
toggling ON and OFF with all other bits OFF. Then adjust
full scale by applying an input voltage of nominal full-scale
minus 3/2LSB, the value which should cause all bits to be
ON. This value is +9.9963V for the 10V range and +19.9927V
for the 20V range. Adjust potentiometer R2 until bits DB1-
DB11 are ON and DB0 is toggling ON and OFF.
There are no other modifications required for the ADS774 to
function with a single +5V supply.
CALIBRATION PROCEDURE—BIPOLAR RANGES
If external adjustments of full-scale and bipolar offset are
not required, replace the potentiometers in Figure 11 by
50Ω, 1% metal film resistors.
CALIBRATION
OPTIONAL EXTERNAL FULL-SCALE
AND OFFSET ADJUSTMENTS
If adjustments are required, connect the converter as shown
in Figure 11. The calibration procedure is similar to that
described above for unipolar operation, except that the offset
adjustment is performed with an input voltage which is
1/2LSB above the minus full-scale value (–4.9988V for the
±5V range, –9.9976V for the ±10V range). Adjust R1 for
DB0 to toggle ON and OFF with all other bits OFF. To
adjust full-scale, apply a DC input signal which is 3/2LSB
below the nominal plus full-scale value (+4.9963V for ±5V
range, +9.9927V for ±10V range) and adjust R2 for DB0 to
toggle ON and OFF with all other bits ON.
Offset and full-scale errors may be trimmed to zero using
external offset and full-scale trim potentiometers connected
to the ADS774 as shown in Figures 10 and 11 for unipolar
and bipolar operation.
CALIBRATION PROCEDURE—
UNIPOLAR RANGES
If external adjustments of full-scale and offset are not
required, replace R2 in Figure 10 with a 50Ω 1% metal film
resistor and connect pin 12 to pin 9, omitting the other
adjustment components.
®
13
ADS774
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