ADS7862YB/2K5 [BB]
ADC, Successive Approximation, 12-Bit, 2 Func, 2 Channel, Parallel, Word Access, CMOS, PQFP32, TQFP-32;
| 型号： | ADS7862YB/2K5 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | ADC, Successive Approximation, 12-Bit, 2 Func, 2 Channel, Parallel, Word Access, CMOS, PQFP32, TQFP-32 转换器 |
| 文件： | 总13页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADS7862
ADS7862
¤
For most current data sheet and other product
information, visit www.burr-brown.com
Dual 500kHz, 12-Bit, 2 + 2 Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS7862 is a dual 12-bit, 500kHz analog-to-
digital converter (A/D) with 4 fully differential input
channels grouped into two pairs for high speed simulta-
neous signal acquisition. Inputs to the sample-and-hold
amplifiers are fully differential and are maintained dif-
ferential to the input of the A/D converter. This provides
excellent common-mode rejection of 80dB at 50kHz
which is important in high noise environments.
● 4 INPUT CHANNELS
● FULLY DIFFERENTIAL INPUTS
● 2µs TOTAL THROUGHPUT PER CHANNEL
● GUARANTEED NO MISSING CODES
● PARALLEL INTERFACE
● 1MHz EFFECTIVE SAMPLING RATE
● LOW POWER: 40mW
The ADS7862 offers parallel interface and control in-
puts to minimize software overhead. The output data for
each channel is available as a 12-bit word. The ADS7862
is offered in an TQFP-32 package and is full specified
over the –40°C to +85°C operating range.
APPLICATIONS
● MOTOR CONTROL
● MULTI-AXIS POSITIONING SYSTEMS
● 3-PHASE POWER CONTROL
CH A0+
CH A0–
SAR
S/H
Amp
COMP
Interface
CDAC
A0
CLOCK
CS
CH A1+
Conversion
and
CH A1–
MUX
RD
Control
BUSY
CONVST
REFIN
Internal
2.5V
REFOUT
Reference
Output
Registers
Data Output
CH B0+
CH B0–
12
S/H
Amp
COMP
CDAC
CH B1+
CH B1–
MUX
SAR
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
Printed in U.S.A. May, 2000
PDS-1475B
SPECIFICATIONS
All specifications TMIN to TMAX, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
ADS7862Y
TYP
ADS7862YB
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
12
✻
Bits
ANALOG INPUT
Input Voltage Range-Bipolar
Absolute Input Range
VCENTER = Internal VREF at 2.5V
–VREF
–0.3
–0.3
+VREF
VCC + 0.3
VCC + 0.3
✻
✻
V
V
V
+IN
–IN
Input Capacitance
Input Leakage Current
15
±1
✻
✻
pF
µA
CLK = GND
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity
Integral Linearity Match
Differential Linearity
Bipolar Offset Error
Bipolar Offset Error Match
Positive Gain Error
Positive Gain Error Match
Negative Gain Error
Negative Gain Error Match
Common-Mode Rejection Ratio
12
✻
Bits
LSB
LSB
LSB
LSB
LSB
% of FSR
LSB
% of FSR
LSB
±0.75
0.5
±0.75
±0.75
±2
1
±0.5
✻
±0.5
±0.5
±1
✻
±1
±2
2
±0.5
1
±0.5
1
Referenced to REFIN
Referenced to REFIN
Referenced to REFIN
±3
3
±0.75
2
±0.75
2
±0.15
±0.15
±0.1
±0.1
At DC
80
80
120
±0.5
✻
✻
✻
✻
dB
dB
µVrms
LSB
VIN = ±1.25Vp-p at 50kHz
Noise
Power Supply Rejection Ratio
±2
✻
SAMPLING DYNAMICS
Conversion Time per A/D
Acquisition Time
1.75
0.25
✻
✻
µs
µs
Throughput Rate
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Small-Signal Bandwidth
500
✻
kHz
ns
ps
ps
MHz
3.5
100
50
✻
✻
✻
✻
40
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
Spurious Free Dynamic Range
Channel-to-Channel Isolation
VIN = ±2.5Vp-p at 100kHz
VIN = ±2.5Vp-p at 100kHz
VIN = ±2.5Vp-p at 100kHz
VIN = ±2.5Vp-p at 100kHz
75
71
–78
✻
✻
✻
dB
dB
dB
dB
–80
✻
✻
VOLTAGE REFERENCE
Internal
Internal Drift
2.475
2.5
±25
50
2.525
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
ppm/°C
µVp-p
mA
mV/µA
dB
V
µA
pF
Internal Noise
Internal Source Current
Internal Load Rejection
Internal PSRR
External Voltage Range
Input Current
2
0.005
65
2.5
0.05
5
1.2
2.6
1
✻
✻
Input Capacitance
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels: VIH
VIL
VOH
VOL
External Clock
Data Format
CMOS
✻
IIH = +5µA
IIL = +5µA
IOH = –500µA
IOL = 500µA
3.0
–0.3
3.5
+VDD + 0.3
0.8
✻
✻
✻
✻
✻
V
V
V
V
MHz
0.4
8
✻
✻
0.2
✻
Binary Two’s Complement
✻
POWER SUPPLY REQUIREMENTS
Power Supply Voltage, +V
Quiescent Current, +VA
4.75
5
5
25
5.25
8
40
✻
✻
✻
✻
✻
✻
✻
V
mA
mW
Power Dissipation
✻ Specifications same as ADS7862Y.
Theinformationprovidedhereinisbelievedtobereliable;however,BURR-BROWNassumesnoresponsibilityforinaccuraciesoromissions.BURR-BROWNassumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
ADS7862
2
PIN DESCRIPTIONS
PIN CONFIGURATION
PIN
NAME
DESCRIPTION
Top View
1
2
REFIN
Reference Input
REFOUT
+2.5V Reference Output. Connect directly to REFIN
(pin 1) when using internal reference.
32 31 30 29 28 27 26 25
3
4
AGND
+VA
Analog Ground
Analog Power Supply, +5VDC. Connect directly to
digital power supply (pin 24). Decouple to analog
ground with a 0.1µF ceramic capacitor and a 10µF
tantalum capacitor.
1
2
3
4
5
6
7
8
24 +VD
REFIN
REFOUT
AGND
+VA
23 DGND
22 A0
5
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BUSY
Data Bit 11, MSB
Data Bit 10
6
21 RD
ADS7862
7
Data Bit 9
20 CS
DB11
DB10
DB9
8
Data Bit 8
19 CLOCK
18 CONVST
17 BUSY
9
Data Bit 7
10
11
12
13
14
15
16
17
18
19
Data Bit 6
Data Bit 5
DB8
Data Bit 4
Data Bit 3
9
10 11 12 13 14 15 16
Data Bit 2
Data Bit 1
Data Bit 0, LSB
HIGH when a conversion is in progress.
CONVST Convert Start
ABSOLUTE MAXIMUM RATINGS
CLOCK
An external CMOS-compatible clock can be applied to
the CLOCK input to synchronize the conversion pro-
cess to an external source. The CLOCK pin controls
Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+VD + 0.3V)
REFIN ............................. –0.3V to (+VD + 0.3V)
Digital Inputs to DGND.......................................... –0.3V to (+VD + 0.3V)
Ground Voltage Differences: AGND, DGND ................................... ±0.3V
+VD to AGND ......................... –0.3V to +6V
Power Dissipation .......................................................................... 325mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
the sampling rate by the equation: CLOCK 16 • fSAMPLE
.
20
21
CS
RD
Chip Select
Synchronization pulse for the parallel output. During a
Read operation, the first falling edge selects the A
register and the second edge selects the B register,
A0, then controls whether input 0 or input 1 is read.
22
A0
On the falling edge of Convert Start, when A0 is LOW
Channel A0 and Channel B0 are converted and when
it is HIGH, Channel A1 and Channel B1 are converted.
During a Read operation, the first falling edge selects
the A register and the second edge selects the B of RD
register, A0, then controls whether input 0 or input 1 is
read.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
23
24
25
26
27
28
29
30
31
32
DGND
+VD
Digital Ground. Connect directly to analog ground (pin 3).
Digital Power Supply, +5VDC
CH B1+ Non-Inverting Input Channel B1
CH B1– Inverting Input Channel B1
CH B0+ Non-Inverting Input Channel B0
CH B0– Inverting Input Channel B0
CH A1– Inverting Input Channel A1
CH A1+ Non-Inverting Input Channel A1
CH A0– Inverting Input Channel A0
CH A0+ Non-Inverting Input Channel A0
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi-
cations.
®
ADS7862
3
PACKAGE/ORDERING INFORMATION
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
GAIN
ERROR
(%)
PACKAGE
DRAWING
NUMBER(1)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
ADS7862Y
ADS7862Y
ADS7862YB
ADS7862YB
±2
"
±1
"
±0.75
TQFP-32
351
"
351
"
–40°C to +85°C
A62
"
A62
"
ADS7862Y/250 Tape and Reel
ADS7862Y/2K5 Tape and Reel
ADS7862YB/250 Tape and Reel
ADS7862YB/2K5 Tape and Reel
"
±0.5
"
"
"
TQFP-32
–40°C to +85°C
"
"
NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked
on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices
per reel). Ordering 2500 pieces of ”ADS7862Y/2K5“ will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the
www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions.
BASIC OPERATION
1
2
3
4
5
6
7
8
REFIN
REFOUT
AGND
+VA
+VD 24
DGND 23
A0 22
+5V
Analog Supply
Address Select
Read Input
RD 21
+
+
ADS7862Y
10µF
0.1µF
DB11
DB10
DB9
CS 20
Chip Select
CLOCK 19
CONVST 18
BUSY 17
Clock Input
Conversion Start
Busy Output
DB8
®
ADS7862
4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.9kHz, –0.5dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 199.9kHz, –0.5dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
62.5
125
187.5
250
0
62.5
125
187.5
250
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
76
74
72
70
68
66
64
0.25
0.2
SNR
0.15
0.1
SINAD
0.05
0
SINAD
–0.05
–0.1
–0.15
–0.2
–0.25
SNR
1k
10k
100k
1M
–40
25
85
Input Frequency (Hz)
Temperature (°C)
CHANGE IN POSITIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
0.65
0.45
0.65
0.6
0.5
0.4
0.3
0.2
0.1
0
0.45
SFDR
0.25
0.25
0.05
0.05
–0.15
–0.35
–0.55
–0.75
–0.15
–0.35
–0.55
–0.75
THD
–40
25
85
–40
25
85
Temperature (°C)
150
Temperature (°C)
®
ADS7862
5
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
CHANGE IN NEGATIVE GAIN MATCH
CHANGE IN REFERENCE VOLTAGE
vs TEMPERATURE
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
2.51
2.505
2.5
0.2
0.18
0.16
0.14
0.12
0.1
2.495
2.49
0.08
0.06
0.04
0.02
0
2.485
–40
25
85
150
–40
25
Temperature (°C)
85
150
150
85
Temperature (°C)
CHANGE IN BIPOLAR ZERO
vs TEMPERATURE
CHANGE IN BPZ MATCH vs TEMPERATURE
0.75
0.5
1
0.75
0.5
B Channel
0.25
0
–0.25
–0.5
–0.75
A Channel
0.25
0
–40
25
85
Temperature (°C)
150
–40
25
Temperature (°C)
85
INTEGRAL LINEARITY ERROR vs CODE
Typical of All Four Channels
CHANGE IN CMRR vs TEMPERATURE
1
0.8
86
85
84
83
82
81
80
79
78
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
800
000
7FF
–40
–5
25
55
Hex BTC Code
Temperature (°C)
®
ADS7862
6
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
DIFFERENTIAL LINEARITY ERROR vs CODE
Typical of All Four Channels
INTEGRAL LINEARITY ERROR vs TEMPERATURE
Positive ILE
1
0.75
0.5
0.6
0.4
0.2
0.25
0
0
–0.2
–0.4
–0.6
–0.8
–0.25
–0.5
–0.75
–1
Negative ILE
800
000
7FF
–40
25
85
150
Hex BTC Code
Temperature (°C)
INTEGRAL LINEARITY ERROR MATCH
vs CODE CHANNEL A0/CHANNEL A1
(Same Converter, Different Channels)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
0.8
0.6
0.25
0.2
Positive DLE
0.15
0.1
0.4
0.2
0.05
0
0
–0.05
–0.1
–0.15
–0.2
–0.25
–0.2
–0.4
–0.6
–0.8
Negative DLE
–40
25
85
150
800
000
7FF
Temperature (°C)
Hex BTC Code
INTEGRAL LINEARITY ERROR MATCH
vs TEMPERATURE
CHANNEL A0/CHANNEL B0
(Different Converter, Different Channels)
INTEGRAL LINEARITY ERROR MATCH
vs CODE CHANNEL A0/CHANNEL B1
(Different Converter, Different Channels)
0.25
0.2
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
800
000
7FF
–40
25
85
150
Hex BTC Code
Temperature (°C)
®
ADS7862
7
REFERENCE
INTRODUCTION
Under normal operation, the REFOUT pin (pin 2) should be
directly connected to the REFIN pin (pin 1) to provide an
internal +2.5V reference to the ADS7862. The ADS7862
can operate, however, with an external reference in the range
of 1.2V to 2.6V for a corresponding full-scale range of 2.4V
to 5.2V.
The ADS7862 is a high speed, low power, dual 12-bit A/D
converter that operates from a single +5V supply. The input
channels are fully differential with a typical common-mode
rejection of 80dB. The part contains dual 2µs successive
approximation A/Ds, two differential sample-and-hold am-
plifiers, an internal +2.5V reference with REFIN and REFOUT
pins and a high speed parallel interface. There are four
analog inputs that are grouped into two channels (A and B)
selected by the A0 input (A0 LOW selects Channels A0 and
B0, while A0 HIGH selects Channels A1 and B1). Each
A/D converter has two inputs (A0 and A1 and B0 and B1)
that can be sampled and converted simultaneously, thus
preserving the relative phase information of the signals on
both analog inputs. The part accepts an analog input voltage
in the range of –VREF to +VREF, centered around the internal
+2.5V reference. The part will also accept bipolar input
ranges when a level shift circuit is used at the front end (see
Figure 7).
The internal reference of the ADS7862 is double-buffered.
If the internal reference is used to drive an external load, a
buffer is provided between the reference and the load ap-
plied to pin 2 (the internal reference can typically source
2mA of current—load capacitance should not exceed 100pF).
If an external reference is used, the second buffer provides
isolation between the external reference and the CDAC.
This buffer is also used to recharge all of the capacitors of
both CDACs during conversion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS7862: single-ended or differential (see Figures 1 and 2).
When the input is single-ended, the –IN input is held at the
common-mode voltage. The +IN input swings around the
same common voltage and the peak-to-peak amplitude is the
(common-mode +VREF) and the (common-mode –VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 3).
A conversion is initiated on the ADS7862 by bringing the
CONVST pin LOW for a minimum of 15ns. CONVST
LOW places both sample-and-hold amplifiers in the hold
state simultaneously and the conversion process is started on
both channels. The BUSY output will then go HIGH and
remain HIGH for the duration of the conversion cycle.
Depending on the status of the A0 pin, the data will either
reflect a conversion of Channel 0 (A0 LOW) or Channel 1
(A0 HIGH). The data can be read from the parallel output
bus following the conversion by bringing both RD and CS
LOW.
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or: (+IN) – (–IN).
The peak-to-peak amplitude of each input is ±1/2VREF around
this common voltage. However, since the inputs are 180° out
of phase, the peak-to-peak amplitude of the differential voltage
is +VREF to –VREF. The value of VREF also determines the
range of the voltage that may be common to both inputs (see
Figure 4).
Conversion time for the ADS7862 is 1.75µs when an 8MHz
external clock is used. The corresponding acquisition time is
0.25µs. To achieve maximum output rate (500kHz), the read
function can be performed immediately at the start of the
next conversion.
NOTE: This mode of operation is described in more detail
in the Timing and Control section of this data sheet.
SAMPLE-AND-HOLD SECTION
–VREF to +VREF
ADS7862
The sample-and-hold amplifiers on the ADS7862 allow the
A/Ds to accurately convert an input sine wave of full-scale
amplitude to 12-bit accuracy. The input bandwidth of the
sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the A/D even when
the A/D is operated at its maximum throughput rate of
500kHz. The typical small-signal bandwidth of the sample-
and-hold amplifiers is 40MHz.
peak-to-peak
Common
Voltage
Single-Ended Input
VREF
peak-to-peak
ADS7862
Common
VREF
Typical aperture delay time or the time it takes for the
ADS7862 to switch from the sample to the hold mode
following the CONVST pulse is 3.5ns. The average delta of
repeated aperture delay values is typically 50ps (also known
as aperture jitter). These specifications reflect the ability of
the ADS7862 to capture AC input signals accurately at the
exact same moment in time.
Voltage
peak-to-peak
Differential Input
FIGURE 1. Methods of Driving the ADS7862 Single-Ended
or Differential.
®
ADS7862
8
+IN
CM +VREF
+VREF
CM Voltage
–IN = CM Voltage
–VREF
t
CM –VREF
Single-Ended Inputs
+IN
+VREF
CM +1/2VREF
CM Voltage
–VREF
–IN
t
CM –1/2VREF
Differential Inputs
(IN+) + (IN–)
NOTES: Common-Mode Voltage (Differential Mode) =
Common-Mode Voltage (Single-Ended Mode) = IN–.
2
The maximum differential voltage between +IN and –IN of the ADS7862 is VREF. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
FIGURE 2. Using the ADS7862 in the Single-Ended and Differential Input Modes.
5
4
5
4
VCC = 5V
4.7
VCC = 5V
4.1
4.05
3
3
2.7
2.3
Single-Ended Input
Differential Input
2
2
0.90
1
1
0.9
0.3
0
0
–1
–1
1.2
2.52.6
3.0
1.2
1.0
1.5
2.0
2.52.6
3.0
1.0
1.5
2.0
VREF (V)
VREF (V)
FIGURE 3. Single-Ended Input: Common-Mode Voltage
Range vs VREF
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs VREF
.
.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, which
will change with both temperature and input voltage.
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (15pF) to a 12-bit settling
level within 2 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.
The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS7862 charges the inter-
nal capacitor array during the sampling period. After this
Care must be taken regarding the absolute analog input
voltage. The +IN input should always remain within the
range of GND – 300mV to VDD + 0.3V.
®
ADS7862
9
TRANSITION NOISE
1.4V
Figure 5 shows a histogram plot for the ADS7862 following
8,000 conversions of a DC input. The DC input was set at
output code 2046. All but one of the conversions had an
output code result of 2046 (one of the conversions resulted
in an output of 2047). The histogram reveals the excellent
noise performance of the ADS7862.
3kΩ
DATA
Test Point
100pF
CLOAD
8000
7000
6000
5000
4000
3000
2000
1000
0
VOH
VOL
DATA
tR
tF
Voltage Waveforms for DATA Rise and Fall Times tR, and tF.
FIGURE 6. Test Circuits for Timing Specifications.
2044
2045
2046
2047
2048
Code (decimal)
R1
FIGURE 5. Histogram of 8,000 Conversions of a DC Input.
4kΩ
+IN
–IN
OPA132
20kΩ
BIPOLAR INPUTS
Bipolar Input
The differential inputs of the ADS7862 were designed to
accept bipolar inputs (–VREF and +VREF) around the internal
reference voltage (2.5V), which corresponds to a 0V to 5V
input range with a 2.5V reference. By using a simple op amp
circuit featuring a single amplifier and four external resis-
tors, the ADS7862 can be configured to except bipolar
inputs. The conventional ±2.5V, ±5V, and ±10V input
ranges can be interfaced to the ADS7862 using the resistor
values shown in Figure 7.
ADS7862
R2
REFOUT (pin 2)
2.5V
BIPOLAR INPUT
R1
R2
±10V
±5V
±2.5V
1kΩ
2kΩ
4kΩ
5kΩ
10kΩ
20kΩ
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
TIMING AND CONTROL
The ADS7862 uses an external clock (CLOCK, pin 19)
which controls the conversion rate of the CDAC. With an
8MHz external clock, the A/D sampling rate is 500kHz
which corresponds to a 2µs maximum throughput time.
Three timing diagrams are used to explain the operation of
the ADS7862. Figure 8 shows the timing relationship be-
tween the CLOCK, CONVST (pin 18) and the conversion
tCKP
tCKH
tCKL
CLOCK
t3
CONVST
CONVERSION
MODE
SAMPLE
HOLD
CONVERT
NOTE: The ADS7862 will switch from the sample to the hold mode the instant CONVST goes LOW regardless of
the state of the external clock. The conversion process is initiated with the first rising edge of the external clock
following CONVST going LOW.
FIGURE 8. Conversion Mode.
®
ADS7862
10
mode. Figure 9, in conjunction with Table I, shows the basic
read/write functions of the ADS7862 and highlights all of
the timing specifications. Figure 10 shows a more detailed
description of initiating a conversion using CONVST. Fig-
ure 11 illustrates three consecutive conversions and, with the
accompanying text, describes all of the read and write
capabilities of the ADS7862.
first followed by Channel 1. Channel 1 can be converted
prior to Channel 0 if the user wishes by simply starting the
conversion process with the A0 pin at logic HIGH (Channel
1) followed by logic LOW (Channel 0).
TIMING SPECIFICATIONS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
DESCRIPTION
ANALOG INPUT
tCONV
tACQ
tCKP
tCKL
tCKH
t1
Conversion Time
Acquisition Time
1.75
0.25
5000
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
Full-Scale Input Span
–VREF to +VREF
Clock Period
125
40
40
0
Least Significant
Bit (LSB)
(–VREF to +VREF)/4096(2)
Clock LOW
BINARY CODE
HEX CODE
Clock HIGH
+Full Scale
Midscale
4.99878V
2.5V
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
CS to RD Setup Time
CS to RD Hold Time
t2
0
t3
CONVST LOW
15
30
Midscale – 1 LSB
–Full Scale
2.49878V
0V
t4
RD Pulse Width
t5
RD to Valid Data (Bus Access)
RD to HI-Z Delay (Bus Relinquish)
Time Between Conversion Reads
Address Setup Time
16
10
25
20
NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corre-
sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.
t6
t7
40
250
20
t8
TABLE I. Ideal Input Voltages and Output Codes.
t9
CONVST HIGH
t10
t11
t12
t13
tF
Address Hold Time
20
CONVST to BUSY Propagation Delay
CONVST LOW Prior to CLOCK Rising Edge
CONVST LOW After CLOCK Rising Edge
Data Fall Time
30
The Figure 11 timing diagram can be divided into three
sections: (a) initiating a conversion (n – 2), (b) starting a
second conversion (n – 1) while reading the data output from
the previous conversion (n – 2), and (c) starting a third
conversion (n) while reading both previous conversions
(n – 2 and n – 1). In this sequence, Channel 0 is converted
10
5
13
20
25
30
tR
Data Rise Time
CLOCK
1
2
3
4
5
14
15
16
1
2
3
4
5
14
15
16
tCONV
tACQ
t12 t13
CONVST
BUSY
A0
t3
t9
t11
Conversion n
Conversion n + 1
t10
t8
CS
t1
t2
t7
RD
t4
t5
t6
DATA
CHA1
CHB1
CHA0
CHB0
Conversion n – 1 Results
Conversion n Results
FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle.
®
ADS7862
11
tCKP
125ns
CLOCK
Cycle 1
Cycle 2
10ns
10ns
5ns
5ns
B
A
C
CONVST
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion.
SECTION A
SECTION B
SECTION C
1
16
1
16
1
CLOCK
CONVST
A0
min 250ns
min 250ns
A0 = 0 Conversion of Ch0
A0 = 1 Conversion of Ch1
A0 = 0 Conversion of Ch0
A0 Selects Between
Ch0 and Ch1 at Output
1st RD After CONVST ChA at Output
2nd RD After CONVST ChB at Output
RD
CS
4 Output-Register
Data of Ch0 Still Stored
CS Needed Only During Reading
High Data Level Output Active
Low Data Level Tri-state of Output
DATA
ChA0 ChB0
ChA1 ChB1 ChA0 ChB0
Conversion of Ch0
Conversion of Ch1
Conversion of Ch0
BUSY
TIME
0
1µ
2µ
3µ
4µ
5µ
Time (seconds)
FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality.
®
ADS7862
12
output data should not be read 125ns prior to the falling edge
of CONVST and 10ns after the falling edge. Any other
combination of CS and RD will tri-state the parallel output.
Valid conversion data can be read on pins 5 through 16
(MSB-LSB). Refer to Table I for ideal output codes.
SECTION A
Conversions are initiated by bringing the CONVST pin (pin
18) LOW for a minimum of 5ns (after the 5ns minimum
requirement has been met, the CONVST pin can be brought
HIGH). The ADS7862 will switch from the sample to the
hold mode on the falling edge of the CONVST command.
Following the first rising edge of the external clock after a
CONVST LOW, the ADS7862 will begin conversion (this
first rising edge of the external clock represents the start of
clock cycle one; the ADS7862 requires sixteen cycles to
complete a conversion). The input channel is also latched in
at this point in time. The A0 input (pin 22) must be selected
250ns prior to the CONVST pin going LOW so that the
correct address will be selected prior to conversion. The
BUSY output will go HIGH immediately following CONVST
going LOW. BUSY will stay HIGH through the conversion
process and return LOW when the conversion has ended.
After CONVST has remained LOW for the minimum time,
the ADS7862 will switch from the hold mode to the conver-
sion mode synchronous to the next rising edge of the
external clock and conversion ‘n – 2’ will begin. Both RD
(pin 21) and CS (pin 20) can be HIGH during and before a
conversion. However, they must both be LOW to enable the
output bus and read data out.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7862 circuitry. This is particu-
larly true if the CLOCK input is approaching the maximum
throughput rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections
and digital inputs that occur just prior to latching the output
of the analog comparator. Thus, driving any single conver-
sion for an n-bit SAR converter, there are n “windows” in
which large external transient voltages can affect the conver-
sion result. Such glitches might originate from switching
power supplies, nearby digital logic or high power devices.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the exter-
nal event. Their error can change if the external event
changes in time with respect to the CLOCK input.
With this in mind, power to the ADS7862 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low-pass filter a noisy supply. On average, the ADS7862
draws very little current from an external reference as the
reference voltage is internally buffered. If the reference
voltage is external and originates from an op amp, make sure
that it can drive the bypass capacitor or capacitors without
oscillation. A bypass capacitor is not necessary when using
the internal reference (tie pin 1 directly to pin 2).
SECTION B
The CONVST pin is switched from HIGH to LOW a second
time to initiate conversion ‘n – 1’. Again, the address must be
selected 250ns prior to CONVST going LOW to ensure that
the new address is selected for conversion. Both the RD and
CS pins are brought LOW in order to enable the parallel output
bus with the ‘n – 2’ conversion results of Channel A0. While
continuing to hold CS LOW, RD is held LOW for a minimum
of 30ns which enables the output bus with the Channel A0
results of conversion ‘n – 2’. The RD pin is toggled from
HIGH to LOW a second time in order to enable the output bus
with the Channel B0 results of conversion ‘n – 2’.
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the ‘analog’
ground. Avoid connections which are too close to the ground-
ing point of a microcontroller or digital signal processor. If
required, run a ground trace directly from the converter to
the power supply entry point. The ideal layout will include
an analog ground plane dedicated to the converter and
associated analog circuitry.
SECTION C
CONVST is brought LOW for a third time to initiate
conversion ‘n’ (Channel 0). While the conversion is in
process, the results for both conversions ‘n – 2’ and ‘n – 1’
can be read. The address pin is brought HIGH while CS and
RD are brought LOW which enables the output bus with the
Channel A1 results of conversion ‘n – 1’. The RD pin is
toggled from HIGH to LOW for a second time in Section C
and the ‘n – 1’ conversion results for Channel B1 appear at
the output bus. The address pin (A0) is then brought LOW
and the read process repeats itself with the most recent
conversion results for Channel 0 (n – 2) appearing at the
output bus.
APPLICATIONS
An applications section will be added featuring the ADS7862
interfacing to popular DSP processors. The updated data
sheet will be available in the near future on the Burr-Brown
web site:
http: //www.burr-brown.com/
READING DATA
The ADS7862 outputs full parallel data in Binary Two’s
Complement data output format. The parallel output will be
active when CS (pin 20) and RD (pin 21) are both LOW. The
®
ADS7862
13
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