ADS7862YB/2KG4 [TI]

Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling; 双500kHz的12位，2个2通道同时采样


型号：	ADS7862YB/2KG4
厂家：	TEXAS INSTRUMENTS
描述：	Dual 500kHz, 12-Bit, 2 2 Channel Simultaneous Sampling 双500kHz的12位，2个2通道同时采样转换器模数转换器
文件：	总20页 (文件大小：706K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADS7862

SBAS101B – JANUARY 1998 – REVISED AUGUST 2005

Dual 500kHz, 12-Bit, 2 + 2 Channel

Simultaneous Sampling

ANALOG-TO-DIGITAL CONVERTER

DESCRIPTION

FEATURES

The ADS7862 is a dual 12-bit, 500kHz analog-to-digital

converter (A/D) with 4 fully differential input channels grouped

into two pairs for high speed simultaneous signal acquisition.

Inputs to the sample-and-hold amplifiers are fully differential

and are maintained differential to the input of the A/D con-

verter. This provides excellent common-mode rejection of

80dB at 50kHz, which is important in high noise environ-

ments.

ꢀ 4 INPUT CHANNELS

ꢀ FULLY DIFFERENTIAL INPUTS

ꢀ 2µs TOTAL THROUGHPUT PER CHANNEL

ꢀ GUARANTEED NO MISSING CODES

ꢀ PARALLEL INTERFACE

ꢀ 1MHz EFFECTIVE SAMPLING RATE

ꢀ LOW POWER: 40mW

The ADS7862 offers parallel interface and control inputs to

minimize software overhead. The output data for each channel

is available as a 12-bit word. The ADS7862 is offered in an

TQFP-32 package and is fully specified over the –40°C to

+85°C operating range.

APPLICATIONS

ꢀ MOTOR CONTROL

ꢀ MULTI-AXIS POSITIONING SYSTEMS

ꢀ 3-PHASE POWER CONTROL

CH A0+

CH A0–

SAR

S/H

Amp

COMP

Interface

CDAC

CLOCK

CH A1+

Conversion

and

CH A1–

MUX

Control

BUSY

CONVST

REF_IN

Internal

2.5V

REF_OUT

Reference

Output

Registers

Data Output

CH B0+

CH B0–

S/H

Amp

COMP

CDAC

CH B1+

CH B1–

MUX

SAR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

www.ti.com

ORDERING INFORMATION⁽¹⁾

MAXIMUM

RELATIVE

ACCURACY

(LSB)

MAXIMUM

GAIN

ERROR

(%)

SPECIFICATION

TEMPERATURE

RANGE

PACKAGE

DESIGNATOR

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

PACKAGE

ADS7862Y

ADS7862YB

±2

±1

±0.75

TQFP-32

PBS

–40°C to +85°C

ADS7862Y/250

ADS7862Y/2K5

ADS7862YB/250

ADS7862YB/2K5

Tape and Reel, 250

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 2500

±0.5

TQFP-32

–40°C to +85°C

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

PIN DESCRIPTIONS

NAME

DESCRIPTION

Analog Inputs to AGND: Any Channel Input ........ –0.3V to (+V_D+ 0.3V)

REF_IN............................. –0.3V to (+V_D+ 0.3V)

Digital Inputs to DGND .......................................... –0.3V to (+V_D+ 0.3V)

Ground Voltage Differences: AGND, DGND ................................... ±0.3V

+V_Dto AGND ......................... –0.3V to +6V

REF_IN

Reference Input

REF_OUT

+2.5V Reference Output. Connect directly to REF_IN

(pin 1) when using internal reference.

Power Dissipation .......................................................................... 325mW

Maximum Junction Temperature ................................................... +150°C

Operating Temperature Range ........................................–40°C to +85°C

Storage Temperature Range .........................................–65°C to +150°C

Lead Temperature (soldering, 10s) ............................................... +300°C

AGND

+V_A

Analog Ground

Analog Power Supply, +5VDC. Connect directly to

digital power supply (pin 24). Decouple to analog

ground with a 0.1µF ceramic capacitor and a 10µF

tantalum capacitor.

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

BUSY

Data Bit 11, MSB

Data Bit 10

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and

installation procedures can cause damage.

Data Bit 9

Data Bit 8

Data Bit 7

Data Bit 6

Data Bit 5

Data Bit 4

Data Bit 3

ESD damage can range from subtle performance degradation to

completedevicefailure.Precisionintegratedcircuitsmaybemore

susceptible to damage because very small parametric changes

could cause the device not to meet its published specifications.

Data Bit 2

Data Bit 1

Data Bit 0, LSB

HIGH when a conversion is in progress.

CONVST Convert Start

CLOCK

An external CMOS-compatible clock can be applied to

PIN CONFIGURATION

the CLOCK input to synchronize the conversion pro-

cess to an external source. The CLOCK pin controls

Top View

the sampling rate by the equation: CLOCK 16 • f_SAMPLE

Chip Select

Synchronization pulse for the parallel output. During a

Read operation, the first falling edge selects the A

A0, then controls whether input 0 or input 1 is read.

32 31 30 29 28 27 26 25

24 +V_D

REF_IN

REF_OUT

AGND

+V_A

On the falling edge of Convert Start, when A0 is LOW

Channel A0 and Channel B0 are converted and when

it is HIGH, Channel A1 and Channel B1 are converted.

During a Read operation, the first falling edge selects

the A register and the second edge selects the B of RD

read.

23 DGND

22 A0

21 RD

ADS7862

20 CS

DB11

DB10

DB9

DGND

+V_D

Digital Ground. Connect directly to analog ground (pin 3).

Digital Power Supply, +5VDC

19 CLOCK

18 CONVST

17 BUSY

CH B1+ Non-Inverting Input Channel B1

CH B1– Inverting Input Channel B1

CH B0+ Non-Inverting Input Channel B0

DB8

CH B0–

CH A1–

Inverting Input Channel B0

Inverting Input Channel A1

10 11 12 13 14 15 16

CH A1+ Non-Inverting Input Channel A1

CH A0– Inverting Input Channel A0

CH A0+ Non-Inverting Input Channel A0

ADS7862

SBAS101B

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications T_MINto T_MAX, +V_A= +V_D= +5V, V_REF= internal +2.5V and f_CLK= 8MHz, f_SAMPLE= 500kHz, unless otherwise noted.

ADS7862Y

TYP

ADS7862YB

TYP

PARAMETER

RESOLUTION

CONDITIONS

MIN

MAX

MIN

MAX

UNITS

ꢀ

Bits

ANALOG INPUT

Input Voltage Range-Bipolar

Absolute Input Range

V_CENTER= Internal V_REFat 2.5V

–V_REF

–0.3

+V_REF

V_CC+ 0.3

ꢀ

+IN

–IN

Input Capacitance

Input Leakage Current

±1

ꢀ

µA

CLK = GND

SYSTEM PERFORMANCE

No Missing Codes

Integral Linearity

Integral Linearity Match

Differential Linearity

Bipolar Offset Error

Bipolar Offset Error Match

Positive Gain Error

Positive Gain Error Match

Negative Gain Error

Negative Gain Error Match

Common-Mode Rejection Ratio

ꢀ

Bits

LSB

% of FSR

LSB

% of FSR

LSB

±0.75

0.5

±0.75

±2

±0.5

ꢀ

±0.5

±1

ꢀ

±1

±2

±0.5

Referenced to REF_IN

At DC

±3

±0.75

±0.15

±0.1

120

±0.5

ꢀ

µV_RMS

LSB

_IN= ±1.25V_PPat 50kHz

Noise

Power Supply Rejection Ratio

±2

ꢀ

SAMPLING DYNAMICS

Conversion Time per A/D

Acquisition Time

1.75

0.25

ꢀ

µs

Throughput Rate

Aperture Delay

Aperture Delay Matching

Aperture Jitter

Small-Signal Bandwidth

500

ꢀ

kHz

MHz

3.5

100

ꢀ

DYNAMIC CHARACTERISTICS

Total Harmonic Distortion

SINAD

Spurious Free Dynamic Range

Channel-to-Channel Isolation

_IN= ±2.5V_PPat 100kHz

–78

ꢀ

–80

ꢀ

VOLTAGE REFERENCE

Internal

Internal Drift

2.475

2.5

±25

2.525

ꢀ

ppm/°C

µV_PP

mV/µA

µA

Internal Noise

Internal Source Current

Internal Load Rejection

Internal PSRR

External Voltage Range

Input Current

0.005

2.5

0.05

1.2

2.6

ꢀ

Input Capacitance

DIGITAL INPUT/OUTPUT

Logic Family

Logic Levels: V_IH

V_IL

V_OH

V_OL

External Clock

Data Format

CMOS

ꢀ

I_IH= +5µA

I_IL= +5µA

I_OH= –500µA

I_OL= 500µA

3.0

–0.3

3.5

+V_DD+ 0.3

0.8

ꢀ

MHz

0.4

ꢀ

0.2

ꢀ

Binary Two’s Complement

ꢀ

POWER SUPPLY REQUIREMENTS

Power Supply Voltage, +V

Quiescent Current, +V_A

4.75

5.25

ꢀ

Power Dissipation

ꢀ Specifications same as ADS7862Y.

ADS7862

SBAS101B

www.ti.com

BASIC OPERATION

REF_IN

REF_OUT

AGND

+V_A

+V_D24

DGND 23

A0 22

+5V

Analog Supply

Address Select

Read Input

RD 21

ADS7862Y

10µF

0.1µF

DB11

DB10

DB9

CS 20

Chip Select

CLOCK 19

CONVST 18

BUSY 17

Clock Input

Conversion Start

Busy Output

DB8

ADS7862

SBAS101B

www.ti.com

TYPICAL PERFORMANCE CHARACTERISTICS

At T_A= +25°C, +V_A= +V_D= +5V, V_REF= internal +2.5V and f_CLK= 8MHz, f_SAMPLE= 500kHz, unless otherwise noted.

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 99.9kHz, –0.5dB)

FREQUENCY SPECTRUM

(4096 Point FFT; f_IN= 199.9kHz, –0.5dB)

–20

–40

–60

–80

–100

–120

–100

–120

62.5

125

187.5

250

62.5

125

187.5

250

Frequency (kHz)

SIGNAL-TO-NOISE RATIO AND

SIGNAL-TO-(NOISE+DISTORTION)

vs INPUT FREQUENCY

CHANGE IN SIGNAL-TO-NOISE RATIO

AND SIGNAL-TO-(NOISE+DISTORTION)

vs TEMPERATURE

0.25

0.2

SNR

0.15

0.1

SINAD

0.05

SINAD

–0.05

–0.1

–0.15

–0.2

–0.25

SNR

10k

100k

–40

Input Frequency (Hz)

Temperature (°C)

CHANGE IN POSITIVE GAIN MATCH

vs TEMPERATURE

(Maximum Deviation for All Four Channels)

CHANGE IN SPURIOUS FREE DYNAMIC RANGE

AND TOTAL HARMONIC DISTORTION

vs TEMPERATURE

0.65

0.45

0.65

0.6

0.5

0.4

0.3

0.2

0.1

0.45

SFDR

0.25

0.05

–0.15

–0.35

–0.55

–0.75

–0.15

–0.35

–0.55

–0.75

THD

–40

Temperature (°C)

150

Temperature (°C)

ADS7862

SBAS101B

www.ti.com

TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)

At T_A= +25°C, +V_A= +V_D= +5V, V_REF= internal +2.5V and f_CLK= 8MHz, f_SAMPLE= 500kHz, unless otherwise noted.

CHANGE IN NEGATIVE GAIN MATCH

CHANGE IN REFERENCE VOLTAGE

vs TEMPERATURE

(Maximum Deviation for All Four Channels)

2.51

2.505

2.5

0.2

0.18

0.16

0.14

0.12

0.1

2.495

2.49

0.08

0.06

0.04

0.02

2.485

–40

150

7FF

–40

Temperature (°C)

150

Temperature (°C)

CHANGE IN BIPOLAR ZERO

vs TEMPERATURE

CHANGE IN BPZ MATCH vs TEMPERATURE

0.75

0.5

0.75

0.5

B Channel

0.25

–0.25

–0.5

–0.75

A Channel

0.25

–40

Temperature (°C)

–40

Temperature (°C)

INTEGRAL LINEARITY ERROR vs CODE

Typical of All Four Channels

CHANGE IN CMRR vs TEMPERATURE

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1

800

000

–40

–5

Hex BTC Code

Temperature (°C)

ADS7862

SBAS101B

www.ti.com

TYPICAL PERFORMANCE CHARACTERISTICS (Cont.)

At T_A= +25°C, +V_A= +V_D= +5V, V_REF= internal +2.5V and f_CLK= 8MHz, f_SAMPLE= 500kHz, unless otherwise noted.

DIFFERENTIAL LINEARITY ERROR vs CODE

Typical of All Four Channels

INTEGRAL LINEARITY ERROR vs TEMPERATURE

Positive ILE

0.75

0.5

0.6

0.4

0.2

0.25

–0.2

–0.4

–0.6

–0.8

–0.25

–0.5

–0.75

–1

Negative ILE

800

000

7FF

–40

150

7FF

150

Hex BTC Code

Temperature (°C)

INTEGRAL LINEARITY ERROR MATCH

vs CODE CHANNEL A0/CHANNEL A1

(Same Converter, Different Channels)

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

0.8

0.6

0.25

0.2

Positive DLE

0.15

0.1

0.4

0.2

0.05

–0.05

–0.1

–0.15

–0.2

–0.25

–0.2

–0.4

–0.6

–0.8

Negative DLE

–40

150

800

000

Temperature (°C)

Hex BTC Code

INTEGRAL LINEARITY ERROR MATCH

vs TEMPERATURE

CHANNEL A0/CHANNEL B0

(Different Converter, Different Channels)

INTEGRAL LINEARITY ERROR MATCH

vs CODE CHANNEL A0/CHANNEL B1

(Different Converter, Different Channels)

0.25

0.2

0.19

0.18

0.17

0.16

0.15

0.14

0.13

0.12

0.15

0.1

0.05

–0.05

–0.1

–0.15

–0.2

–0.25

–40

800

000

7FF

Temperature (°C)

Hex BTC Code

ADS7862

SBAS101B

www.ti.com

REFERENCE

INTRODUCTION

Under normal operation, the REF_OUTpin (pin 2) should be

directly connected to the REF_INpin (pin 1) to provide an

internal +2.5V reference to the ADS7862. The ADS7862

can operate, however, with an external reference in the range

of 1.2V to 2.6V for a corresponding full-scale range of 2.4V

to 5.2V.

The ADS7862 is a high speed, low power, dual 12-bit A/D

converter that operates from a single +5V supply. The input

channels are fully differential with a typical common-mode

rejection of 80dB. The part contains dual 2µs successive

approximation A/Ds, two differential sample-and-hold am-

plifiers, an internal +2.5V reference with REF_INand REF_OUT

pins and a high speed parallel interface. There are four

analog inputs that are grouped into two channels (A and B)

selected by the A0 input (A0 LOW selects Channels A0 and

B0, while A0 HIGH selects Channels A1 and B1). Each

A/D converter has two inputs (A0 and A1 and B0 and B1)

that can be sampled and converted simultaneously, thus

preserving the relative phase information of the signals on

both analog inputs. The part accepts an analog input voltage

in the range of –V_REFto +V_REF, centered around the internal

+2.5V reference. The part will also accept bipolar input

ranges when a level shift circuit is used at the front end (see

Figure 7).

The internal reference of the ADS7862 is double-buffered.

If the internal reference is used to drive an external load, a

buffer is provided between the reference and the load ap-

plied to pin 2 (the internal reference can typically source

2mA of current—load capacitance should not exceed 100pF).

If an external reference is used, the second buffer provides

isolation between the external reference and the CDAC.

This buffer is also used to recharge all of the capacitors of

both CDACs during conversion.

ANALOG INPUT

The analog input is bipolar and fully differential. There are

two general methods of driving the analog input of the

ADS7862: single-ended or differential (see Figures 1 and 2).

When the input is single-ended, the –IN input is held at the

common-mode voltage. The +IN input swings around the

same common voltage and the peak-to-peak amplitude is the

(common-mode +V_REF) and the (common-mode –V_REF).

The value of V_REFdetermines the range over which the

common-mode voltage may vary (see Figure 3).

A conversion is initiated on the ADS7862 by bringing the

CONVST pin LOW for a minimum of 15ns. CONVST

LOW places both sample-and-hold amplifiers in the hold

state simultaneously and the conversion process is started on

both channels. The BUSY output will then go HIGH and

remain HIGH for the duration of the conversion cycle.

Depending on the status of the A0 pin, the data will either

reflect a conversion of Channel 0 (A0 LOW) or Channel 1

(A0 HIGH). The data can be read from the parallel output

bus following the conversion by bringing both RD and CS

LOW.

When the input is differential, the amplitude of the input is the

difference between the +IN and –IN input, or: (+IN) – (–IN).

The peak-to-peak amplitude of each input is ±1/2V_REFaround

this common voltage. However, since the inputs are 180° out

of phase, the peak-to-peak amplitude of the differential voltage

is +V_REFto –V_REF. The value of V_REFalso determines the

range of the voltage that may be common to both inputs (see

Figure 4).

Conversion time for the ADS7862 is 1.75µs when an 8MHz

external clock is used. The corresponding acquisition time is

0.25µs. To achieve maximum output rate (500kHz), the read

function can be performed immediately at the start of the

next conversion.

NOTE: This mode of operation is described in more detail

in the Timing and Control section of this data sheet.

SAMPLE-AND-HOLD SECTION

–V_REFto +V_REF

ADS7862

The sample-and-hold amplifiers on the ADS7862 allow the

A/Ds to accurately convert an input sine wave of full-scale

amplitude to 12-bit accuracy. The input bandwidth of the

sample-and-hold is greater than the Nyquist rate (Nyquist

equals one-half of the sampling rate) of the A/D even when

the A/D is operated at its maximum throughput rate of

500kHz. The typical small-signal bandwidth of the sample-

and-hold amplifiers is 40MHz.

peak-to-peak

Common

Voltage

Single-Ended Input

V_REF

peak-to-peak

ADS7862

Common

V_REF

Typical aperture delay time or the time it takes for the

ADS7862 to switch from the sample to the hold mode

following the CONVST pulse is 3.5ns. The average delta of

repeated aperture delay values is typically 50ps (also known

as aperture jitter). These specifications reflect the ability of

the ADS7862 to capture AC input signals accurately at the

exact same moment in time.

Voltage

peak-to-peak

Differential Input

FIGURE 1. Methods of Driving the ADS7862 Single-Ended

or Differential.

ADS7862

SBAS101B

www.ti.com

+IN

CM +V_REF

+V_REF

CM Voltage

–IN = CM Voltage

–V_REF

CM –V_REF

Single-Ended Inputs

+IN

+V_REF

CM +1/2V_REF

CM Voltage

–V_REF

–IN

CM –1/2V_REF

Differential Inputs

(IN+) + (IN–)

NOTES: Common-Mode Voltage (Differential Mode) =

Common-Mode Voltage (Single-Ended Mode) = IN–.

The maximum differential voltage between +IN and –IN of the ADS7862 is V_REF. See Figures 3 and 4 for a further

explanation of the common voltage range for single-ended and differential inputs.

FIGURE 2. Using the ADS7862 in the Single-Ended and Differential Input Modes.

V_CC= 5V

4.7

V_CC= 5V

4.1

4.05

2.7

2.3

Single-Ended Input

Differential Input

0.90

0.9

0.3

–1

1.2

2.5^2.6

3.0

1.2

2.6

1.0

1.5

2.0

1.0

1.5

2.0

2.5

3.0

V_REF(V)

FIGURE 3. Single-Ended Input: Common-Mode Voltage

Range vs V_REF

FIGURE 4. Differential Input: Common-Mode Voltage

Range vs V_REF

In each case, care should be taken to ensure that the output

impedance of the sources driving the +IN and –IN inputs are

matched. Otherwise, this may result in offset error, which

will change with both temperature and input voltage.

capacitance has been fully charged, there is no further input

current. The source of the analog input voltage must be able

to charge the input capacitance (15pF) to a 12-bit settling

level within 2 clock cycles. When the converter goes into the

hold mode, the input impedance is greater than 1GΩ.

The input current on the analog inputs depend on a number

of factors: sample rate, input voltage, and source impedance.

Essentially, the current into the ADS7862 charges the inter-

nal capacitor array during the sampling period. After this

Care must be taken regarding the absolute analog input

voltage. The +IN input should always remain within the

range of GND – 300mV to V_DD+ 0.3V.

ADS7862

SBAS101B

www.ti.com

TRANSITION NOISE

1.4V

Figure 5 shows a histogram plot for the ADS7862 following

8,000 conversions of a DC input. The DC input was set at

output code 2046. All but one of the conversions had an

output code result of 2046 (one of the conversions resulted

in an output of 2047). The histogram reveals the excellent

noise performance of the ADS7862.

3kΩ

DATA

Test Point

100pF

C_LOAD

8000

7000

6000

5000

4000

3000

2000

1000

V_OH

V_OL

DATA

t_R

t_F

Voltage Waveforms for DATA Rise and Fall Times t_R, and t_F.

FIGURE 6. Test Circuits for Timing Specifications.

2044

2045

2046

2047

2048

Code (decimal)

R₁

FIGURE 5. Histogram of 8,000 Conversions of a DC Input.

4kΩ

+IN

OPA132

20kΩ

BIPOLAR INPUTS

Bipolar Input

–IN

The differential inputs of the ADS7862 were designed to

accept bipolar inputs (–V_REFand +V_REF) around the internal

reference voltage (2.5V), which corresponds to a 0V to 5V

input range with a 2.5V reference. By using a simple op amp

circuit featuring a single amplifier and four external resis-

tors, the ADS7862 can be configured to except bipolar

inputs. The conventional ±2.5V, ±5V, and ±10V input

ranges can be interfaced to the ADS7862 using the resistor

values shown in Figure 7.

ADS7862

R₂

REF_OUT(pin 2)

2.5V

BIPOLAR INPUT

R₁

R₂

±10V

±5V

±2.5V

1kΩ

2kΩ

4kΩ

5kΩ

10kΩ

20kΩ

FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.

TIMING AND CONTROL

The ADS7862 uses an external clock (CLOCK, pin 19)

which controls the conversion rate of the CDAC. With an

8MHz external clock, the A/D sampling rate is 500kHz

which corresponds to a 2µs maximum throughput time.

Three timing diagrams are used to explain the operation of

the ADS7862. Figure 8 shows the timing relationship be-

tween the CLOCK, CONVST (pin 18) and the conversion

t_CKP

t_CKH

t_CKL

CLOCK

t₃

CONVST

CONVERSION

MODE

SAMPLE

HOLD

CONVERT

NOTE: The ADS7862 will switch from the sample to the hold mode the instant CONVST goes LOW regardless of

the state of the external clock. The conversion process is initiated with the first rising edge of the external clock

following CONVST going LOW.

FIGURE 8. Conversion Mode.

ADS7862

SBAS101B

www.ti.com

mode. Figure 9, in conjunction with Table I, shows the basic

read/write functions of the ADS7862 and highlights all of

the timing specifications. Figure 10 shows a more detailed

description of initiating a conversion using CONVST. Fig-

ure 11 illustrates three consecutive conversions and, with the

accompanying text, describes all of the read and write

capabilities of the ADS7862.

first followed by Channel 1. Channel 1 can be converted

prior to Channel 0 if the user wishes by simply starting the

conversion process with the A0 pin at logic HIGH (Channel

1) followed by logic LOW (Channel 0).

TIMING SPECIFICATIONS

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

DESCRIPTION

ANALOG INPUT

t_CONV

t_ACQ

t_CKP

t_CKL

t_CKH

t₁

Conversion Time

Acquisition Time

1.75

0.25

5000

µs

(1)

DIGITAL OUTPUT

BINARY TWO’S COMPLEMENT

Full-Scale Input Span

–V_REFto +V_REF

Clock Period

125

Least Significant

Bit (LSB)

(–V_REFto +V_REF)/4096⁽²⁾

Clock LOW

BINARY CODE

HEX CODE

Clock HIGH

+Full Scale

Midscale

4.99878V

2.5V

0111 1111 1111

0000 0000 0000

1111 1111 1111

1000 0000 0000

7FF

000

FFF

800

CS to RD Setup Time

CS to RD Hold Time

t₂

t₃

CONVST LOW

Midscale – 1 LSB

–Full Scale

2.49878V

t₄

RD Pulse Width

t₅

RD to Valid Data (Bus Access)

RD to HI-Z Delay (Bus Relinquish)

Time Between Conversion Reads

Address Setup Time

NOTES: (1) –V_REFto +V_REFaround V_REF. With a 2.5V reference, this corre-

sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.

t₆

t₇

250

t₈

TABLE I. Ideal Input Voltages and Output Codes.

t₉

CONVST HIGH

t₁₀

t₁₁

t₁₂

t₁₃

t_F

Address Hold Time

CONVST to BUSY Propagation Delay

CONVST LOW Prior to CLOCK Rising Edge

CONVST LOW After CLOCK Rising Edge

Data Fall Time

The Figure 11 timing diagram can be divided into three

sections: (a) initiating a conversion (n – 2), (b) starting a

second conversion (n – 1) while reading the data output from

the previous conversion (n – 2), and (c) starting a third

conversion (n) while reading both previous conversions

(n – 2 and n – 1). In this sequence, Channel 0 is converted

t_R

Data Rise Time

CLOCK

t_CONV

t_ACQ

t₁₂t₁₃

CONVST

BUSY

t₃

t₉

t₁₁

Conversion n

Conversion n + 1

t₁₀

t₈

t₁

t₂

t₇

t₄

t₅

t₆

DATA

CHA1

CHB1

CHA0

CHB0

Conversion n – 1 Results

Conversion n Results

FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle.

ADS7862

SBAS101B

www.ti.com

t_CKP

125ns

CLOCK

Cycle 1

Cycle 2

10ns

5ns

CONVST

NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock

(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after

the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the

rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will

initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from

HIGH to LOW in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If

CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or

the following edge.

FIGURE 10. Timing Between CLOCK and CONVST to Start a Conversion.

SECTION A

SECTION B

SECTION C

CLOCK

CONVST

min 250ns

A0 = 0 Conversion of Ch0

A0 = 1 Conversion of Ch1

A0 = 0 Conversion of Ch0

A0 Selects Between

Ch0 and Ch1 at Output

1st RD After CONVST ChA at Output

2nd RD After CONVST ChB at Output

4 Output-Register

CS Needed Only During Reading

High Data Level Output Active

Data of Ch0 Still Stored

Low Data Level Tri-state of Output

DATA

ChA0 ChB0

ChA1 ChB1 ChA0 ChB0

Conversion of Ch0

Conversion of Ch1

Conversion of Ch0

BUSY

TIME

1µ

2µ

3µ

4µ

5µ

Time (seconds)

FIGURE 11. ADS7862 Timing Diagram Showing Complete Functionality.

ADS7862

SBAS101B

www.ti.com

SECTION A

output data should not be read 125ns prior to the falling edge

of CONVST and 10ns after the falling edge. Any other

combination of CS and RD will tri-state the parallel output.

Valid conversion data can be read on pins 5 through 16

(MSB–LSB). Refer to Table I for ideal output codes.

Conversions are initiated by bringing the CONVST pin (pin

18) LOW for a minimum of 5ns (after the 5ns minimum

requirement has been met, the CONVST pin can be brought

HIGH). The ADS7862 will switch from the sample to the

hold mode on the falling edge of the CONVST command.

Following the first rising edge of the external clock after a

CONVST LOW, the ADS7862 will begin conversion (this

first rising edge of the external clock represents the start of

clock cycle one; the ADS7862 requires sixteen cycles to

complete a conversion). The input channel is also latched in

at this point in time. The A0 input (pin 22) must be selected

250ns prior to the CONVST pin going LOW so that the

correct address will be selected prior to conversion. The

BUSY output will go HIGH immediately following CONVST

going LOW. BUSY will stay HIGH through the conversion

process and return LOW when the conversion has ended.

After CONVST has remained LOW for the minimum time,

the ADS7862 will switch from the hold mode to the conver-

sion mode synchronous to the next rising edge of the

external clock and conversion ‘n – 2’ will begin. Both RD

(pin 21) and CS (pin 20) can be HIGH during and before a

conversion. However, they must both be LOW to enable the

output bus and read data out.

In applications where multiple devices are present on the

data bus, care should be taken to ensure that the signal

applied to RD (pin 21) is toggled only when the target device

is properly chip-selected. Toggling the RD pin will advance

the internal read pointer regardless of the state of the chip

select, causing the output data to appear channel-swapped.

If multiple devices share a single read enable from the host

processor, the signal may be ORed with an address-decoded

chip select to ensure channel data integrity. For more infor-

mation, refer to Application Report SBAA138, Reading

Data from the ADS7862, available for download from the TI

website at www.ti.com.

LAYOUT

For optimum performance, care should be taken with the

physical layout of the ADS7862 circuitry. This is particu-

larly true if the CLOCK input is approaching the maximum

throughput rate.

The basic SAR architecture is sensitive to glitches or sudden

changes on the power supply, reference, ground connections

and digital inputs that occur just prior to latching the output

of the analog comparator. Thus, driving any single conver-

sion for an n-bit SAR converter, there are n “windows” in

which large external transient voltages can affect the conver-

sion result. Such glitches might originate from switching

power supplies, nearby digital logic or high power devices.

The degree of error in the digital output depends on the

reference voltage, layout, and the exact timing of the exter-

nal event. This error can change if the external event changes

in time with respect to the CLOCK input.

SECTION B

The CONVST pin is switched from HIGH to LOW a second

time to initiate conversion ‘n – 1’. Again, the address must be

selected 250ns prior to CONVST going LOW to ensure that

the new address is selected for conversion. Both the RD and

CS pins are brought LOW in order to enable the parallel output

bus with the ‘n – 2’ conversion results of Channel A0. While

continuing to hold CS LOW, RD is held LOW for a minimum

of 30ns which enables the output bus with the Channel A0

results of conversion ‘n – 2’. The RD pin is toggled from

HIGH to LOW a second time in order to enable the output bus

with the Channel B0 results of conversion ‘n – 2’.

With this in mind, power to the ADS7862 should be clean

and well bypassed. A 0.1µF ceramic bypass capacitor should

be placed as close to the device as possible. In addition, a

1µF to 10µF capacitor is recommended. If needed, an even

larger capacitor and a 5Ω or 10Ω series resistor may be used

to low-pass filter a noisy supply. On average, the ADS7862

draws very little current from an external reference as the

reference voltage is internally buffered. If the reference

voltage is external and originates from an op amp, make sure

that it can drive the bypass capacitor or capacitors without

oscillation. A bypass capacitor is not necessary when using

the internal reference (tie pin 1 directly to pin 2).

SECTION C

CONVST is brought LOW for a third time to initiate

conversion ‘n’ (Channel 0). While the conversion is in

process, the results for both conversions ‘n – 2’ and ‘n – 1’

can be read. The address pin is brought HIGH while CS and

RD are brought LOW which enables the output bus with the

Channel A1 results of conversion ‘n – 1’. The RD pin is

toggled from HIGH to LOW for a second time in Section C

and the ‘n – 1’ conversion results for Channel B1 appear at

the output bus. The address pin (A0) is then brought LOW

and the read process repeats itself with the most recent

conversion results for Channel 0 (n – 2) appearing at the

output bus.

The AGND and DGND pins should be connected to a clean

ground point. In all cases, this should be the ‘analog’

ground. Avoid connections which are too close to the ground-

ing point of a microcontroller or digital signal processor. If

required, run a ground trace directly from the converter to

the power supply entry point. The ideal layout will include

an analog ground plane dedicated to the converter and

associated analog circuitry.

READING DATA

The ADS7862 outputs full parallel data in Binary Two’s

Complement data output format. The parallel output will be

active when CS (pin 20) and RD (pin 21) are both LOW. The

ADS7862

SBAS101B

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

ADS7862Y/250

ADS7862Y/250G4

ADS7862Y/2K

ACTIVE

TQFP

PBS

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

2000

250

Green (RoHS

& no Sb/Br)

ADS7862Y/2KG4

ADS7862YB/250

ADS7862YB/250G4

ADS7862YB/2K

ADS7862YB/2KG4

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

21-May-2010

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ADS7862Y/250

ADS7862Y/2K

ADS7862YB/250

ADS7862YB/2K

TQFP

PBS

250

2000

250

330.0

16.4

7.2

1.5

12.0

16.0

2000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ADS7862Y/250

ADS7862Y/2K

ADS7862YB/250

ADS7862YB/2K

TQFP

PBS

250

2000

250

367.0

38.0

2000

Pack Materials-Page 2

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