ADS801U [BB]
12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER; 12位， 25MHz的采样模拟数字转换器
| 型号： | ADS801U |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 12-Bit, 25MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总13页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADS801
ADS801U
ADS801E
TM
12-Bit, 25MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
● NO MISSING CODES
● LOW POWER: 270mW
● INTERNAL REFERENCE
● WIDEBAND TRACK/HOLD: 65MHz
● SINGLE +5V SUPPLY
The ADS801 is a low power, monolithic 12-bit, 25MHz
analog-to-digital converter utilizing a small geometry
CMOS process. This COMPLETE converter includes
a 12-bit quantizer, wideband track/hold, reference, and
three-state outputs. It operates from a single +5V
power supply and can be configured to accept either
single-ended or differential input signals.
● PACKAGE: 28-Lead SOIC and
The ADS801 employs digital error correction to provide
excellent Nyquist differential linearity performance for
demanding imaging applications. Its low distortion,
high SNR and high oversampling capability give it the
extra margin needed for telecommunications, instru-
mentation and video applications.
28-Lead SSOP
APPLICATIONS
● IF AND BASEBAND DIGITIZATION
● DIGITAL COMMUNICATIONS
● TEST INSTRUMENTATION
This high performance A/D converter is specified over
temperature for AC and DC performance at a 25MHz
sampling rate. The ADS820 is available in 28-lead
SOIC and 28-lead SSOP packages.
● CCD IMAGING
Copiers
Scanners
Cameras
● VIDEO DIGITIZING
● GAMMA CAMERAS
CLK
MSBI
OE
Timing
Circuitry
IN
IN
12-Bit
Digital
Data
Error
Correction
Logic
3-State
Outputs
Pipeline
A/D
T/H
+3.25V
REFT
CM
REFB
+1.25V
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
•
Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1995 Burr-Brown Corporation
PDS-1287E
Printed in U.S.A. September, 1996
SPECIFICATIONS
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
ADS801U
TYP
ADS801E
TYP
PARAMETER
CONDITIONS
TEMP
MIN
MAX
MIN
MAX
UNITS
Resolution
Specified Temperature Range
12
12
Bits
°C
(1)
TAMBIENT
–40
+85
✻
✻
✻
ANALOG INPUT
Differential Full Scale Input Range
Both Inputs,
180° Out of Phase
+1.25
+3.25
✻
V
V
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small Signal
Full Power
Input Impedance
+2.25
✻
–20dBFS(2) Input
0dBFS Input
+25°C
+25°C
400
65
1.25 || 4
✻
✻
✻
MHz
MHz
MΩ || pF
DIGITAL INPUT
Logic Family
Convert Command
TTL/HCT Compatible CMOS
Falling Edge
TTL/HCT Compatible CMOS
Falling Edge
Start Conversion
ACCURACY(3)
Gain Error
+25°C
Full
±0.6
±1.0
±85
0.03
±2.1
0.05
±1.5
±2.5
✻
✻
✻
✻
✻
✻
✻
✻
%
%
Gain Tempco
Power Supply Rejection of Gain
Input Offset Error
ppm/°C
%FSR/%
%
Delta +VS = ±5%
Delta +VS = ±5%
+25°C
Full
+25°C
0.15
±3.0
0.15
✻
✻
✻
Power Supply Rejection of Offset
%FSR/%
CONVERSION CHARACTERISTICS
Sample Rate
10k
25M
✻
✻
Sample/s
Data Latency
6.5
✻
Convert Cycle
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
+25°C
0°C to +85°C
+25°C
0°C to +85°C
0°C to +85°C
Full
±0.3
±0.4
±0.3
±1.0
±1.0
±1.0
±1.0
±0.4
±0.5
±0.4
✻
✻
✻
✻
LSB
LSB
LSB
LSB
LSB
LSB
f = 10MHz
±0.4
±0.5
No Missing Codes
Guaranteed
±1.7
Guaranteed
✻
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
63
62
57
55
77
73
61
61
✻
✻
✻
✻
✻
✻
✻
✻
dBFS
dBFS
dBFS
dBFS
f = 10MHz (–1dBFS input)
Two-Tone Intermodulation Distortion (IMD)(4)
f = 4.4MHz and 4.5MHz (–7dBFS each tone)
+25°C
Full
–64
–63
✻
✻
dBc
dBc
Signal-to-Noise Ratio (SNR)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
64
61
62
58
66
64
65
64
62
59
✻
64
✻
✻
✻
dB
dB
dB
dB
f = 10MHz (–1dBFS input)
✻
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (–1dBFS input)
+25°C
Full
+25°C
Full
+25°C
+25°C
+25°C
+25°C
+25°C
63
60
56
54
66
63
59
58
0.5
0.1
2
61
58
✻
64
✻
✻
✻
✻
✻
✻
✻
✻
dB
dB
dB
dB
%
degrees
ns
ps rms
ns
f = 10MHz (–1dBFS input)
✻
Differential Gain Error
Differential Phase Error NTSC or PAL
Aperture Delay Time
Aperture Jitter
Overvoltage Recovery Time(5)
NTSC or PAL
7
2
1.5x Full Scale Input
NOTE: (1) An asterisk (✻) indicates same specifications as the ADS801U. (2) dBFS refers to dB below Full Scale. (3) Percentage accuracies are referred to the
internal A/D Full Scale Range of 4Vp-p. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope signal (≈0dB), the intermodulation
products will be 7dB lower. (5) No “rollover” of bits.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
2
ADS801
SPECIFICATIONS (CONT)
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
ADS801U
TYP
ADS801E
TYP
PARAMETER
CONDITIONS
TEMP
MIN
MAX
MIN
MAX
UNITS
OUTPUTS
Logic Family
Logic Coding
Logic Levels
TTL/HCT Compatible CMOS
Falling Edge
TTL/HCT Compatible CMOS
Falling Edge
Logic Selectable
Logic “LO”,
CL = 15pF max
Logic “HI”,
Full
Full
0
0.4
✻
✻
V
V
+2.5
+VS
✻
✻
CL = 15pF max
3-State Enable Time
3-State Disable Time
20
2
40
10
✻
✻
✻
✻
ns
ns
Full
POWER SUPPLY REQUIREMENTS
Supply Voltage: +VS
Supply Current: +IS
Operating
Operating
Operating
Operating
Operating
Full
+25°C
Full
+25°C
Full
+4.75
+5.0
54
54
270
270
+5.25
65
68
325
340
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
mA
mA
mW
mW
Power Consumption
Thermal Resistance, θJA
28-Lead SOIC
28-Lead SSOP
75
50
✻
✻
°C/W
°C/W
✻
Specifications same as ADS801U.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
+VS ....................................................................................................... +6V
Analog Input ............................................................. 0V to (+VS + 300mV)
Logic Input ................................................................ 0V to (+VS + 300mV)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +125°C
External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB) .............................. +1.1V Min
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
NOTE: Stresses above these ratings may permanently damage the device.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING TEMPERATURE
PRODUCT
PACKAGE
NUMBER(1)
RANGE
ADS801U
ADS801E
28-Lead SOIC
28-Lead SSOP
217
324
–40°C to +85°C
–40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
ADS801
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
DESIGNATOR DESCRIPTION
TOP VIEW
SOIC/SSOP
1
2
GND
B1
Ground
Bit 1, Most Significant Bit
3
B2
Bit 2
4
B3
Bit 3
GND
B1
B2
B3
B4
B5
B6
B7
B8
1
2
3
4
5
6
7
8
9
28 GND
27 IN
5
6
7
8
B4
B5
B6
B7
B8
B9
B10
B11
B12
GND
+VS
CLK
+VS
OE
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
26 IN
9
10
11
12
13
14
15
16
17
18
25 GND
24 +VS
23 REFT
22 CM
21 REFB
20 +VS
19 MSBI
18 OE
Bit 12, Least Significant Bit
Ground
+5V Power Supply
Convert Clock Input, 50% Duty Cycle
+5V Power Supply
ADS801
HI: High Impedance State. LO or Floating: Nor-
mal Operation. Internal pull-down resistors.
Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight
output. Internal pull-down resistors.
+5V Power Supply
Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.
Common-Mode Voltage. It is derived by (REFT +
REFB)/2.
Top Reference Bypass. For external bypassing
of internal +3.25V reference.
+5V Power Supply
Ground
Input
19
MSBI
B9 10
B10 11
B11 12
B12 13
GND 14
20
21
+VS
REFB
17 +VS
16 CLK
15 +VS
22
23
CM
REFT
24
25
26
27
28
+VS
GND
IN
IN
GND
Complementary Input
Ground
TIMING DIAGRAM
tCONV
tL
tH
CONVERT
CLOCK
tD
DATA LATENCY
(6.5 Clock Cycles)
(1)
Hold
"N"
Hold
"N + 1"
Hold
"N + 2"
Hold
"N + 3"
Hold
Hold
Hold
"N + 6"
Track
Track
Track
Track
Track
Track
"N + 4" "N + 5
Track
Track
"
INTERNAL
TRACK/HOLD
t2
OUTPUT
DATA
Data Valid
N-8
Data Valid
N-7
Data Valid
N-6
N-5
N-4
N-3
N-2
N-1
t1
N
Data Invalid
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tCONV
tL
tH
tD
t1
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
40
19
19
100µs
ns
ns
ns
ns
ns
ns
20
20
2
3.9
t2
New Data Delay Time, CL = 15pF max
12.5
NOTE: (1) “ ” indicates the portion of the waveform that will stretch out at slower sample rates.
®
4
ADS801
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
–
0
–20
–
–40
–
–60
–
–80
–1
–120
–100
–120
0
2.5
5.0
7.5
10.0
12.5
0
2.5
5.0
7.5
10.0
12.5
Frequency (MHz)
Frequency (MHz)
DIFFERENTIAL LINEARITY ERROR
DIFFERENTIAL LINEARITY ERROR
fIN = 10MHz
2.0
1.0
2.0
1.0
fIN = 500kHz
0
0
–1.0
–2.0
–1.0
–2.0
0
1024
2048
Code
3072
4096
0
1024
2048
Code
3072
4096
INPUT FREQUENCY vs DYNAMIC PERFORMANCE
TWO-TONE INTERMODULATION
80
75
70
65
60
55
50
0
–20
f1 = 4.5MHz
f2 = 4.4MHz
SFDR
–40
–60
SNR
–80
–100
–120
0.0
3.13
6.25
9.38
12.50
0.1
1
10
Frequency (MHz)
100
Frequency (MHz)
®
5
ADS801
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
OUTPUT NOISE HISTOGRAM (NO SIGNAL)
SWEPT POWER SFDR
800k
600k
400k
200k
0.0
100
80
60
40
20
0
fIN = 10MHz
N–2
N–1
N
N+1
N+2
–50
–40
–30
–20
–10
0
10
Code
Input Amplitude (dBm)
SWEPT POWER SNR
INTEGRAL LINEARITY ERROR
fIN = 500kHz
80
60
40
20
0
4.0
2.0
fIN = 10MHz
0
–2.0
–4.0
–50
–40
–30
–20
–10
0
10
0
1024
2048
Code
3072
4096
Input Amplitude (dBm)
DYNAMIC PERFORMANCE
DYNAMIC PERFORMANCE
vs DIFFERENTIAL FULL-SCALE INPUT RANGE
vs SINGLE-ENDED FULL-SCALE INPUT RANGE
70
65
60
55
65
60
55
50
SFDR (fIN = 10MHz)
SNR (fIN = 10MHz)
SNR (fIN = 10MHz)
SFDR (fIN = 10MHz)
1
2
3
4
5
1
2
3
4
5
Differential Full-Scale Input Range (Vp-p)
Single-Ended Full-Scale Input Range (Vp-p)
®
6
ADS801
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
vs TEMPERATURE
DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE
fIN = 500kHz
0.5
0.4
0.3
0.2
0.1
80
75
70
65
60
55
fIN = 500kHz
fIN = 10MHz
fIN = 10MHz
–50
–50
–50
–25
0
25
50
75
100
100
100
–50
–50
–50
–25
0
25
50
75
100
100
100
Ambient Temperature (°C)
Ambient Temperature (°C)
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
70
65
60
55
50
45
70
68
66
64
62
fIN = 500kHz
fIN = 500kHz
fIN = 10MHz
fIN = 10MHz
–25
0
25
50
75
–25
0
25
50
75
Ambient Temperature (°C)
Ambient Temperature (°C)
SUPPLY CURRENT vs TEMPERATURE
POWER DISSIPATION vs TEMPERATURE
52
51
50
49
265
260
255
250
245
–25
0
25
50
75
–25
0
25
50
75
Ambient Temperature (°C)
Ambient Temperature (°C)
®
7
ADS801
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +5V, Sampling Rate = 25MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
OFFSET ERROR vs TEMPERATURE
–0.05
–0.55
–1.05
–1.55
–1.50
–1.75
–2.0
–2.25
–50
–25
0
25
50
75
100
–50
–25
0
25
50
75
100
Ambient Temperature (°C)
Ambient Temperature (°C)
TRACK-MODE SMALL-SIGNAL INPUT BANDWIDTH
1
0
–1
–2
–3
–4
–5
10k
100k
1M
10M
100M
1G
Frequency (Hz)
®
8
ADS801
THEORY OF OPERATION
Op Amp
Bias
VCM
The ADS801 is a high speed sampling analog-to-digital
converter with pipelining. It uses a fully differential archi-
tecture and digital error correction to guarantee 12-bit reso-
lution. The differential track/hold circuit is shown in Figure
1. The switches are controlled by an internal clock which is
a non-overlapping two phase signal, φ1 and φ2. At the
sampling time the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase, φ2, the
bottom plates of the input capacitors are connected together
and the feedback capacitors are switched to the op amp
output. At this time the charge redistributes between CI and
CH, completing one track/hold cycle. The differential output
is a held DC representation of the analog input at the sample
time. The track/hold circuit can also convert a single-ended
input signal into a fully differential signal for the quantizer.
φ1
φ1
φ1
φ1
CH
φ2
φ2
CI
CI
IN
IN
OUT
OUT
φ1
φ1
φ2
CH
φ1
Input Clock (50%)
Op Amp
Bias
VCM
Internal Non-overlapping Clock
φ1 φ2 φ1
The pipelined quantizer architecture has 11 stages with each
stage containing a two-bit quantizer and a two bit digital-to-
analog converter, as shown in Figure 2. Each two-bit quan-
tizer stage converts on the edge of the sub-clock, which is
twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
IN
Digital Delay
Input
T/H
IN
2-Bit
Flash
2-Bit
DAC
+
STAGE 1
–
Σ
x2
B1 (MSB)
Digital Delay
B2
B3
B4
B5
B6
B7
B8
B9
B10
2-Bit
Flash
2-Bit
DAC
STAGE 2
+
–
Σ
x2
B11
Digital Delay
B12 (LSB)
2-Bit
Flash
2-Bit
DAC
STAGE 10
+
–
Σ
x2
2-Bit
Flash
Digital Delay
STAGE 11
FIGURE 2. Pipeline A/D Architecture.
®
9
ADS801
time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
gives the ADS801 excellent differential linearity and guar-
antees no missing codes at the 12-bit level.
DIGITAL OUTPUT DATA
The 12-bit output data is provided at CMOS logic levels.
The standard output coding is Straight Offset Binary where
a full scale input signal corresponds to all “1’s” at the output.
This condition is met with pin 19 “LO” or Floating due to
an internal pull-down resistor. By applying a logic “HI”
voltage to this pin, a Binary Two’s Complement output will
be provided where the most significant bit is inverted. The
digital outputs of the ADS801 can be set to a high imped-
ance state by driving OE (pin 18) with a logic “HI”. Normal
operation is achieved with pin 18 “LO” or Floating due to
internal pull-down resistors. This function is provided for
testability purposes and is not meant to drive digital buses
directly or be dynamically changed during the conversion
process.
Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS801 can be configured in
various ways and driven with different circuits, depending
on the nature of the signal and the level of performance
desired. The ADS801 has an internal reference that sets the
full scale input range of the A/D. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full scale range of
+1.25V to +3.25V. Since each input is 2V peak-to-peak and
180° out of phase with the other, a 4V differential input
signal to the quantizer results. As shown in Figure 3, the
positive full scale reference (REFT) and the negative full
scale (REFB) are brought out for external bypassing. In
addition, the common-mode voltage (CM) may be used as a
reference to provide the appropriate offset for the driving
circuitry. However, care must be taken not to appreciably
load this reference node. For more information regarding
external references, single-ended input, and ADS801 drive
circuits, refer to the applications section.
OUTPUT CODE
SOB
PIN 19
FLOATING or LO
BTC
PIN 19
HI
DIFFERENTIAL INPUT(1)
+FS (IN = +3.25V, IN = +1.25V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full Scale
111111111111
111111111111
111111111110
111000000000
110000000000
101000000000
100000000001
100000000000
011111111111
011000000000
010000000000
001000000000
000000000001
000000000000
011111111111
011111111111
011111111110
011000000000
010000000000
001000000000
000000000001
000000000000
111111111111
111000000000
110000000000
101000000000
100000000001
100000000000
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1.25V, IN = +3.25V)
Note: In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS801.
ADS801
+3.25V
REFT
23
APPLICATIONS
DRIVING THE ADS801
0.1µF
2kΩ
To
Internal
Comparators
The ADS801 has a differential input with a common-mode
of +2.25V. For AC-coupled applications, the simplest way
to create this differential input is to drive the primary
winding of a transformer with a single-ended input. A
differential output is created on the secondary if the center
tap is tied to the common-mode voltage of +2.25V per
Figure 4. This transformer-coupled input arrangement pro-
CM
22
21
+2.25V
0.1µF
2kΩ
REFB
+1.25V
FIGURE 3. Internal Reference Structure.
22 CM
CLOCK REQUIREMENTS
0.1µF
The CLK pin accepts a CMOS level clock input. The rising
and falling edges of the externally applied convert command
clock control the various interstage conversions in the pipe-
line. Therefore, the duty cycle of the clock should be held at
50% with low jitter and fast rise/fall times of 2ns or less.
This is particularly important when digitizing a high fre-
quency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten
some of the interstage settling times, thus degrading the
SNR and DNL performance.
26
IN
IN
AC Input
Signal
ADS801
22pF
27
22pF
Mini-Circuits
TT1-6-KK81
or equivalent
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
®
10
ADS801
vides good high frequency AC performance. It is important
to select a transformer that gives low distortion and does not
exhibit core saturation at full scale voltage levels. Since the
transformer does not appreciably load the ladder, there is no
need to buffer the common-mode (CM) output in this in-
stance. In general, it is advisable to keep the current draw
from the CM output pin below 0.5µA to avoid nonlinearity
in the internal reference ladder. A FET input operational
amplifier such as the OPA130 can provide a buffered refer-
ence for driving external circuitry. The analog IN and IN
inputs should be bypassed with 22pF capacitors to minimize
track/hold glitches and to improve high input frequency
performance.
by fC = 1/(2πRSER•(CSH+CADC)) where RSER is the resistor
in series with the input, CSH is the external capacitor from
the input to ground, and CADC is the internal input capaci-
tance of the A/D converter (typically 4pF).
Resistors R1 and R2 are used to derive the necessary com-
mon mode voltage from the buffered top and bottom refer-
ences. The total load of the resistor string should be selected
so that the current does not exceed 1mA. Although the
circuit in Figure 5 uses two resistors of equal value so that
the common mode voltage is centered between the top and
bottom reference (+2.25V), it is not necessary to do so. In all
cases the center point, VCM, should be bypassed to ground
in order to provide a low impedance AC ground.
Figure 5 illustrates another possible low cost interface circuit
which utilizes resistors and capacitors in place of a trans-
former. Depending on the signal bandwidth, the component
values should be carefully selected in order to maintain the
performance outlined in the data sheet. The input capacitors,
CIN, and the input resistors, RIN, create a high-pass filter with
the lower corner frequency at fC = 1/(2πRINCIN). The corner
frequency can be reduced by either increasing the value of
RIN or CIN. If the circuit operates with a 50Ω or 75Ω
impedance level, the resistors are fixed and only the value of
the capacitor can be increased. Usually AC-coupling capaci-
tors are electrolytic or tantalum capacitors with values of 1µF
or higher. It should be noted that these large capacitors
become inductive with increased input frequency, which
could lead to signal amplitude errors or oscillation. To
maintain a low AC-coupling impedance throughout the sig-
nal band, a small value (e.g. 1µF) ceramic capacitor could be
added in parallel with the polarized capacitor.
If the signal needs to be DC coupled to the input of the
ADS801, an operational amplifier input circuit is required.
In the differential input mode, any single-ended signal must
be modified to create a differential signal. This can be
accomplished by using two operational amplifiers, one in
the noninverting mode for the input and the other amplifier
in the inverting mode for the complementary input. The low
distortion circuit in Figure 6 will provide the necessary
input shifting required for signals centered around ground.
It also employs a diode for output level shifting to guarantee
a low distortion +3.25V output swing. Other amplifiers can
be used in place of the OPA642s if the lowest distortion is
not necessary. If output level shifting circuits are not used,
care must be taken to select operational amplifiers that give
the necessary performance when swinging to +3.25V with
a ±5V supply operational amplifier.
The ADS801 can also be configured with a single-ended
input full scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference volt-
age as shown in Figure 7 . This configuration will result in
increased even-order harmonics, especially at higher input
frequencies. However, this tradeoff may be quite acceptable
for time-domain applications. The driving amplifier must
give adequate performance with a +0.25V to +4.25V output
swing in this case.
Capacitors CSH1 and CSH2 are used to minimize current
glitches resulting from the switching in the input track and
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors RSER1 and RSER2 were added in series with
each input. The cut-off frequency of the filter is determined
C1
0.1µF
R1
(6kΩ)
CIN
0.1µF
*RSER1
49.9Ω
+3.25V
Top Reference
IN
CSH1
22pF
RIN1
25Ω
R3
1kΩ
ADS8xx
VCM
C2
0.1µF
RIN2
25Ω
IN
CSH2
+1.25V
Bottom Reference
*RSER2
49.9Ω
CIN
0.1µF
22pF
R2
(6kΩ)
C3
0.1µF
NOTE: * indicates optional component.
FIGURE 5. AC-Coupled Differential Input Circuit.
®
11
ADS801
+5V
604Ω
+5V
301Ω
BAS16(1)
Optional
High Impedance
Input Amplifier
27 IN
301Ω
OPA642
301Ω
+5V(2)
2.49kΩ
22pF
0.1µF
0.1µF
+5V
–5V
DC-Coupled
Input Signal
ADS801
604Ω
OPA642
604Ω
49.9Ω
+2.25V
OPA130
2.49kΩ
22 CM
+5V
–5V
+5V
301Ω
Input Level
Shift Buffer
301Ω
BAS16(1)
24.9Ω
26 IN
OPA642
22pF
0.1µF
–5V
604Ω
NOTES: (1) A Philips BAS16 diode or equivalent
may be used. (2) Supply bypassing not shown.
301Ω
FIGURE 6. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.
REFBEXT), with the common-mode being centered at
(REFTEXT + REFBEXT)/2. Refer to the typical performance
curves for expected performance vs full scale input range.
22 CM
0.1µF
Single-Ended
Input Signal
The circuit in Figure 8 works completely on a single +5V
supply. As a reference element, it uses the micro-power
reference REF1004-2.5, which is set to a quiescent current
of 0.1mA. Amplifier A2 is configured as a follower to buffer
the +1.25V generated from the resistor divider. To provide
the necessary current drive, a pull-down resistor, RP is
added.
ADS801
26 IN
27 IN
22pF
Full Scale = +0.25V to +4.25V with internal references.
FIGURE 7. Single-Ended Input Connection.
Amplifier A1 is configured as an adjustable gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor
again relieves the op amp from providing the full current
drive. The value of the pull-up/down resistors is not critical
and can be varied to optimize power consumption. The need
for pull-up/down resistors depends only on the drive capa-
bility of the selected drive amplifier and thus can be omitted.
EXTERNAL REFERENCES AND ADJUSTMENT OF
FULL SCALE RANGE
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V
and +3.25V references may be overridden by external refer-
ences that have at least 18mA (at room temperature) of
output drive capability. In this instance, the common-mode
voltage will be set halfway between the two references. This
feature can be used to adjust the gain error, improve gain
drift, or to change the full scale input range of the ADS801.
Changing the full scale range to a lower value has the benefit
of easing the swing requirements of external input amplifi-
ers. The external references can vary as long as the value of
the external top reference (REFTEXT) is less than or equal to
+3.4V and the value of the external bottom reference
(REFBEXT) is greater than or equal to +1.1V and the differ-
ence between the external references are greater than or
equal to 1.5V.
PC BOARD LAYOUT AND BYPASSING
A well-designed, clean PC board layout will assure proper
operation and clean spectral response. Proper grounding and
bypassing, short lead lengths, and the use of ground planes
are particularly important for high frequency circuits. Mul-
tilayer PC boards are recommended for best performance
but if carefully designed, a two-sided PC board with large,
heavy ground planes can give excellent results. It is recom-
mended that the analog and digital ground pins of the
ADS801 be connected directly to the analog ground plane.
In our experience, this gives the most consistent results. The
A/D power supply commons should be tied together at the
analog ground plane. Power supplies should be bypassed
with 0.1µF ceramic capacitors as close to the pin as possible.
For the differential configuration, the full scale input range
will be set to the external reference values that are selected. For
the single-ended mode, the input range is 2•(REFTEXT
–
®
12
ADS801
DYNAMIC PERFORMANCE TESTING
DYNAMIC PERFORMANCE DEFINITIONS
The ADS801 is a high performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high resolution FFT measurements to be made without
using data windowing functions. A low jitter signal genera-
tor such as the HP8644A for the test signal, phase-locked
with a low jitter HP8022A pulse generator for the A/D
clock, gives excellent results. Low pass filtering (or bandpass
filtering) of test signals is absolutely necessary to test the
low distortion of the ADS801. Using a signal amplitude
slightly lower than full scale will allow a small amount of
“headroom” so that noise or DC offset voltage will not
overrange the A/D and cause clipping on signal peaks.
1. Signal-to-Noise-and-Distortion Ratio (SINAD):
Sinewave Signal Power
10 log
Noise + Harmonic Power (first 15 harmonics)
2. Signal-to-Noise Ratio (SNR):
Sinewave Signal Power
10 log
Noise Power
3. Intermodulation Distortion (IMD):
Highest IMD Product Power (to 5th-order)
10 log
Sinewave Signal Power
IMD is referenced to the larger of the test signals f1 or f2.
Five “bins” either side of peak are used for calculation of
fundamental and harmonic power. The “0” frequency bin
(DC) is not included in these calculations as it is of little
importance in dynamic signal processing applications.
+5V
RP
220Ω
A
Top
1
1/2
OPA2234
Reference
+5V
+2.5V to +3.25V
2kΩ
10kΩ
6.2kΩ
10kΩ
REF1004
A
+2.5V
0.1µF
2
+1.25V
1/2
Bottom
Reference
10kΩ*
OPA2234
10kΩ
RP
220Ω
10kΩ*
NOTE: (*) Use parts alternatively for adjustment capability.
FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.
IDT74FCT2245
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
+5V
0.1µF
0.1µF
+VS
CLK
+VS
GND
LSB
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
13
12
11
10
9
Ext
Clk
1
Dir
G+
R1
50Ω
19
OE
MSBI
+VS
IDT74FCT2245
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
0.1µF
0.1µF
REFB
CM
8
ADS800
7
REFT
+VS
6
0.1µF
5
0.1µF
0.1µF
AC Input
Signal
GND
IN
4
3
R2
50Ω
IN
MSB
GND
2
(1)
GND
22pF
1
1
22pF
Mini-Circuits
TT1-6-KK81
or equivalent
Dir
G+
19
NOTE: (1) All capacitors should be located as close to the pins as the manufacturing
process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.
FIGURE 9. ADS801 Interface Schematic with AC-Coupling and External Buffers.
13
®
ADS801
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