ADS8323YB/2K [BB]
16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER; 16位， 500KSPS ，微功耗模拟数字转换器
| 型号： | ADS8323YB/2K |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总16页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADS8323
®
A
D
S
8
3
2
3
SBAS224B – DECEMBER 2001 – REVISED MAY 2002
16-Bit, 500kSPS, microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The ADS8323 is a 16-bit, 500kSPS Analog-to-Digital Con-
verter (ADC) with an internal 2.5V reference. The device
includes a 16-bit capacitor-based SAR ADC with inherent
sample-and-hold. The ADS8323 offers a full 16-bit interface,
or an 8-bit option where data is read using two read cycles.
ꢀ HIGH-SPEED PARALLEL INTERFACE
ꢀ 500kSPS SAMPLING RATE
ꢀ LOW POWER: 85mW at 500kSPS
ꢀ BIPOLAR INPUT RANGE
ꢀ TQFP-32 PACKAGE
The ADS8323 is available in a TQFP-32 package and is
specified over the industrial –40°C to +85°C temperature
range.
APPLICATIONS
ꢀ HIGH-SPEED DATA AQUISITION
ꢀ OPTICAL POWER MONITORING
ꢀ MOTOR CONTROL
ꢀ ATE
BYTE
SAR
Output Latches
and
Parallel
Three State
Data
ADS8323
Drivers
Output
+IN
CDAC
–IN
S/H Amp
CLOCK
Comparator
CONVST
CS
Conversion
and Control
Logic
REFIN
RD
BUSY
Internal
+2.5V Ref
REFOUT
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
PACKAGE/ORDERING INFORMATION
MAXIMUM
INTEGRAL
LINEARITY
ERROR (LSB)
NO
MISSING
CODES
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
ERROR (LSB) PACKAGE-LEAD DESIGNATOR(1)
ADS8323Y
±8
"
±6
"
14
"
15
"
TQFP-32
PBS
"
PBS
"
–40°C to 85°C
ADS8323Y/250
ADS8323Y/2K
ADS8323YB/250
ADS8323YB/2K
Tape and Reel, 250
Tape and Reel, 2000
Tape and Reel, 250
Tape and Reel, 2000
"
"
"
ADS8323YB
TQFP-32
–40°C to 85°C
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings over operating free-air temperature (unless
otherwise noted)(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage, DGND to DVDD .............................................................. –0.3V to 6V
Supply Voltage, AGND to AVDD ............................................................... –0.3V to 6V
Analog Input Voltage Range ..................... AGND - 0.3V to AVDD + 0.3V
Reference Input Voltage ........................... AGND - 0.3V to AVDD + 0.3V
Digital Input Voltage Range ...................... DGND - 0.3V to DVDD + 0.3V
Ground Voltage Differences, AGND to DGND ................................ ±0.3V
Voltage Differences, DVDD to AGND ..................................... –0.3V to 6V
Power Dissipation .......................................................................... 850mW
Operating Virtual Junction Temperature Range, TJ ........ –40°C to 150°C
Operating Free-Air Temperature Range, TA ...................... –40°C to 85°C
Storage Temperature Range, TSTG .................................. –65°C to 150°C
Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260°C
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses beyond those listed under "absolute maximum ratings" may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under "recommended operating conditions" is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
POWER SUPPLY
MIN
TYP
MAX
UNIT
DISSIPATION RATING TABLE
DERATING
(1)
Supply Voltage AVDD
4.75
4.75
5.0
5.0
5.25
5.25
V
V
(1)
TA ≤ 25°C
POWER
RATING
FACTOR
ABOVE
T
TA = 70°C
POWER
RATING
TA = 85°C
POWER
RATING
DVDD
ANALOG/REFERENCE INPUTS
PACKAGE
A = 25°C(1)
Differential analog input voltage
(IN+ to IN–)
External Reference Voltage
–REFIN
+REFIN
2.55
V
V
TQFP-32
1636mW
13.09mW/°C
1047mW
850mW
1.5
2.5
NOTE: (1) This is the inverse of the traditional junction-to-ambient thermal
resistance (RθJA). Thermal resistances are not production tested and are for
informational purposes only.
NOTE: (1) The voltage difference between AVDD and DVDD terminals cannot
exceed 0.3V to maintain performance specifications.
EQUIVALENT INPUT CIRCUIT
AVDD
DVDD
C(SAMPLE)
20pF
RON
20Ω
AIN
DIN
AGND
DGND
Diode Turn-On Voltage: 0.35V
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
ADS8323
2
SBAS224B
www.ti.com
ELECTRICAL CHARACTERISTICS
At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified.
ADS8323Y
TYP
ADS8323YB
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
16
ꢀ
Bits
ANALOG INPUT
Full-Scale Input Span(1)
Absolute Input Range
+IN – (–IN)
+IN
–VREF
–0.3
–0.3
+VREF
AVDD + 0.3
AVDD + 0.3
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
–IN
Capacitance
Leakage Current
25
±1
ꢀ
ꢀ
pF
nA
SYSTEM PERFORMANCE
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error(3)
Common-Mode Rejection Ratio
14
15
Bits
LSB(2)
LSB
±4
±3
±1
±0.25
70
50
±8
±3
±1
±0.5
±0.12
ꢀ
±6
±2
±0.5
±1
mV
±0.25 % of FSR
At DC
VIN = 1Vp-p at 1MHz
dB
dB
ꢀ
Noise
60
±3
ꢀ
ꢀ
µVrms
LSB
Power-Supply Rejection
At FFFFH Output Code
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
1.6
0.4
ꢀ
ꢀ
µs
µs
Throughput Rate
Aperture Delay
Aperture Jitter
Small-Signal Bandwidth
Step Response
Overvoltage Recovery
500
ꢀ
kSPS
ns
ps
MHz
ns
ns
10
30
20
100
150
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(4)
SINAD
VIN = 5Vp-p at 100kHz
–90
81
94
–93
83
96
dB
dB
dB
V
V
IN = 5Vp-p at 100kHz
IN = 5Vp-p at 100kHz
Spurious-Free Dynamic Range
REFERENCE OUTPUT
Voltage
Source Current
Drift
IOUT = 0
Static Load
IOUT = 0
2.475
1.5
2.50
2.525
10
2.48
ꢀ
2.52
ꢀ
V
µA
ppm/°C
mV
25
0.6
ꢀ
ꢀ
Line Regulation
4.75V ≤ VCC ≤ 5.25V
REFERENCE INPUT
Range
2.55
ꢀ
ꢀ
V
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
VIH
CMOS
ꢀ
IIH ≤ +5µA
IIL ≤ –5µA
3.0
–0.3
4.0
+DVDD
0.8
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
V
VIL
VOH
IOH = –1.6mA
IOL = +1.6mA
VOL
0.4
ꢀ
ꢀ
Data Format
Binary Two’s Complement
POWER-SUPPLY REQUIREMENT
Power-Supply Voltage
+AVDD
4.75
4.75
5
5
5.25
5.25
25
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
+DVDD
Supply Current
Power Dissipation
fSAMPLE = 500kSPS
fSAMPLE = 500kSPS
17
85
mA
mW
125
TEMPERATURE RANGE
Specified Performance
–40
+85
ꢀ
ꢀ
°C
ꢀ Specifications same as ADS8323Y.
NOTES: (1) Ideal input span; does not include gain or offset error. (2) LSB means Least Signifcant Bit, with VREF equal to +2.5V; 1LSB = 76µV. (3) Measured relative
to an ideal, full-scale input (+In – (–In)) of 4.9999V. Thus, gain error includes the error of the internal voltage reference. (4) Calculated on the first nine harmonics
of the input frequency.
ADS8323
SBAS224B
3
www.ti.com
TIMING CHARACTERISTICS(1)(2)
All specifications typical at –40°C to +85°C, +DVDD = +5V.
ADS8323Y
TYP
ADS8323YB
TYP
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
Conversion Time
Acquisition Time
CLOCK Period
CLOCK HIGH Time
CLOCK LOW Time
CONVST LOW to CLOCK HIGH
CONVST LOW Time
CONVST LOW to BUSY HIGH
CS LOW to CONVST LOW
CONVST HIGH
CLOCK HIGH to BUSY LOW
CS HIGH
CS LOW to RD LOW
RD HIGH to CS HIGH
RD LOW Time
tCONV
tACQ
tC1
tW1
tW2
tD1
tW3
tD2
tD3
tW4
tD4
tW5
tD5
tD6
tW6
tD7
1.6
0.4
ꢀ
ꢀ
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
40
40
10
20
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
25
25
ꢀ
ꢀ
0
20
ꢀ
ꢀ
0
0
0
50
40
5
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
RD LOW to Data Valid
Data Hold from RD HIGH
BYTE Change to RD LOW(3)
RD HIGH Time
tD8
tD9
tW7
0
20
NOTES: (1) All input signals are specified with rise and fall times of 5ns, tR = tF = 5ns (10% to 90% of DVDD), and timed from a voltage level of (VIL + VIH)/2. (2)
See timing diagram, below. (3) BYTE is asynchronous; when BYTE is 0, bits 15 through 0 appear at DB15-DB0. When BYTE is 1, bits 15 through 8 appear on
DB7-DB0. RD may remain LOW between changes in BYTE.
TIMING DIAGRAM
tC1
tW2
tW1
CLOCK
1
2
3
4
5
17
18
19
20
1
2
3
4
17
18
19
20
Acquisition
Conversion
tCONV
Acquisition
tACQ
tD1
CONVST
tW3
tW4
BUSY
BYTE
tD2
tD4
tD3
tW5
CS
RD
tD5
tD9
tD6
tW6
tD7
tD8
tW7
DB15-D8
DB7-D0
Bits 15-8
Bits 7-0
Bits 15-8
Bits 7-0
FF
Bits 15-8
ADS8323
4
SBAS224B
www.ti.com
PIN CONFIGURATION
Top View
TQFP
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24 CS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
23 BYTE
22 RD
21 CONVST
20 CLOCK
19 DGND
18 +DVDD
17 BUSY
ADS8323
DB8
9
10 11 12 13 14 15 16
PIN ASSIGNMENTS
PIN
NAME
I/O DESCRIPTION
PIN
NAME
I/O DESCRIPTION
19
20
DGND
P
Digital Ground
1
2
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DO Data Bit 15 - MSB
DO Data Bit 14
DO Data Bit 13
DO Data Bit 12
DO Data Bit 11
DO Data Bit 10
DO Data Bit 9
DO Data Bit 8
DO Data Bit 7
DO Data Bit 6
DO Data Bit 5
DO Data Bit 4
DO Data Bit 3
DO Data Bit 2
DO Data Bit 1
DO Data Bit 0 - LSB
CLOCK
DI
An external CMOS compatible clock can be applied
to the CLOCK input to synchronize the conversion
process to an external source.
3
4
21
22
CONVST DI
Convert Start, Active LOW.
5
RD
DI
Synchronization pulse for the parallel output, Active
LOW.
6
3
23
BYTE
DI
Selects 8 most significant bits (LOW) or 8 least
significant bits (HIGH). Data valid on pins 9-16.
8
DB8
9
DB7
24
25
26
27
28
29
30
31
CS
–IN
DI
AI
AI
P
Chip Select, Active LOW.
Inverting Input Channel
Noninverting Input Channel
Analog Ground
10
11
12
13
14
15
16
17
18
DB6
DB5
+IN
DB4
AGND
+AVDD
NC
DB3
P
Analog Power Supply, +5VDC.
No Connect
DB2
—
—
AI
DB1
NC
No Connect
DB0
REFIN
Reference Input. When using the internal 2.5V
BUSY
+DVDD
DO HIGH when a conversion is in progress.
Digital Power Supply, +5VDC.
reference tie this pin directly to REFOUT
REFOUT AO Reference Output
.
P
32
NOTE: AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, and P is Power-Supply Connection.
ADS8323
SBAS224B
5
www.ti.com
TYPICAL CHARACTERISTICS
At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified.
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 100.1kHz, –0.2dB)
90
85
80
75
0
–30
–50
SNR
–70
–90
SINAD
–110
–130
1
10
100
250
0
25
50
75 100 125 150 175 200 225 250
Frequency (kHz)
Frequency (kHz)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
INL+ vs TEMPERATURE
100
95
90
85
80
75
–100
–95
–90
–85
–80
–75
0.3
0.2
0.1
0
22.9
15.3
7.6
SFDR
THD
0
–0.1
–7.6
1
10
100
250
–40
–20
0
20
40
60
80
100
Temperature (°C)
Frequency (kHz)
DNL+ vs TEMPERATURE
INL– vs TEMPERATURE
19.1
11.4
3.8
0.25
0.15
3.8
0.05
0
0
–3.8
–7.6
–11.4
–15.3
–0.05
–0.10
–0.15
–0.20
0.05
–3.8
–11.4
–0.05
–0.15
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
ADS8323
6
SBAS224B
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified.
DNL– vs TEMPERATURE
GAIN ERROR vs TEMPERATURE
0.6
0.4
45.8
30.5
15.3
0
10
8
762.9
610.4
457.8
305.2
152.6
0
0.2
6
0
4
–0.2
–0.4
–0.6
–15.3
–30.5
–45.8
2
0
–2
–152.6
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
VREF vs TEMPERATURE
IQ vs TEMPERATURE
2.0
1.0
26.2
0.8
0.4
13.1
0.0
0
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
–7.0
–8.0
–13.1
–26.2
–39.3
–52.4
–65.5
–78.6
–91.8
–104.9
0
–0.4
–0.8
–1.2
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
POSITIVE FULL-SCALE vs TEMPERATURE
BIPOLAR ZERO vs TEMPERATURE
5.4
412.0
335.7
253.4
183.1
106.8
30.5
1.4
1
106.8
76.3
4.4
3.4
0.6
0.2
–0.2
–0.6
–1
45.8
2.4
15.3
1.4
–15.3
–45.8
–76.3
0.4
–0.6
–45.8
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
Temperature (°C)
Temperature (°C)
ADS8323
SBAS224B
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At –40°C to +85°C, +DVDD = +AVDD = +5V, VREF = +2.5V, fSAMPLE = 500kSPS, and fCLK = 20 • fSAMPLE, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
NEGATIVE FULL-SCALE vs TEMPERATURE
1
0
76.3
4
3
2
0
1
0
–1
–2
–3
–4
–1
–2
–3
–4
–5
–76.3
–152.6
–228.9
–305.2
–381.5
2.5
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
–40
–20
0
20
40
60
80
100
Temperature (°C)
Decimal Code
NOTE: This mode of operation is described in more detail in
the Timing and Control section of this data sheet.
THEORY OF OPERATION
The ADS8323 is a high-speed Successive Approximation
Register (SAR) 16-bit ADC with an internal 2.5V bandgap
reference that operates from a single +5V supply. The input
is fully differential with a typical common-mode rejection of
70dB. The part accepts a differential analog input voltage in
the range of –VREF to +VREF, centered on the common-mode
voltage (see the Analog Input section). The part will also
accept bipolar input ranges when a level shift circuit is used
at the front end (see Figure 7). See Figure 1 for the basic
operating circuit for the ADS8323.
SAMPLE-AND-HOLD SECTION
The sample-and-hold on the ADS8323 allow the ADC to
accurately convert an input sine wave of full-scale amplitude
to 16-bit resolution. The input bandwidth of the sample-and-
hold is greater than the Nyquist rate (Nyquist equals one-half
of the sampling rate) of the ADC even when the ADC is
operated at its maximum throughput rate of 500kSPS. The
typical small-signal bandwidth of the sample-and-hold ampli-
fier is 20MHz. Typical aperture delay time, or the time it takes
for the ADS8323 to switch from the sample to the hold mode
following the negative edge of the CONVST signal, is 10ns.
The average delta of repeated aperture delay values is typi-
cally 30ps (also known as aperture jitter). These specifications
reflect the ability of the ADS8323 to capture AC input signals
accurately at the exact same moment in time.
The ADS8323 requires an external clock to run the conver-
sion process. This clock can vary between 25kHz (1.25kHz
throughput) and 10MHz (500kSPS throughput). The duty
cycle of the clock is unimportant as long as the minimum
HIGH and LOW times are at least 40ns and the clock period
is at least 100ns. The minimum clock frequency is governed
by the parasitic leakage of the Capacitive Digital-to-Analog
Converter (CDAC) capacitors internal to the ADS8323.
REFERENCE
The analog input is provided to two input pins, +IN and –IN.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. A conversion
is initiated on the ADS8323 by bringing CONVST (pin 21)
LOW for a minimum of 20ns. CONVST LOW places the
sample-and-hold amplifier in the hold state and the conver-
sion process is started. The BUSY output (pin 17) will go
HIGH when the conversion begins and will stay HIGH during
the conversion. While a conversion is in progress, both
inputs are disconnected from any internal function. When the
conversion result is latched into the output register, the
BUSY signal will go LOW. The data can be read from the
parallel output bus following the conversion by bringing both
RD and CS LOW.
If the internal reference is used, REFOUT (pin 32) should be
directly connected to REFIN (pin 31). The ADS8323 can
operate, however, with an external reference in the range of
1.5V to 2.55V for a corresponding full-scale range of 3.0V to
5.1V. The internal reference of the ADS8323 is double-
buffered. If the internal reference is used to drive an external
load, a buffer is provided between the reference and the load
applied to REFOUT (pin 32) (the internal reference can typi-
cally source or sink 10µA of current; compensation capaci-
tance should be at least 0.1µF to minimize noise). If an
external reference is used, the second buffer provides isola-
tion between the external reference and the CDAC. This
buffer is also used to recharge all of the capacitors of the
CDAC during conversion.
ADS8323
8
SBAS224B
www.ti.com
+5V Analog Supply
10µF
+
0.1µF
0.1µF
+
20pF
Analog Input
–
32 31 30 29 28 27 26 25
Chip Select
1
2
3
4
5
6
7
8
DB15
DB14
DB13
DB12
DB11
DB10
DB9
CS 24
BYTE 23
RD 22
Read Input
Conversion Start
Clock Input
CONVST 21
CLOCK 20
DGND 19
+DVDD 18
BUSY 17
ADS8323
Busy Output
DB8
9
10 11 12 13 14 15 16
FIGURE 1. Typical Circuit Configuration.
When the input is differential, the amplitude of the input is the
difference between the +IN and –IN input, or (+IN) – (–IN).
The peak-to-peak amplitude of each input is ±1/2VREF around
this common voltage. However, since the inputs are 180°
out-of-phase, the peak-to-peak amplitude of the differential
voltage is +VREF to –VREF. The value of VREF also determines
the range of the voltage that may be common to both inputs
(see Figure 5).
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8323: single-ended or differential, as shown in Figures 2
and 3. When the input is single-ended, the –IN input is held
at the common-mode voltage. The +IN input swings around
the same common voltage and the peak-to-peak amplitude is
the (common-mode + VREF) and the (common-mode – VREF).
The value of VREF determines the range over which the
common-mode voltage may vary (see Figure 4).
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. If matching is not observed, it may result in offset
error, which changes with temperature. Often, a small capacitor
(20pF) between the positive and negative inputs helps to match
their impedance.
–VREF to +VREF
peak-to-peak
ADS8323
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source imped-
ance. Essentially, the current into the ADS8323 charges the
internal capacitor array during the sampling period. After this
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to a 16-bit settling
level within 4 clock cycles (400ns), if the minimum acquisition
time is used. When the converter goes into the hold mode,
the input impedance is greater than 1GΩ.
Common
Voltage
Single-Ended Input
VREF
peak-to-peak
ADS8323
Common
VREF
Voltage
peak-to-peak
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AVDD + 0.3V.
Differential Input
FIGURE 2. Methods of Driving the ADS8323 either Single-
Ended or Differential.
ADS8323
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+IN
CM + VREF
CM Voltage
+VREF
–IN = CM Voltage
–VREF
t
CM – VREF
Single-Ended Inputs
+IN
+VREF
CM + 1/2VREF
CM Voltage
CM – 1/2VREF
–VREF
–IN
t
Differential Inputs
(+IN) + (–IN)
NOTES: Common-Mode Voltage (Differential Mode) =
, Common-Mode Voltage (Single-Ended Mode) = IN–.
2
The maximum differential voltage between +IN and –IN of the ADS8323 is VREF. See Figures 4 and 5 for a further
explanation of the common voltage range for single-ended and differential inputs.
FIGURE 3. Using the ADS8323 in the Single-Ended and Differential Input Modes.
5
4
5
4
AVDD = 5V
4.55
AVDD = 5V
4.025
3.8
3
3
2.75
Single-Ended Input
Differential Input
2.25
2
2
1.2
1
0.975
1
0.45
0
0
–1
–1
2.55
2.5
2.55
2.5
1.0
1.5
2.0
REF (V)
3.0
1.0
1.5
2.0
REF (V)
3.0
V
V
FIGURE 4. Single-Ended Input: Common-Mode Voltage
Range vs VREF
FIGURE 5. Differential Input: Common-Mode Voltage Range
vs VREF
.
.
ADS8323
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NOISE
R1
Figure 6 shows the transition noise of the ADS8323. A low-
level DC input was applied to the analog-input pins and the
converter was put through 8192 conversions. The digital
output of the ADC will vary in output code due to the internal
noise of the ADS8323. This is true for all 16-bit SAR-type
ADCs. The ADS8323, with five output codes for the σ distribu-
tion, will yield a < ±0.8LSB transition noise at 5V operation.
Remember that to achieve this low-noise performance, the
peak-to-peak noise of the input signal and reference must be
< 50µV.
4kΩ
+IN (pin 26)
OPA132
20kΩ
Bipolar
Input
–IN (pin 25)
ADS8323
R2
OPA353
REFOUT (pin 32)
2.5V
BIPOLAR INPUT
R1
R2
±10V
±5V
±2.5V
1kΩ
2kΩ
4kΩ
5kΩ
10kΩ
20kΩ
5052
FIGURE 7. Level Shift Circuit for Bipolar Input Ranges.
DIGITAL INTERFACE
TIMING AND CONTROL
1968
See the timing diagram in the Timing Characteristics section for
detailed information on timing signals and their requirements.
818
300
54
The ADS8323 uses an external clock (CLOCK, pin 20) that
controls the conversion rate of the CDAC. With a 10MHz
external clock, the ADC sampling rate is 500kSPS that
corresponds to a 2µs maximum throughput time.
0014
0015
0016
Code
0017
0018
FIGURE 6. Histogram of 8192 Conversions of a Low-Level
DC Input.
EXPLANATION OF CLOCK, BUSY AND BYTE PINS
CLOCK—An external clock must be provided for the
ADS8323. The maximum clock frequency is 10MHz and that
provides 500kSPS throughput. The minimum clock frequency
is 25kHz and that provides 1.25kHz throughput. The mini-
mum clock cycle is 100ns (see Timing Diagram, tC1), and
CLOCK must remain HIGH (see Timing Diagram, tW1) or
LOW (see Timing Diagram, tW2) for at least 40ns.
AVERAGING
Averaging the digital codes can compensate the noise of the ADC.
By averaging conversion results, transition noise will be reduced by
a factor of 1/√n, where n is the number of averages. For example,
averaging 4 conversion results will reduce the transition noise by
1/2 to ±0.4LSB. Averaging should only be used for input signals
with frequencies near DC. For AC signals, a digital filter can be
used to low-pass filter and decimate the output codes. This works
in a similar manner to averaging—for every decimation by 2, the
signal-to-noise ratio will improve 3dB.
BUSY—Initially BUSY output is LOW. Reading data from
output register or sampling the input analog signal will not
affect the state of the BUSY signal. After the CONVST input
goes LOW and conversion starts, a maximum of 25ns later
the BUSY output will go HIGH. That signal will stay HIGH
during conversion and will provide the status of the internal
ADC to the DSP or uC. At the end of conversion, on the rising
edge of 17th clock cycle, new data from the internal ADC is
latched into the output registers. The BUSY signal will go
LOW a maximum of 25ns later (see Timing Diagram, tD4).
BIPOLAR INPUTS
The differential inputs of the ADS8323 were designed to accept
bipolar inputs (–VREF and +VREF) around the common-mode
voltage, which corresponds to a 0V to 5V input range with a
2.5V reference. By using a simple op amp circuit featuring four
high-precision external resistors, the ADS8323 can be config-
ured to accept bipolar inputs. The conventional ±2.5V, ±5V, and
±10V input ranges could be interfaced to the ADS8323 using
the resistor values shown in Figure 7.
BYTE—The output data will appear as a full 16-bit word on
DB15-DB0 (MSB-LSB or D15-D0) if BYTE is LOW. If there is
only an 8-bit bus available on a board, the result may also be
read on an 8-bit bus by using only DB7-DB0. In this case, two
reads are necessary (see Timing Diagram). The first, as
before, leaving BYTE LOW and reading the 8 least significant
bits on DB7-DB0, then bringing BYTE HIGH. When BYTE is
HIGH, the upper 8 bits (D15-D8) will appear on DB7-DB0.
ADS8323
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START OF A CONVERSION AND READING DATA
LAYOUT
By bringing the CONVST signal LOW, the input data is
immediately placed in the hold mode (10ns). Although CS
must be LOW when CONVST goes LOW to initiate a conver-
sion. The conversion follows with the next rising edge of
CLOCK. If it is important to detect a hold command during a
certain clock cycle, then the falling edge of the CONVST
signal must occur at least 10ns before the rising edge of
CLOCK (see Timing Diagram, tD1). The CONVST signal can
remain LOW without initiating a new conversion. The CONVST
signal must be HIGH for at least 20ns (see Timing Diagram,
For optimum performance, care should be taken with the
physical layout of the ADS8323 circuitry. This is particularly
true if the CLOCK input is approaching the maximum through-
put rate.
As the ADS8323 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switch-
ing speed, the more difficult it will be to achieve good
performance from the converter.
t
W4) before it is brought LOW again and CONVST must stay
LOW for at least 20ns (see Timing Diagram, tW3). Once a
CONVST signal goes LOW, further impulses of this signal
are ignored until the conversion is finished or the part is
reset.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “windows”
in which large external transient voltages can affect the
conversion result. Such glitches might originate from switch-
ing power supplies, nearby digital logic, or high-power de-
vices.
When the conversion is finished (after 16 clock cycles) the
sampling switches will close and sample the new value. The
start of the next conversion must be delayed to allow the
input capacitor of the ADS8323 to be fully charged. This
delay time depends on the driving amplifier, but should be at
least 400ns. To gain acquisition time, the falling edge of
CONVST must take place just before the rising edge of
CLOCK (see Timing Diagram, tD1). One conversion cycle
requires 20 clock cycles. However, reading data during the
conversion or on a falling hold edge might cause a loss in
performance.
The degree of error in the digital output depends on the
reference voltage, layout, and the exact timing of the external
event. Their error can change if the external event changes
in time with respect to the CLOCK input.
On average, the ADS8323 draws very little current from an
external reference as the reference voltage is internally
buffered. If the reference voltage is external and originates
from an op amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation. A 0.1µF bypass
capacitor is recommended from pin 31 directly to ground.
Reading Data (RD, CS)—In general, the data outputs are in
tri-state. Both CS and RD must be LOW to enable these
outputs. RD and CS must stay LOW together for at least
40ns (see Timing Diagram, tD7) before the output data is
valid. RD must remain HIGH for at least 20ns (see Timing
Diagram, tW7) before bringing it back LOW for a subsequent
read command. 16 clock-cycles after the start of a conver-
sion (next rising edge of clock after the falling edge of
CONVST), the new data is latched into the output register
and the reading process can start again.
The AGND and DGND pins should be connected to a clean
ground point. In all cases, this should be the “analog” ground.
Avoid connections which are too close to the grounding point
of a microcontroller or digital signal processor. If required, run
a ground trace directly from the converter to the power-
supply entry point. The ideal layout will include an analog
ground plane dedicated to the converter and associated
analog circuitry.
CS being LOW tells the ADS8323 that the bus on the board
is assigned to the ADS8323. If an ADC shares a bus with
digital gates, there is a possibility that digital (high-frequency)
noise gets coupled into the ADC. If the bus is just used by the
ADS8323, CS can be hard-wired to ground. The output data
should not be read 125ns prior to the falling edge of CONVST
and 10ns after the falling edge.
As with the GND connections, VDD should be connected to a
+5V power supply plane, or trace, that is separate from the
connection for digital logic until they are connected at the
power entry point. Power to the ADS8323 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor is recommended. If needed, an even
larger capacitor and a 5Ω or 10Ω series resistor may be used
to low-pass filter a noisy supply. In some situations, addi-
tional bypassing may be required, such as a 100µF electro-
lytic capacitor, or even a Pi filter made up of inductors and
capacitors all designed to essentially low-pass filter the +5V
supply, removing the high-frequency noise.
The ADS8323’s output is in Binary Two’s Complement for-
mat (see Figure 8).
DESCRIPTION
ANALOG VALUE
2 • VREF
DIGITAL OUTPUT
Full-Scale Range
BINARY TWO’S COMPLEMENT
Least Significant
Bit (LSB)
2 • VREF/65535
BINARY CODE
HEX CODE
7FFF
+Full Scale
Midscale
+VREF – 1 LSB
0V
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
0000
Midscale – 1LSB
Zero
0V – 1 LSB
–VREF
FFFF
8000
TABLE I. Ideal Input Voltages and Output Codes.
ADS8323
12
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Binary Two’s
Complement
BTC
65535
0111 1111 1111 1111
65534
65533
0111 1111 1111 1110
0111 1111 1111 1101
32769
32768
32767
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
2
1
0
2.499962V
VNFS = VCM – VREF = 0V
2.500038V
VPFS = VCM + VREF = 5V
0.000038V
0.000076V
0.000152V
VPFS – 1LSB = 4.999924V
VBPZ = 2.5V
Unipolar Analog Input Voltage
4.999848V
1LSB = 76µV
VCM = 2.5V
16-BIT
V
REF = 2.5V
Bipolar Input, Binary Two’s Complement Output: (BTC)
Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM – VREF
Bipolar Zero Code
= VBPZ = 0000H, Vcode = VCM
Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (VCM + VREF) – 1LSB
FIGURE 8. Ideal Conversion Characteristics (Condition: Single-Ended. VCM = IN– = 2.5V, VREF = 2.5V).
ADS8323
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PACKAGE DRAWING
PBS (S-PQFP-G32)
MPQF027 – NOVEMBER 1995
PLASTIC QUAD FLATPACK
0,23
0,17
M
0,50
0,08
24
17
25
32
16
9
0,13 NOM
1
8
3,50 TYP
Gage Plane
5,05
SQ
4,95
0,25
7,10
SQ
0,10 MIN
6,90
0°–7°
0,70
0,40
1,05
0,95
Seating Plane
0,08
1,20 MAX
4087735/A 11/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
ADS8323
14
SBAS224B
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TQFP
TQFP
TQFP
TQFP
Drawing
ADS8323Y/250
ADS8323Y/2K
ADS8323YB/250
ADS8323YB/2K
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PBS
32
32
32
32
250
2000
250
None
None
None
None
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
PBS
PBS
PBS
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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相关型号：
ADS8324E/2K5G4
1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, GREEN, PLASTIC, MSOP-8
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