ADS8344NB [BB]
16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER; 16位8通道串行输出采样模拟数字转换器
| 型号： | ADS8344NB |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER |
| 文件： | 总13页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
ADS8344
¤
ADS8344
ADS8344
¤
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit, 8-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
● PIN FOR PIN WITH ADS7844
● SINGLE SUPPLY: 2.7V to 5V
The ADS8344 is an 8-channel, 16-bit sampling ana-
log-to-digital converter (ADC) with a synchronous
serial interface. Typical power dissipation is 10mW at
a 100kHz throughput rate and a +5V supply. The
reference voltage (VREF) can be varied between 500mV
and VCC, providing a corresponding input voltage
range of 0V to VREF. The device includes a shutdown
mode which reduces power dissipation to under 15µW.
The ADS8344 is guaranteed down to 2.7V operation.
● 8-CHANNEL SINGLE-ENDED OR
4-CHANNEL DIFFERENTIAL INPUT
● UP TO 100kHz CONVERSION RATE
● 84dB SINAD
● SERIAL INTERFACE
● QSOP-20 AND SSOP-20 PACKAGES
Low power, high speed, and on-board multiplexer
make the ADS8344 ideal for battery operated systems
such as personal digital assistants, portable multi-
channel data loggers, and measurement equipment.
The serial interface also provides low-cost isolation
for remote data acquisition. The ADS8344 is available
in a QSOP-20 or a SSOP-20 package and is guaran-
teed over the –40°C to +85°C temperature range.
APPLICATIONS
● DATA ACQUISITION
● TEST AND MEASUREMENT
● INDUSTRIAL PROCESS CONTROL
● PERSONAL DIGITAL ASSISTANTS
● BATTERY-POWERED SYSTEMS
CH0
CH1
CH2
SAR
DCLK
Eight
Channel
Multiplexer
CH3
CH4
CH5
CH6
CH7
COM
VREF
CS
Comparator
SHDN
DIN
Serial
Interface
and
CDAC
DOUT
Control
BUSY
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
Twx: 910-952-1111
•
Internet: http://www.burr-brown.com/
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©2000 Burr-Brown Corporation
Printed in U.S.A. April, 2000
PDS-1571A
SPECIFICATION: +5V
At TA = –40°C to +85°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8344E, N
TYP
ADS8344EB, NB
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Positive Input - Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VCC +0.2
+1.25
✻
✻
✻
✻
✻
✻
V
V
V
Negative Input
Capacitance
Leakage Current
25
±1
✻
✻
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Offset Error
16
✻
Bits
Bits
LSB
mV
14
15
8
±2
6
±1
Offset Error Match
Gain Error
Gain Error Match
Noise
1.2
4
✻
✻
±0.024
✻
LSB(1)
%
LSB
µVrms
LSB(1)
±0.05
4
1.0
20
3
✻
✻
✻
Power Supply Rejection
+4.75V < VCC < 5.25V
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
16
✻
✻
Clk Cycles
Clk Cycles
kHz
4.5
✻
Throughput Rate
100
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External Clock Frequency
500
30
100
2.4
✻
✻
✻
✻
ns
ns
ps
MHz
MHz
MHz
SHDN = VDD
0.024
0
2.4
2.4
✻
✻
✻
✻
Data Transfer Only
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
VIN = 5Vp-p at 10kHz
–90
86
92
✻
✻
✻
✻
dB
dB
dB
dB
100
REFERENCE INPUT
Range
Resistance
0.5
+VCC
100
3
✻
✻
✻
✻
V
DCLK Static
5
40
2.5
✻
✻
✻
✻
GΩ
µA
µA
µA
Input Current
fSAMPLE = 12.5kHz
DCLK Static
0.001
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
CMOS
✻
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
3.0
–0.3
3.5
5.5
+0.8
✻
✻
✻
✻
✻
V
V
V
V
VOL
0.4
✻
Data Format
Straight Binary
✻
✻
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
Specified Performance
4.75
5.25
2.0
✻
✻
✻
V
mA
µA
1.5
300
fSAMPLE = 100kHz
Power-Down Mode(3), CS = +VCC
3
✻
✻
µA
mW
Power Dissipation
7.5
10
TEMPERATURE RANGE
Specified Performance
–40
+85
✻
✻
°C
✻ Same specifications as ADS8344E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
ADS8344
2
SPECIFICATION: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8344E, N
TYP
ADS8344EB, NB
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Absolute Input Range
Positive Input - Negative Input
Positive Input
0
–0.2
–0.2
VREF
+VCC +0.2
+0.2
✻
✻
✻
✻
✻
✻
V
V
V
Negative Input
Capacitance
Leakage Current
25
±1
✻
✻
pF
µA
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Noise
16
✻
Bits
Bits
LSB
mV
LSB
% of FSR
LSB
µVrms
LSB(1)
14
15
12
±1
4
±0.05
4
8
0.5
✻
1.2
✻
±0.0024
1
20
3
✻
✻
✻
✻
Power Supply Rejection
+2.7 < VCC < +3.3V
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
16
✻
✻
Clk Cycles
Clk Cycles
kHz
4.5
✻
Throughput Rate
100
Multiplexer Settling Time
Aperture Delay
Aperture Jitter
Internal Clock Frequency
External Clock Frequency
500
30
100
2.4
✻
✻
✻
✻
ns
ns
ps
MHz
MHz
MHz
SHDN = VDD
0.024
0
2.0
2.0
✻
✻
✻
✻
Data Transfer Only
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2)
Signal-to-(Noise + Distortion)
Spurious Free Dynamic Range
Channel-to-Channel Isolation
VIN = 2.5Vp-p at 1kHz
–90
86
92
✻
✻
✻
✻
dB
dB
dB
dB
V
V
IN = 2.5Vp-p at 1kHz
IN = 2.5Vp-p at 1kHz
VIN = 2.5Vp-p at 10kHz
100
REFERENCE INPUT
Range
Resistance
0.5
+VCC
40
✻
✻
✻
✻
V
DCLK Static
5
13
2.5
✻
✻
✻
✻
GΩ
µA
µA
µA
Input Current
fSAMPLE = 12.5kHz
DCLK Static
0.001
3
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
CMOS
✻
| IIH | ≤ +5µA
| IIL | ≤ +5µA
IOH = –250µA
IOL = 250µA
+VCC • 0.7
–0.3
+VCC • 0.8
5.5
+0.8
✻
✻
✻
✻
✻
V
V
V
V
VOL
0.4
✻
Data Format
Straight Binary
✻
POWER SUPPLY REQUIREMENTS
+VCC
Quiescent Current
Specified Performance
2.7
3.6
1.85
✻
✻
✻
V
mA
µA
µA
mW
1.2
220
✻
✻
fSAMPLE = 100kHz
Power-Down Mode(3), CS = +VCC
3
5
✻
✻
Power Dissipation
3.2
TEMPERATURE RANGE
Specified Performance
–40
+85
✻
✻
°C
✻ Same specifications as ADS8344E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
®
3
ADS8344
PIN DESCRIPTIONS
PIN CONFIGURATION
Top View
PIN
NAME
DESCRIPTION
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Analog Input Channel 0.
Analog Input Channel 1.
Analog Input Channel 2.
Analog Input Channel 3.
Analog Input Channel 4.
Analog Input Channel 5.
Analog Input Channel 6.
Analog Input Channel 7.
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
20 +VCC
19 DCLK
18 CS
17 DIN
Ground reference for analog inputs. Sets zero code
voltage in single ended mode. Connect this pin to ground
or ground reference point.
16 BUSY
15 DOUT
14 GND
13 GND
12 +VCC
11 VREF
ADS8344
10
11
SHDN
VREF
Shutdown. When LOW, the device enters a very low
power shutdown mode.
Voltage Reference Input. See Specification Table for
ranges.
12
13
14
15
+VCC
GND
GND
DOUT
Power Supply, 2.7V to 5V.
Ground
SHDN 10
Ground
Serial Data Output. Data is shifted on the falling edge of
DCLK. This output is high impedance when
CS is high.
16
BUSY
Busy Output. Busy goes low when the DIN control bits
are being read and also when the device is converting.
The Output is high impedance when CS is High.
Serial Data Input. If CS is LOW, data is latched on rising
ABSOLUTE MAXIMUM RATINGS(1)
17
18
DIN
CS
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
edge of DCLK
.
Chip Select Input. Active LOW. Data will not be clocked
into DIN unless CS is low. When CS is high DOUT is high
impedance.
19
20
CLK
External Clock Input. The clock speed determines the
conversion rate by the equation fCLK = 24 • fSAMPLE
.
+VCC
Power Supply
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi-
cations.
PACKAGE/ORDERING INFORMATION
MINIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
GAIN ERROR
(%)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
DRAWING
NUMBER
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
ADS8344E
8
"
"
"
6
"
±0.05
"
"
"
–40°C to +85°C
QSOP-20
349
"
334
"
349
"
334
"
ADS8344E
ADS8344E/2K5
ADS8344N
ADS8344N/1K
ADS8344EB
ADS8344EB/2K5
ADS8344NB
ADS8344NB/1K
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
"
"
"
"
"
ADS8344N
SSOP-20
"
"
ADS8344EB
±0.024
–40°C to +85°C
QSOP-20
"
"
"
"
"
"
"
"
ADS8344NB
"
"
"
SSOP-20
"
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “ADS8344E/2K5” will get a single 2500-piece Tape and Reel.
®
ADS8344
4
TYPICAL PERFORMANCE CURVES: +5V
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
10
20
30
40
50
0
10
20
30
40
50
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
100
90
80
70
60
–100
–90
–80
–70
–60
100
90
80
70
60
SNR
SFDR
THD(1)
SINAD
NOTE: (1) First Nine Harmonics
of the Input Frequency
1
10
100
1
10
100
Frequency (kHz)
Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.4
0.2
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
fIN = 9.985kHz, –0.2dB
0.0
–0.2
–0.4
–0.6
–0.8
–40
–25
0
20
50
75
100
1
10
100
Temperature (˚C)
Frequency (kHz)
®
5
ADS8344
TYPICAL PERFORMANCE CURVES: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
INTEGRAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
2
1
3
2
0
1
–1
–2
–3
–4
0
–1
–2
–3
0000H
4000H
8000H
C000H
FFFFH
0000H
4000H
8000H
C000H
FFFFH
Output Code
Output Code
TYPICAL PERFORMANCE CURVES: +2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
10
20
30
40
50
0
10
20
30
40
50
Frequency (kHz)
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
100
90
80
70
60
50
100
90
80
70
60
50
–100
SNR
–90
–80
–70
–60
–50
SFDR
THD(1)
SINAD
NOTE: (1) First Nine Harmonics
of the Input Frequency
1
10
100
1
10
100
Frequency (kHz)
Frequency (kHz)
®
ADS8344
6
TYPICAL PERFORMANCE CURVES: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
2.0
1.5
15
14
13
12
11
10
9
fIN = 9.985kHz, –0.2dB
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
8
–40
–25
0
20
50
75
100
1
10
100
Temperature (˚C)
Frequency (kHz)
INTEGRAL LINEARITY ERROR vs CODE
DIFFERENTIAL LINEARITY ERROR vs CODE
3
2
3
2
1
1
0
0
–1
–2
–3
–1
–2
–3
0000H
4000H
8000H
C000H
FFFFH
0000H
4000H
8000H
C000H
FFFFH
Output Code
Output Code
SUPPLY CURRENT vs +VSS
fSAMPLE = 100kHz, VREF = +VSS
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.5
3.0
3.5
4.0
4.5
5.0
+VSS (V)
®
7
ADS8344
ANALOG INPUT
THEORY OF OPERATION
Figure 2 shows a block diagram of the input multiplexer on
the ADS8344. The differential input of the converter is
derived from one of the eight inputs in reference to the COM
pin or four of the eight inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
The ADS8344 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6µs CMOS process.
The basic operation of the ADS8344 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 500mV and
+VCC. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS8344.
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (see Figure 2) is
captured on the internal capacitor array. The voltage on the
–IN input is limited between –0.2V and 1.25V, allowing the
input to reject small signals which are common to both the
+IN and –IN input. The +IN input has a range of –0.2V to
+VCC + 0.2V.
The analog input to the converter is differential and is
provided via an eight-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using four of the
eight input channels (CH0 - CH7). The particular configura-
tion is selectable via the digital interface.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typi-
A2
A1
A0
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
A2
A1
A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+IN
–IN
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
–IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
–IN
–IN
+IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
–IN
+IN
+IN
+IN
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
TABLE II. Differential Channel Control (SGL/DIF LOW).
+2.7V to +5V
ADS8344
+VCC 20
1µF to 10µF
0.1µF
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
Serial/Conversion Clock
Chip Select
DCLK 19
CS 18
Single-ended
or differential
analog inputs
Serial Data In
DIN 17
BUSY 16
DOUT 15
GND 14
GND 13
+VCC 12
VREF 11
Serial Data Out
10 SHDN
1µF to 10µF
FIGURE 1. Basic Operation of the ADS8344.
®
ADS8344
8
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
500mV, the LSB size is 7.6µV. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
A2-A0
(shown 00oB)(1)
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low noise, low ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
+IN
Converter
–IN
The voltage into the VREF input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC)
portion of the ADS8344. Typically, the input current is
13µA with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
COM
DIGITAL INTERFACE
SGL/DIF
(shown HIGH)
NOTE: (1) See Truth Tables, Table I
and Table II for address coding.
The ADS8344 has a four-wire serial interface compatible
with several microprocessor families (note that the digital
inputs are over-voltage tolerant up to +5.5V, regardless of
+VCC). Figure 3 shows the typical operation of the ADS8344
digital interface.
FIGURE 2. Simplified Diagram of the Analog Input.
cally 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion
rate.
Most microprocessors communicate using 8-bit transfers;
the ADS8344 can complete a conversion with three such
transfers, for a total of 24 clock cycles on the DCLK input,
provided the timing is as shown in Figure 3.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After four more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample/hold goes into the hold mode.
The next sixteen clock cycles accomplish the actual A/D
conversion.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8344 will operate with a reference in the range of
100mV to +VCC. Keep in mind that the analog input is the
difference between the +IN input and the –IN input as shown
in Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH7) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
Control Byte
Also, shown in Figure 3 is the placement and order of the
control bits within the control byte. Table III and IV give
detailed information about these bits. The first bit, the “S”
bit, must always be HIGH and indicates the start of the
control byte. The ADS8344 will ignore inputs on the DIN
pin until the start bit is detected. The next three bits (A2-A0)
select the active input channel or channels of the input
multiplexer (see Tables I and II and Figure 2).
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is re-
duced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 65536. Any offset or gain error inherent in the
A/D converter will appear to increase, in terms of LSB size,
as the reference voltage is reduced. For example, if the offset
of a given converter is 2 LSBs with a 2.5V reference, then it
will typically be 10 LSBs with a 0.5V reference. In each case,
the actual offset of the device is the same, 76.3µV.
The SGL/DIF-bit controls the multiplexer input mode: ei-
ther single-ended mode, the selected input channel is refer-
enced to the COM pin. In differential mode, the two selected
®
9
ADS8344
CS
DCLK
DIN
tACQ
1
8
1
8
1
8
1
8
1
Idle
Acquire
Conversion
Idle
Acquire
Conversion
SGL/
DIF
SGL/
DIF
S
A2 A1 A0
PD1 PD0
S
A2 A1 A0
PD1 PD0
(START)
(START)
BUSY
DOUT
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Zero Filled...
15 14
(MSB)
(MSB)
(LSB)
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
inputs provide a differential input. See Tables I and II and
BIT
NAME
DESCRIPTION
Figure 2 for more information. The last two bits (PD1 - PD0)
select the power-down mode and clock mode as shown in
Table V. If both PD1 and PD0 are HIGH, the device is
always powered up. If both PD1 and PD0 are low, the device
enters a power-down mode between conversions. When a
new conversion is initiated, the device will resume normal
operation instantly—no delay is needed to allow the device
to power up and the very first conversion will be valid.
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN.
6 - 4
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input
as detailed in Tables I and II.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input as detailed in Tables I and II.
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
details.
Clock Modes
The ADS8344 can be used with an external serial clock or
an internal clock to perform the successive-approximation
conversion. In both clock modes, the external clock shifts
data in and out of the device. Internal clock mode is selected
when PD1 is HIGH and PD0 is LOW.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
PD0
0
PD1
0
Description
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
External Clock Mode
In external clock mode, the external clock not only shifts
data in and out of the ADS8344, it also controls the A/D
conversion steps. BUSY will go HIGH for one clock period
after the last bit of the control byte is shifted in. Successive-
approximation bit decisions are made and appear at DOUT
on each of the next 16 SCLK falling edges (Figure 3). Figure
4 shows the BUSY timing in external clock mode.
0
1
1
1
0
1
Internal clock mode.
Reserved for future use.
No power-down between conversions, device al-
ways powered.
TABLE V. Power-Down Selection.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
S
A2
A1
A0
—
SGL/DIF PD1
PD0
TABLE III. Order of the Control Bits in the Control Byte.
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
15
14
FIGURE 4. Detailed Timing Diagram.
®
ADS8344
10
Since one clock cycle of the serial clock is consumed with
BUSY going high (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits of
data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
If CS is LOW when BUSY goes LOW following a conver-
sion, the next falling edge of the external serial clock will
write out the MSB on the DOUT line. The remaining bits
(D14-D0) will be clocked out on each successive clock cycle
following the MSB. If CS is HIGH when BUSY goes LOW
then the DOUT line will remain in tri-state until CS goes
LOW (Figure 6). CS does not need to remain LOW once a
conversion has started. Note that BUSY is not tri-stated
when CS goes HIGH in internal clock mode.
There are two ways of handling this requirement. One is
shown in Figure 3, where the beginning of the next control
byte appears at the same time the LSB is being clocked out
of the ADS8344. This method allows for maximum through-
put and 24 clock cycles per conversion.
Data can be shifted in and out of the ADS8344 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition
time tACQ, is kept above 1.7µs.
The other method is shown in Figure 5, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when CS goes high; after the next CS
falling edge, BUSY will go LOW.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for
the digital interface of the ADS8344.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
Internal Clock Mode
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
1.5
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
In internal clock mode, the ADS8344 generates its own
conversion clock internally. This relieves the microproces-
sor from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate up to 2.4MHz. BUSY goes
HIGH at the start of conversion and then returns LOW when
the conversion is complete. During the conversion, BUSY
will remain LOW for a maximum of 8µs. Also, during the
conversion, SCLK should remain LOW to achieve the best
noise performance. The conversion result is stored in an
internal register; the data may be clocked out of this register
any time after the conversion is complete.
tDH
tDO
tDV
200
200
200
tTR
tCSS
tCSH
tCH
100
0
200
200
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
tBDV
tBTR
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
CS
tACQ
DCLK
DIN
1
8
1
8
1
8
1
8
Idle
A2 A1 A0
Acquire
Conversion
Idle
SGL/
DIF
S
PD1 PD0
(START)
BUSY
DOUT
Zero Filled...
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
(MSB)
(LSB)
FIGURE 5.
CS
DCLK
DIN
tACQ
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Idle
Acquire
Conversion
SGL/
PD1 PD0
S
A2 A1 A0
DIF
(START)
BUSY
DOUT
15
(MSB)
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Zero Filled...
(LSB)
FIGURE 6.
®
11
ADS8344
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK fre-
quency is kept at the maximum rate during a conversion, but
conversions are simply done less often, then the difference
between the two modes is dramatic. In the latter case, the
converter spends an increasing percentage of its time in
power-down mode (assuming the auto power-down mode is
active).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
1.7
50
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
tDO
tDV
100
70
tTR
70
tCSS
tCSH
tCH
50
0
If DCLK is active and CS is LOW while the ADS8344 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH.
150
150
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
100
70
tBDV
tBTR
70
Operating the ADS8344 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time “penalty” on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
TABLE VII. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
Data Format
The ADS8344 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
NOISE
The noise floor of the ADS8344 itself is extremely low, as
can be seen from Figures 8 thru 11, and is much lower than
competing A/D converters. The ADS8344 was tested at both
5V and 2.7V and in both the internal and external clock
modes. A low level DC input was applied to the analog input
pins and the converter was put through 5,000 conversions.
The digital output of the A/D converter will vary in output
code due to the internal noise of the ADS8344. This is true
for all 16-bit SAR-type A/D converters. Using a histogram
to plot the output codes, the distribution should appear bell-
shaped with the peak of the bell curve representing the
nominal code for the input value. The ±1σ, ±2σ, and ±3σ
distributions will represent the 68.3%, 95.5%, and 99.7%,
respectively, of all codes. The transition noise can be calcu-
lated by dividing the number of codes measured by 6 and
this will yield the ±3σ distribution or 99.7% of all codes.
Statistically, up to 3 codes could fall outside the distribution
when executing 1000 conversions. The ADS8344, with < 3
output codes for the ±3σ distribution, will yield a < ±0.5LSB
transition noise at 5V operation. Remember, to achieve this
low noise performance, the peak-to-peak noise of the input
signal and reference must be < 50µV.
FS = Full-Scale Voltage = VREF
1 LSB = VREF/65,536
1 LSB
11...111
11...110
11...101
00...010
00...001
00...000
0V
FS – 1 LSB
Input Voltage(1) (V)
NOTE(1): Voltage at converter input, after
multiplexer: +IN–(–IN). (See Figure 2.)
FIGURE 7. Ideal Input Voltages and Output Codes.
POWER DISSIPATION
4561
There are three power modes for the ADS8344: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The effects of these modes
varies depending on how the ADS8344 is being operated.
For example, at full conversion rate and 24-clocks per
conversion, there is very little difference between full power
mode and auto power-down, a shutdown (SHDN LOW) will
not lower power dissipation
When operating at full-speed and 24-clocks per conversion
(as shown in Figure 3), the ADS8344 spends most of its time
acquiring or converting. There is little time for auto power-
down, assuming that this mode is active. Thus, the differ-
ence between full power mode and auto power-down is
negligible. If the conversion rate is decreased by simply
0
242
197
0
7FFD
7FFE
7FFF
Code
8000
8001
FIGURE 8. Histogram of 5000 Conversions of a DC Input at the
Code Transition, 5V operation external clock mode.
®
ADS8344
12
sion results will reduce the transition noise by 1/2 to ±0.25
LSBs. Averaging should only be used for input signals with
frequencies near DC.
4507
For AC signals, a digital filter can be used to low pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8344 circuitry. This is particu-
larly true if the reference voltage is low and/or the conver-
sion rate is high.
0
251
242
0
7FFD
7FFE
7FFF
Code
8000
8001
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
FIGURE 9. Histogram of 5000 Conversions of a DC Input at the
Code Center, 5V operation internal clock mode.
3511
666
721
With this in mind, power to the ADS8344 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may
be used to lowpass filter a noisy supply.
50
52
7FFD
7FFE
7FFF
Code
8000
8001
The reference should be similarly bypassed with a 0.1µF
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8344 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
FIGURE 10. Histogram of 5000 Conversions of a DC Input at the
Code Transition, 2.7V operation external clock mode.
2868
The ADS8344 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high fre-
quency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
1137
858
78
59
7FFD
7FFE
7FFF
Code
8000
8001
The GND pin should be connected to a clean ground point.
In many cases, this will be the “analog” ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
FIGURE 11. Histogram of 5000 Conversions of a DC Input at the
Code Center, 2.7V operation internal clock mode.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/√n, where n
is the number of averages. For example, averaging 4 conver-
®
13
ADS8344
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