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ADS8345E/2K5 [TI]

16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER; 16位8通道串行输出采样模拟数字转换器
ADS8345E/2K5
型号： ADS8345E/2K5
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
16位8通道串行输出采样模拟数字转换器

转换器 光电二极管
文件： 总20页 (文件大小：503K)
中文：  中文翻译
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ADS8345  
A
®
D
S
8
3
4
5
ADS8345  
®
SBAS177C – FEBRUARY 2001 – REVISED APRIL 2003  
16-Bit, 8-Channel Serial Output Sampling  
ANALOG-TO-DIGITAL CONVERTER  
DESCRIPTION  
FEATURES  
ꢀ BIPOLAR INPUT RANGE  
The ADS8345 is an 8-channel, 16-bit, sampling  
Analog-to-Digital (A/D) converter with a synchronous serial  
interface. Typical power dissipation is 8mW at a 100kHz  
throughput rate and a +5V supply. The reference voltage  
(VREF) can be varied between 500mV and VCC/2, providing a  
corresponding input voltage range of ±VREF. The device  
includes a shutdown mode which reduces power dissipation  
to under 15µW. The ADS8345 is ensured down to 2.7V  
operation.  
ꢀ PIN-FOR-PIN COMPATIBLE WITH THE  
ADS7844 AND ADS8344  
ꢀ SINGLE SUPPLY: 2.7V to 5V  
ꢀ 8-CHANNEL SINGLE-ENDED OR  
4-CHANNEL DIFFERENTIAL INPUT  
ꢀ UP TO 100kHz CONVERSION RATE  
ꢀ 85dB SINAD  
Low-power, high-speed, and an onboard multiplexer make  
the ADS8345 ideal for battery-operated systems such as  
personal digital assistants, portable multi-channel data log-  
gers, and measurement equipment. The serial interface also  
provides low-cost isolation for remote data acquisition. The  
ADS8345 is available in a QSOP-20 or SSOP-20 package  
and is ensured over the –40°C to +85°C temperature range.  
ꢀ SERIAL INTERFACE  
ꢀ QSOP-20 AND SSOP-20 PACKAGES  
APPLICATIONS  
ꢀ DATA ACQUISITION  
ꢀ TEST AND MEASUREMENT EQUIPMENT  
ꢀ INDUSTRIAL PROCESS CONTROL  
ꢀ PERSONAL DIGITAL ASSISTANTS  
ꢀ BATTERY-POWERED SYSTEMS  
CH0  
CH1  
CH2  
SAR  
DCLK  
CH3  
CH4  
CH5  
CH6  
CH7  
COM  
VREF  
8-Channel  
Multiplexer  
CS  
Comparator  
SHDN  
DIN  
Serial  
Interface  
and  
CDAC  
DOUT  
Control  
BUSY  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001-2003, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
www.ti.com  
ABSOLUTE MAXIMUM RATINGS(1)  
+VCC to GND ........................................................................ –0.3V to +6V  
Analog Inputs to GND .......................................... –0.3V to (+VCC) + 0.3V  
ELECTROSTATIC  
DISCHARGE SENSITIVITY  
This integrated circuit can be damaged by ESD. Texas Instru-  
ments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling  
and installation procedures can cause damage.  
Digital Inputs to GND ........................................................... –0.3V to +6V  
Power Dissipation .......................................................................... 250mW  
Maximum Junction Temperature ................................................... +150°C  
Operating Temperature Range ........................................–40°C to +85°C  
Storage Temperature Range .........................................–65°C to +150°C  
Lead Temperature (soldering, 10s)............................................... +300°C  
ESD damage can range from subtle performance degrada-  
tion to complete device failure. Precision integrated circuits  
may be more susceptible to damage because very small  
parametric changes could cause the device not to meet its  
published specifications.  
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”  
may cause permanent damage to the device. Exposure to absolute maximum  
conditions for extended periods may affect device reliability.  
PACKAGE/ORDERING INFORMATION  
MAXIMUM  
INTEGRAL  
LINEARITY  
ERROR (LSB)  
MAXIMUM  
GAIN  
ERROR (%)  
SPECIFIED  
TEMPERATURE  
RANGE  
PACKAGE  
DESIGNATOR(1)  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
PACKAGE-LEAD  
ADS8345E  
8
"
±0.05  
QSOP-20  
DBQ  
"
–40°C to +85°C  
ADS8345E  
ADS8345E/2K5  
ADS8345N  
Rails, 100  
Tape and Reel, 2500  
Rails, 100  
"
"
"
"
ADS8345N  
8
±0.05  
SSOP-20  
DB  
–40°C to +85°C  
"
"
"
"
"
"
ADS8345N/1K  
ADS8345EB  
Tape and Reel, 1000  
Rails, 100  
ADS8345EB  
6
"
±0.024  
QSOP-20  
DBQ  
"
–40°C to +85°C  
"
"
±0.024  
"
"
"
ADS8345EB/2K5 Tape and Reel, 2500  
ADS8345NB  
6
SSOP-20  
DB  
–40°C to +85°C  
ADS8345NB  
Rails, 100  
"
"
"
"
"
ADS8345NB/1K  
Tape and Reel, 1000  
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.  
PIN DESCRIPTIONS  
PIN CONFIGURATION  
PIN  
NAME  
DESCRIPTION  
Top View  
SSOP  
1
2
3
4
5
6
7
8
9
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
COM  
Analog Input Channel 0  
Analog Input Channel 1  
Analog Input Channel 2  
Analog Input Channel 3  
Analog Input Channel 4  
Analog Input Channel 5  
Analog Input Channel 6  
Analog Input Channel 7  
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
COM  
1
2
3
4
5
6
7
8
9
20 +VCC  
19 DCLK  
18 CS  
Common reference for analog inputs. This pin is typically  
connected to VREF  
.
10  
11  
SHDN  
VREF  
Shutdown. When LOW, the device enters a very  
low-power shutdown mode.  
17 DIN  
Voltage Reference Input. See the Electrical Character-  
istics Table for ranges.  
16 BUSY  
15 DOUT  
14 GND  
13 GND  
12 +VCC  
11 VREF  
ADS8345  
12  
13  
14  
15  
+VCC  
GND  
GND  
DOUT  
Power Supply, 2.7V to 5.25V  
Ground  
Ground  
Serial Data Output. Data is shifted on the falling edge of  
DCLK. This output is high impedance when CS is HIGH.  
Busy Output. Busy goes LOW when the DIN control bits  
are being read and also when the device is converting.  
The Output is high impedance when CS is HIGH.  
Serial Data Input. If CS is LOW, data is latched on rising  
16  
BUSY  
SHDN 10  
17  
18  
DIN  
CS  
edge of DCLK  
.
Chip Select Input; Active LOW. Data will not be clocked  
into DIN unless CS is LOW. When CS is HIGH, DOUT is  
high impedance.  
19  
20  
DCLK  
+VCC  
External Clock Input. The clock speed determines the  
conversion rate by the equation fDCLK = 24 • fSAMPLE  
.
Power Supply  
2
ADS8345  
SBAS177C  
www.ti.com  
ELECTRICAL CHARACTERISTICS: +5V  
At TA = –40°C to +85°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
ADS8345E, N  
ADS8345EB, NB  
PARAMETER  
RESOLUTION  
CONDITIONS  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNITS  
16  
ꢀ
Bits  
ANALOG INPUT  
Full-Scale Input Span  
Absolute Input Range  
Positive Input-Negative Input  
–VREF  
–0.2  
–0.2  
+VREF  
+VCC + 0.2  
+VCC + 0.2  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
+IN  
–IN  
Capacitance  
Leakage Current  
25  
±1  
ꢀ
ꢀ
pF  
µA  
SYSTEM PERFORMANCE  
No Missing Codes  
Integral Linearity Error  
Bipolar Error  
Bipolar Error Match  
Gain Error  
Gain Error Match  
Noise  
Power-Supply Rejection  
14  
15  
Bits  
LSB  
mV  
LSB(1)  
%
LSB  
±8  
±2  
8
±0.05  
4
±6  
±1  
ꢀ
±0.024  
ꢀ
4
ꢀ
1.0  
20  
3
ꢀ
ꢀ
ꢀ
µVrms  
LSB(1)  
+4.75V < VCC < 5.25V  
SAMPLING DYNAMICS  
Conversion Time  
Acquisition Time  
16  
ꢀ
ꢀ
CLK Cycles  
CLK Cycles  
kHz  
4.5  
ꢀ
Throughput Rate  
100  
Multiplexer Settling Time  
Aperture Delay  
Aperture Jitter  
Internal Clock Frequency  
External Clock Frequency  
500  
30  
100  
2.4  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
ps  
MHz  
MHz  
MHz  
SHDN = VDD  
0.024  
0
2.4  
2.4  
ꢀ
ꢀ
ꢀ
ꢀ
Data Transfer Only  
DYNAMIC CHARACTERISTICS  
Total Harmonic Distortion(2)  
Signal-to-(Noise + Distortion)  
Spurious-Free Dynamic Range  
Channel-to-Channel Isolation  
VIN = 5Vp-p at 10kHz  
VIN = 5Vp-p at 10kHz  
VIN = 5Vp-p at 10kHz  
VIN = 5Vp-p at 10kHz  
–96  
85  
98  
ꢀ
ꢀ
ꢀ
ꢀ
dB  
dB  
dB  
dB  
105  
REFERENCE INPUT  
Range  
0.5  
+VCC/2  
ꢀ
ꢀ
V
Resistance  
Input Current  
DCLK Static  
DCLK Static  
5
40  
0.001  
ꢀ
ꢀ
ꢀ
GΩ  
µA  
µA  
100  
3
ꢀ
ꢀ
DIGITAL INPUT/OUTPUT  
Logic Family  
Logic Levels  
VIH  
VIL  
VOH  
CMOS  
ꢀ
| IIH | ≤ +5µA  
| IIL | ≤ +5µA  
IOH = –250µA  
IOL = 250µA  
3.0  
–0.3  
3.5  
5.5  
+0.8  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
V
VOL  
0.4  
ꢀ
Data Format  
Binary Two’s Complement  
ꢀ
POWER-SUPPLY REQUIREMENTS  
+VCC  
Quiescent Current  
Specified Performance  
4.75  
5.25  
2.0  
ꢀ
ꢀ
ꢀ
V
1.5  
1.2  
ꢀ
ꢀ
mA  
mA  
µA  
fSAMPLE = 10kHz  
Power-Down Mode(3), CS = +VCC  
3
10  
ꢀ
ꢀ
Power Dissipation  
7.5  
ꢀ
mW  
TEMPERATURE RANGE  
Specified Performance  
–40  
+85  
ꢀ
ꢀ
°C  
ꢀ Same specifications as ADS8345E, N.  
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode  
(PD1 = PD0 = 0) active or SHDN = GND.  
3
ADS8345  
SBAS177C  
www.ti.com  
ELECTRICAL CHARACTERISTICS: +2.7V  
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
ADS8345E, N  
ADS8345EB, NB  
PARAMETER  
RESOLUTION  
CONDITIONS  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNITS  
16  
ꢀ
Bits  
ANALOG INPUT  
Full-Scale Input Span  
Absolute Input Range  
Positive Input-Negative Input  
–VREF  
–0.2  
–0.2  
+VREF  
+VCC + 0.2  
+VCC + 0.2  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
+IN  
–IN  
Capacitance  
Leakage Current  
25  
±1  
ꢀ
ꢀ
pF  
µA  
SYSTEM PERFORMANCE  
No Missing Codes  
Integral Linearity Error  
Bipolar Error  
Bipolar Error Match  
Gain Error  
Gain Error Match  
Noise  
Power-Supply Rejection  
14  
15  
Bits  
LSB  
mV  
LSB  
% of FSR  
LSB  
±8  
±1.0  
4
±0.05  
4
±6  
±0.5  
ꢀ
±0.024  
ꢀ
2
ꢀ
1
20  
3
ꢀ
ꢀ
ꢀ
µVrms  
LSB(1)  
+2.7 < VCC < +3.3V  
SAMPLING DYNAMICS  
Conversion Time  
Acquisition Time  
16  
ꢀ
ꢀ
CLK Cycles  
CLK Cycles  
kHz  
4.5  
ꢀ
Throughput Rate  
100  
Multiplexer Settling Time  
Aperture Delay  
Aperture Jitter  
Internal Clock Frequency  
External Clock Frequency  
500  
30  
100  
2.4  
ꢀ
ꢀ
ꢀ
ꢀ
ns  
ns  
ps  
MHz  
MHz  
MHz  
MHz  
SHDN = VDD  
0.024  
0.024  
0
2.4  
2.0  
2.4  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
When used with Internal Clock  
Data Transfer Only  
DYNAMIC CHARACTERISTICS  
Total Harmonic Distortion(2)  
Signal-to-(Noise + Distortion)  
Spurious-Free Dynamic Range  
Channel-to-Channel Isolation  
VIN = 2.5Vp-p at 1kHz  
–95  
81  
95  
ꢀ
ꢀ
ꢀ
ꢀ
dB  
dB  
dB  
dB  
V
V
IN = 2.5Vp-p at 1kHz  
IN = 2.5Vp-p at 1kHz  
V
IN = 2.5Vp-p at 10kHz  
108  
REFERENCE INPUT  
Range  
0.5  
+VCC/2  
ꢀ
ꢀ
V
Resistance  
Input Current  
DCLK Static  
DCLK Static  
5
13  
0.001  
ꢀ
ꢀ
ꢀ
GΩ  
µA  
µA  
40  
3
ꢀ
ꢀ
DIGITAL INPUT/OUTPUT  
Logic Family  
Logic Levels  
VIH  
VIL  
VOH  
CMOS  
ꢀ
| IIH | ≤ +5µA  
| IIL | ≤ +5µA  
IOH = –250µA  
IOL = 250µA  
+VCC • 0.7  
–0.3  
+VCC • 0.8  
5.5  
+0.8  
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
V
V
VOL  
0.4  
ꢀ
Data Format  
Binary Two’s Complement  
ꢀ
POWER-SUPPLY REQUIREMENTS  
+VCC  
Quiescent Current  
Specified Performance  
2.7  
3.6  
1.85  
ꢀ
ꢀ
ꢀ
V
mA  
µA  
µA  
mW  
1.2  
950  
ꢀ
ꢀ
fSAMPLE = 10kHz  
Power-Down Mode(3), CS = +VCC  
3
5
ꢀ
ꢀ
Power Dissipation  
3.2  
ꢀ
TEMPERATURE RANGE  
Specified Performance  
–40  
+85  
ꢀ
ꢀ
°C  
ꢀ Same specifications as ADS8345E, N.  
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +1.25V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down  
mode (PD1 = PD0 = 0) active or SHDN = GND.  
4
ADS8345  
SBAS177C  
www.ti.com  
TYPICAL CHARACTERISTICS: +5V  
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
FREQUENCY SPECTRUM  
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)  
FREQUENCY SPECTRUM  
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)  
0
–20  
0
–20  
–40  
–40  
–60  
–60  
–80  
–80  
–100  
–120  
–140  
–100  
–120  
–140  
0
10  
20  
30  
40  
50  
0
10  
20  
30  
40  
50  
Frequency (kHz)  
Frequency (kHz)  
SPURIOUS-FREE DYNAMIC RANGE  
AND TOTAL HARMONIC DISTORTION  
vs INPUT FREQUENCY  
SIGNAL-TO-NOISE RATIO AND  
SIGNAL-TO-(NOISE + DISTORTION)  
vs INPUT FREQUENCY  
–110  
–100  
–90  
110  
100  
90  
100  
90  
80  
70  
60  
SFDR  
THD(1)  
SNR  
SINAD  
–80  
80  
–70  
70  
NOTE: (1) First Nine Harmonics  
of the Input Frequency  
–60  
60  
1
10  
100  
1
10  
100  
Frequency (kHz)  
Frequency (kHz)  
EFFECTIVE NUMBER OF BITS  
vs INPUT FREQUENCY  
CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)  
vs TEMPERATURE  
15.0  
14.5  
14.0  
13.5  
13.0  
12.5  
12.0  
11.5  
11.0  
0.4  
0.2  
fIN = 4.956kHz, –0.2dB  
0.0  
–0.2  
–0.4  
–0.6  
–0.8  
–50  
–25  
0
20  
50  
75  
100  
1
10  
100  
Temperature (°C)  
Frequency (kHz)  
5
ADS8345  
SBAS177C  
www.ti.com  
TYPICAL CHARACTERISTICS: +5V (Cont.)  
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
INTEGRAL LINEARITY ERROR vs CODE  
DIFFERENTIAL LINEARITY ERROR vs CODE  
3
2
3
2
1
1
0
0
–1  
–2  
–3  
–1  
–2  
–3  
8000H  
C000H  
0000H  
4000H  
7FFFH  
8000H  
C000H  
0000H  
4000H  
7FFFH  
Output Code  
Output Code  
SUPPLY CURRENT vs TEMPERATURE  
CHANGE IN BPZ vs TEMPERATURE  
1.7  
1.6  
1.5  
1.4  
1.3  
1.2  
4
3
2
1
0
–1  
–2  
–50  
–25  
0
25  
50  
75  
100  
–50  
–25  
0
25  
50  
75  
100  
Temperature (°C)  
Temperature (°C)  
WORST-CASE CHANNEL-TO-CHANNEL  
BPZ MATCH vs TEMPERATURE  
CHANGE IN GAIN vs TEMPERATURE  
1.0  
0.5  
0
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
–0.5  
–50  
–25  
0
25  
50  
75  
100  
–50  
–25  
0
25  
50  
75  
100  
Temperature (°C)  
Temperature (°C)  
6
ADS8345  
SBAS177C  
www.ti.com  
TYPICAL CHARACTERISTICS: +5V (Cont.)  
At TA = +25°C, +VCC = +2.5V, VREF = +2.5V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
WORST-CASE CHANNEL-TO-CHANNEL  
GAIN MATCH vs TEMPERATURE  
COMMON-MODE REJECTION vs FREQUENCY  
0.5  
0.4  
0.3  
0.2  
0.1  
100  
90  
80  
70  
60  
50  
VCM = 2Vp-p Sinewave Centered Around VREF  
–50  
–25  
0
25  
50  
75  
100  
0.1  
1
10  
100  
Temperature (°C)  
Frequency (kHz)  
TYPICAL CHARACTERISTICS: +2.7V  
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
FREQUENCY SPECTRUM  
(4096 Point FFT; fIN = 9.985kHz, –0.2dB)  
FREQUENCY SPECTRUM  
(4096 Point FFT; fIN = 1.001kHz, –0.2dB)  
0
–20  
0
–20  
–40  
–40  
–60  
–60  
–80  
–80  
–100  
–120  
–140  
–100  
–120  
–140  
0
10  
20  
30  
40  
50  
0
10  
20  
30  
40  
50  
Frequency (kHz)  
Frequency (kHz)  
SPURIOUS-FREE DYNAMIC RANGE  
AND TOTAL HARMONIC DISTORTION  
vs INPUT FREQUENCY  
SIGNAL-TO-NOISE RATIO AND  
SIGNAL-TO-(NOISE + DISTORTION)  
vs INPUT FREQUENCY  
–100  
–90  
–80  
–70  
–60  
–50  
100  
90  
80  
70  
60  
50  
95  
85  
75  
65  
55  
SNR  
SFDR  
THD(1)  
SINAD  
NOTE: (1) First Nine Harmonics  
of the Input Frequency  
1
10  
100  
1
10  
Frequency (kHz)  
100  
Frequency (kHz)  
7
ADS8345  
SBAS177C  
www.ti.com  
TYPICAL CHARACTERISTICS: +2.7V (Cont.)  
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
EFFECTIVE NUMBER OF BITS  
vs INPUT FREQUENCY  
CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)  
vs TEMPERATURE  
0.4  
0.2  
14.0  
13.5  
13.0  
12.5  
12.0  
11.5  
11.0  
10.5  
10.0  
9.5  
fIN = 4.956kHz, –0.2dB  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
9.0  
–50  
–25  
0
20  
50  
75  
100  
7FFFH  
100  
1
10  
100  
Temperature (°C)  
Frequency (kHz)  
INTEGRAL LINEARITY ERROR vs CODE  
DIFFERENTIAL LINEARITY ERROR vs CODE  
3
2
3
2
1
1
0
0
–1  
–2  
–3  
–1  
–2  
–3  
8000H  
C000H  
0000H  
4000H  
7FFFH  
8000H  
C000H  
0000H  
4000H  
Output Code  
Output Code  
SUPPLY CURRENT vs TEMPERATURE  
CHANGE IN BPZ vs TEMPERATURE  
1.3  
1.0  
1.2  
1.1  
1.0  
0.9  
0.5  
0
–0.5  
–1.0  
–50  
–25  
0
25  
50  
75  
100  
–50  
–25  
0
25  
50  
75  
Temperature (°C)  
Temperature (°C)  
8
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TYPICAL CHARACTERISTICS: +2.7V (Cont.)  
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fDCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.  
WORST-CASE CHANNEL-TO-CHANNEL  
BPZ MATCH vs TEMPERATURE  
CHANGE IN GAIN vs TEMPERATURE  
1.0  
0.5  
0
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
–0.5  
–50  
–25  
0
25  
50  
75  
100  
–50  
0.1  
2.5  
–25  
0
25  
50  
75  
100  
100  
5.0  
Temperature (°C)  
Temperature (°C)  
WORST-CASE CHANNEL-TO-CHANNEL  
GAIN MATCH vs TEMPERATURE  
COMMON-MODE REJECTION vs FREQUENCY  
0.35  
0.30  
0.25  
0.20  
80  
70  
60  
50  
40  
VCM = 1Vp-p Sinewave Centered Around VREF  
–50  
–25  
0
25  
50  
75  
100  
1
10  
Temperature (°C)  
Frequency (kHz)  
POWER-DOWN SUPPLY CURRENT  
vs TEMPERATURE  
SUPPLY CURRENT vs VSS  
140  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
120  
100  
80  
60  
40  
20  
0
External Clock Disabled  
fSAMPLE = 100kHz  
–50  
–25  
0
25  
50  
75  
100  
3.0  
3.5  
4.0  
4.5  
Temperature (°C)  
+VSS (V)  
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determines the range over which the common voltage may  
vary (see Figure 3).  
THEORY OF OPERATION  
The ADS8345 is a classic Successive Approximation  
Register (SAR) A/D converter. The architecture is based on  
capacitive redistribution which inherently includes a sample-  
and-hold function. The converter is fabricated on a 0.6µm  
CMOS process.  
When the input is differential, the amplitude of the input is the  
difference between the CHX and COM input (see Figure 4).  
A voltage or signal is common to both of these inputs. The  
peak-to-peak amplitude of each input is VREF about this  
common voltage. However, since the input are 180°C out-of-  
phase, the peak-to-peak amplitude of the difference voltage is  
2 • VREF. The value of VREF also determines the range of the  
voltage that may be common to both inputs (see Figure 5).  
The basic operation of the ADS8345 is shown in Figure 1.  
The device requires an external reference and an external  
clock. It operates from a single supply of 2.7V to 5.25V. The  
external reference can be any voltage between 500mV and  
+VCC/2. The value of the reference voltage directly sets the  
input range of the converter. The average reference input  
current depends on the conversion rate of the ADS8345.  
In each case, care should be taken to ensure that the output  
impedance of the sources driving the CHX and COM inputs  
are matched. If this is not observed, the two inputs could  
have different settling times. This may result in offset error,  
gain error, and linearity error which changes with both  
temperature and input voltage. If the impedance cannot be  
matched, the errors can be lessened by giving the ADS8345  
additional acquisition time.  
The analog input to the converter is differential and is  
provided via an eight-channel multiplexer. The input can be  
provided in reference to a voltage on the COM pin (which is  
generally +VCC/2) or differentially by using four of the eight  
input channels (CH-CH7). The particular configuration is  
selectable via the digital interface.  
The input current on the analog inputs depends on a number  
of factors: sample rate, input voltage, and source impedance.  
Essentially, the current into the ADS8345 charges the inter-  
nal capacitor array during the sample period. After this  
capacitance has been fully charged, there is no further input  
current.  
ANALOG INPUT  
The analog input is bipolar and fully differential. There are  
two general methods of driving the analog input of the  
ADS8345: single-ended or differential (see Figure 2). When  
the input is single-ended, the COM input is held at a fixed  
voltage. The CHX input swings around the same voltage and  
the peak-to-peak amplitude is 2 • VREF. The value of VREF  
Care must be taken regarding the absolute analog input  
voltage. Outside of these ranges, the converter’s linearity  
may not meet specifications. Please refer to the Electrical  
Characteristics table for min/max ratings.  
+2.7V to +5V  
ADS8345  
+VCC 20  
1µF to 10µF  
0.1µF  
1
2
3
4
5
6
7
8
9
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CH7  
COM  
Serial/Conversion Clock  
Chip Select  
DCLK 19  
CS 18  
Single-ended  
or differential  
analog inputs.  
Serial Data In  
DIN 17  
BUSY 16  
DOUT 15  
GND 14  
GND 13  
+VCC 12  
VREF 11  
Serial Data Out  
VREF  
+1.25V to +2.5V  
10 SHDN  
1µF to 10µF  
FIGURE 1. Basic Operation of the ADS8345.  
10  
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REFERENCE INPUT  
ence between the CHX input and the COM input, as shown  
in Figure 4. For example, in the single-ended mode, a 1.25V  
reference with the COM pin at VCC/2, the selected input  
channel (CH0-CH7) will properly digitize a signal in the range  
of (VCC/2 – 1.25V) to (VCC/2 + 1.25V).  
The external reference sets the analog input range. The  
ADS8345 will operate with a reference in the range of 500mV  
to +VCC/2. Keep in mind that the analog input is the differ-  
A2-A0  
(shown 00oB)(1)  
CH0  
CH1  
CH2  
CH3  
CH4  
CH5  
CH6  
CHX  
(1)  
±VREF  
ADS8345  
COM  
Common-Mode  
Voltage  
(typically VREF  
)
+IN  
Converter  
–IN  
CH7  
Single-Ended Input  
(1)  
VREF  
±
CHX+  
ADS8345  
CHX–  
2
(1)  
Common-Mode  
Voltage  
VREF  
2
±
Differential Input  
NOTE: (1) Relative to common-mode voltage.  
COM  
SGL/DIF  
(shown HIGH)  
NOTE: (1) See Truth Tables, Table I,  
and Table II for address coding.  
FIGURE 2. Methods of Driving the ADS8345—Single-Ended  
FIGURE 4. Simplified Diagram of the Analog Input.  
or Differential.  
5
VCC = 5V  
4.9  
5.2  
5
4
VCC = 5V  
4.2  
4
Single-Ended Input  
3
2
2.8  
2.1  
3
Differential Input  
2
1
0.1  
1
0.8  
0
0.2  
0
–1  
0.0  
1.0  
1.5  
2.0  
2.5  
0.5  
1.0  
1.5  
2.0  
2.5  
VREF (V)  
VREF (V)  
FIGURE 3. Single-Ended Input—Common Voltage Range  
vs VREF  
FIGURE 5. Differential Input—Common Voltage Range vs VREF.  
.
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There are several critical items concerning the reference  
input and its wide-voltage range. As the reference voltage is  
reduced, the analog voltage weight of each digital output  
code is also reduced. This is often referred to as the LSB  
(Least Significant Bit) size and is equal to the reference  
voltage divided by 65536. Any offset or gain error inherent in  
the A/D converter will appear to increase, in terms of LSB  
size, as the reference voltage is reduced. For example, if the  
offset of a given converter is 2LSBs with a 2.5V reference,  
then it will typically be 10LSBs with a 0.5V reference. In each  
case, the actual offset of the device is the same, 152.8µV.  
Most microprocessors communicate using 8-bit transfers; the  
ADS8345 can complete a conversion with three such trans-  
fers, for a total of 24 clock cycles on the DCLK input,  
provided the timing is as shown in Figure 6.  
The first eight clock cycles are used to provide the control  
byte via the DIN pin. When the converter has enough informa-  
tion about the following conversion to set the input multi-  
plexer appropriately, it enters the acquisition (sample) mode.  
After four more clock cycles, the control byte is complete and  
the converter enters the conversion mode. At this point, the  
input sample-and-hold goes into the Hold mode. The next  
sixteen clock cycles accomplish the actual A/D conversion.  
The noise or uncertainty of the digitized output will increase  
with lower LSB size. With a reference voltage of 500mV, the  
LSB size is 15.3µV. This level is below the internal noise of  
the device. As a result, the digital output code will not be  
stable and will vary around a mean value by a number of  
LSBs. The distribution of output codes will be gaussian and  
the noise can be reduced by simply averaging consecutive  
conversion results or applying a digital filter.  
Control Byte  
Figure 6 shows placement and order of the control bits within  
the control byte. Tables I and II give detailed information  
about these bits. The first bit, the “S” bit, must always be  
HIGH and indicates the start of the control byte. The ADS8345  
will ignore inputs on the DIN pin until the START bit is  
detected. The next three bits (A2-A0) select the active input  
channel or channels of the input multiplexer (see Tables III  
and IV and Figure 4).  
With a lower reference voltage, care should be taken to  
provide a clean layout including adequate bypassing, a clean  
(low-noise, low-ripple) power supply, a low-noise reference,  
and a low-noise input signal. Because the LSB size is lower,  
the converter will also be more sensitive to nearby digital  
signals and electromagnetic interference.  
BIT 7  
(MSB)  
BIT 0  
(LSB)  
BIT 6  
BIT 5  
BIT 4  
BIT 3  
BIT 2  
BIT 1  
S
A2  
A1  
A0  
—
SGL/DIF PD1  
PD0  
The voltage into the VREF input is not buffered and directly  
drives the Capacitor Digital-to-Analog Converter (CDAC)  
portion of the ADS8345. Typically, the input current is 13µA  
with a 2.5V reference. This value will vary by microamps  
depending on the result of the conversion. The reference  
current diminishes directly with both conversion rate and  
reference voltage. As the current from the reference is drawn  
on each bit decision, clocking the converter more quickly  
during a given conversion period will not reduce overall  
current drain from the reference.  
TABLE I. Order of the Control Bits in the Control Byte.  
BIT  
NAME  
DESCRIPTION  
7
S
Start Bit. Control byte starts with first HIGH bit on  
DIN  
.
6-4  
2
A2-A0  
Channel Select Bits. Along with the SGL/DIF bit,  
these bits control the setting of the multiplexer input.  
SGL/DIF  
Single-Ended/Differential Select Bit. Along with bits  
A2-A0, this bit controls the setting of the multiplexer  
input.  
1-0  
PD1-PD0 Power-Down Mode Select Bits. See Table V for  
details.  
DIGITAL INTERFACE  
The ADS8345 has a 4-wire serial interface compatible with  
several microprocessor families (note that the digital inputs are  
over-voltage tolerant up to +5.5V, regardless of +VCC). Figure 6  
shows the typical operation of the ADS8345 digital interface.  
TABLE II. Descriptions of the Control Bits within the Control Byte.  
CS  
tACQ  
DCLK  
DIN  
1
8
1
8
1
8
1
8
1
Idle  
Acquire  
Conversion  
Idle  
Acquire  
Conversion  
SGL/  
DIF  
SGL/  
DIF  
S
A2 A1 A0  
PD1 PD0  
S
A2 A1 A0  
PD1 PD0  
(START)  
(START)  
BUSY  
DOUT  
15  
14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
Zero Filled...  
15 14  
(MSB)  
(MSB)  
(LSB)  
FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated  
serial port.  
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The SGL/DIF-bit controls the multiplexer input mode:  
either in single-ended mode, where the selected input chan-  
nel is referenced to the COM pin, or in differential mode,  
where the two selected inputs provide a differential input.  
See Tables III and IV and Figure 4 for more information. The  
last two bits (PD1-PD0) select the Power-Down mode and  
Clock mode, as shown in Table V. If both PD1 and PD0 are  
HIGH, the device is always powered up. If both PD1 and PD0  
are LOW, the device enters a power-down mode between  
conversions. When a new conversion is initiated, the device  
will resume normal operation instantly—no delay is needed  
to allow the device to power up and the very first conversion  
will be valid.  
PD1  
PD0  
DESCRIPTION  
0
0
Power-down between conversions. When each  
conversion is finished, the converter enters a  
low-power mode. At the start of the next conver-  
sion, the device instantly powers up to full power.  
There is no need for additional delays to assure full  
operation and the very first conversion is valid.  
1
0
1
0
1
1
Selects internal clock mode.  
Reserved for future use.  
No power-down between conversions, device al-  
ways powered. Selects external clock mode.  
TABLE V. Power-Down Selection.  
Clock Modes  
The ADS8345 can be used with an external serial clock or an  
internal clock to perform the successive-approximation con-  
version. In both clock modes, the external clock shifts data in  
and out of the device. Internal clock mode is selected when  
PD1 is HIGH and PD0 is LOW.  
A2  
A1  
A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM  
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+IN  
–IN  
–IN  
–IN  
–IN  
–IN  
–IN  
–IN  
–IN  
+IN  
+IN  
If the user decides to switch from one clock mode to the  
other, an extra conversion cycle will be required before the  
ADS8345 can switch to the new mode. The extra cycle is  
required because the PD0 and PD1 control bits need to be  
written to the ADS8345 prior to the change in clock modes.  
+IN  
+IN  
+IN  
+IN  
+IN  
When power is first applied to the ADS8345, the user must  
set the desired clock mode. It can be set by writing PD1 = 1  
and PD0 = 0 for internal clock mode or PD1 = 1 and PD0  
= 1 for external clock mode. After enabling the required clock  
mode, only then should the ADS8345 be set to power-down  
between conversions (i.e., PD1 = PD0 = 0). The ADS8345  
maintains the clock mode it was in prior to entering the  
power-down modes.  
TABLE III. Single-Ended Channel Selection (SGL/DIF HIGH).  
A2  
A1  
A0  
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+IN  
–IN  
+IN  
–IN  
+IN  
–IN  
+IN  
–IN  
–IN  
+IN  
External Clock Mode  
–IN  
+IN  
–IN  
+IN  
In external clock mode, the external clock not only shifts data  
in and out of the ADS8345, it also controls the A/D conver-  
sion steps. BUSY will go HIGH for one clock period after the  
last bit of the control byte is shifted in. Successive-approxi-  
mation bit decisions are made and appear at DOUT on each  
of the next 16 DCLK falling edges (see Figure 6). Figure 7  
shows the BUSY timing in external clock mode.  
–IN  
+IN  
TABLE IV. Differential Channel Control (SGL/DIF LOW).  
CS  
tCL  
tCSH  
tCSS  
tCH  
tBD  
tBD  
tD0  
DCLK  
DIN  
tDH  
tDS  
PD0  
tBDV  
tBTR  
BUSY  
DOUT  
tDV  
tTR  
15  
14  
FIGURE 7. Detailed Timing Diagram.  
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Since one clock cycle of the serial clock is consumed with  
BUSY going HIGH (while the MSB decision is being made),  
16 additional clocks must be given to clock out all 16 bits of  
data; thus, one conversion takes a minimum of 25 clock  
cycles to fully read the data. Since most microprocessors  
communicate in 8-bit transfers, this means that an additional  
transfer must be made to capture the LSB.  
If CS is LOW when BUSY goes LOW following a conversion,  
the next falling edge of the external serial clock will write out  
the MSB on the DOUT line. The remaining bits (D14-D0) will  
be clocked out on each successive clock cycle following the  
MSB. If CS is HIGH when BUSY goes LOW then the DOUT  
line will remain in tri-state until CS goes LOW, as shown in  
Figure 9. CS does not need to remain LOW once a conver-  
sion has started. Note that BUSY is not tri-stated when CS  
goes HIGH in internal clock mode.  
There are two ways of handling this requirement. One is  
where the beginning of the next control byte appears at the  
same time the LSB is being clocked out of the ADS8345 (see  
Figure 6). This method allows for maximum throughput and  
24 clock cycles per conversion.  
Data can be shifted in and out of the ADS8345 at clock rates  
exceeding 2.4MHz, provided that the minimum acquisition  
time tACQ, is kept above 1.7µs.  
The other method is shown in Figure 8, which uses 32 clock  
cycles per conversion; the last seven clock cycles simply  
shift out zeros on the DOUT line. BUSY and DOUT go into a  
high-impedance state when CS goes HIGH; after the next  
CS falling edge, BUSY will go LOW.  
Digital Timing  
Figure 7 and Tables VI and VII provide detailed timing for the  
digital interface of the ADS8345.  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
Internal Clock Mode  
tACQ  
tDS  
Acquisition Time  
DIN Valid Prior to DCLK Rising  
DIN Hold After DCLK HIGH  
DCLK Falling to DOUT Valid  
CS Falling to DOUT Enabled  
CS Rising to DOUT Disabled  
CS Falling to First DCLK Rising  
CS Rising to DCLK Ignored  
DCLK HIGH  
1.5  
100  
10  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
In internal clock mode, the ADS8345 generates its own  
conversion clock internally. This relieves the microprocessor  
from having to generate the SAR conversion clock and  
allows the conversion result to be read back at the processor’s  
convenience, at any clock rate from 0MHz to 2.0MHz. BUSY  
goes LOW at the start of a conversion and then returns HIGH  
when the conversion is complete. During the conversion,  
BUSY will remain LOW for a maximum of 8µs. Also, during  
the conversion, DCLK should remain LOW to achieve the  
best noise performance. The conversion result is stored in an  
internal register; the data may be clocked out of this register  
any time after the conversion is complete.  
tDH  
tDO  
tDV  
200  
200  
200  
tTR  
tCSS  
tCSH  
tCH  
100  
0
200  
200  
tCL  
DCLK LOW  
tBD  
DCLK Falling to BUSY Rising  
CS Falling to BUSY Enabled  
CS Rising to BUSY Disabled  
200  
200  
200  
tBDV  
tBTR  
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,  
TA = –40°C to +85°C, CLOAD = 50pF).  
CS  
tACQ  
DCLK  
1
8
1
8
1
8
1
8
Idle  
Acquire  
Conversion  
Idle  
SGL/  
DIF  
DIN  
S
A2 A1 A0  
PD1 PD0  
(START)  
BUSY  
DOUT  
Zero Filled...  
15  
14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
(MSB)  
(LSB)  
FIGURE 8. External Clock Mode, 32 Clocks Per Conversion.  
CS  
tACQ  
DCLK  
1
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
Idle  
Acquire  
Conversion  
SGL/  
DIF  
DIN  
S
A2 A1 A0  
PD1 PD0  
(START)  
BUSY  
DOUT  
15  
(MSB)  
14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
Zero Filled...  
(LSB)  
FIGURE 9. Internal Clock Mode Timing.  
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If DCLK is active and CS is LOW while the ADS8345 is in  
auto power-down mode, the device will continue to dissipate  
some power in the digital logic. The power can be reduced  
to a minimum by keeping CS HIGH.  
SYMBOL  
DESCRIPTION  
MIN  
TYP  
MAX  
UNITS  
tACQ  
tDS  
Acquisition Time  
DIN Valid Prior to DCLK Rising  
DIN Hold After DCLK HIGH  
DCLK Falling to DOUT Valid  
CS Falling to DOUT Enabled  
CS Rising to DOUT Disabled  
CS Falling to First DCLK Rising  
CS Rising to DCLK Ignored  
DCLK HIGH  
1.7  
50  
10  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tDH  
tDO  
tDV  
100  
70  
Operating the ADS8345 in auto power-down mode will result  
in the lowest power dissipation, and there is no conversion  
time “penalty” on power-up. The very first conversion will be  
valid. SHDN can be used to force an immediate power-down.  
tTR  
70  
tCSS  
tCSH  
tCH  
50  
0
150  
150  
tCL  
DCLK LOW  
NOISE  
tBD  
DCLK Falling to BUSY Rising  
CS Falling to BUSY Enabled  
CS Rising to BUSY Disabled  
100  
70  
tBDV  
tBTR  
The noise floor of the ADS8345 itself is rather low (see  
Figures 10 and 11). The ADS8345 was tested at both 5V and  
2.7V, and in both the internal and external clock modes. A  
low-level DC input was applied to the analog-input pins and  
the converter was put through 5000 conversions. The digital  
output of the A/D converter will vary in output code due to the  
internal noise of the ADS8345. This is true for all 16-bit, SAR-  
type, A/D converters. Using a histogram to plot the output  
codes, the distribution should appear bell-shaped with the  
peak of the bell curve representing the nominal code for the  
input value. The ±1σ, ±2σ, and ±3σ distributions will repre-  
sent the 68.3%, 95.5%, and 99.7%, respectively, of all codes.  
The transition noise can be calculated by dividing the number  
of codes measured by 6 and this will yield the ±3σ distribu-  
tion, or 99.7%, of all codes. Statistically, up to 3 codes could  
fall outside the distribution when executing 1000 conver-  
sions. The ADS8345, with 5 output codes for the ±3σ  
distribution, will yield a < ±0.83LSB transition noise at 5V  
operation. Remember, to achieve this low-noise performance,  
the peak-to-peak noise of the input signal and reference  
must be < 50µV.  
70  
TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V,  
TA = –40°C to +85°C, and CLOAD = 50pF).  
Data Format  
The output data from the ADS8345 is in Binary Two’s  
Complement format, as shown in Table VIII. This table  
represents the ideal output code for the given input voltage  
and does not include the effects of offset, gain error, or noise.  
DESCRIPTION  
ANALOG VALUE  
2 • VREF  
DIGITAL OUTPUT  
Full-Scale Range  
BINARY TWO’S COMPLEMENT  
Least Significant  
Bit (LSB)  
2 • VREF/65536  
BINARY CODE  
HEX CODE  
7FFF  
+Full-Scale  
Midscale  
+VREF – 1LSB  
0V  
0111 1111 1111 1111  
0000 0000 0000 0000  
1111 1111 1111 1111  
1000 0000 0000 0000  
0000  
Midscale – 1LSB  
–Full-Scale  
0V – 1LSB  
–VREF  
FFFF  
8000  
TABLE VIII. Ideal Input Voltages and Output Codes.  
POWER DISSIPATION  
3544  
There are three power modes for the ADS8345: full-power  
(PD1-PD0 = 11B), auto power-down (PD1-PD0 = 00B), and  
shutdown (SHDN LOW). The effects of these modes varies  
depending on how the ADS8345 is being operated. For  
example, at full conversion rate and 24-clocks per conver-  
sion, there is very little difference between  
full-power mode and auto power-down; a shutdown will not  
lower power dissipation.  
701  
568  
When operating at full-speed and 24-clocks per conversion  
(see Figure 6), the ADS8345 spends most of its time acquir-  
ing or converting. There is little time for auto power-down,  
assuming that this mode is active. Thus, the difference  
between full-power mode and auto power-down is negligible.  
If the conversion rate is decreased by simply slowing the  
frequency of the DCLK input, the two modes remain approxi-  
mately equal. However, if the DCLK frequency is kept at the  
maximum rate during a conversion, but conversions are  
simply done less often, then the difference between the two  
modes is dramatic. In the latter case, the converter spends  
an increasing percentage of its time in power-down mode  
(assuming the auto power-down mode is active).  
122  
65  
FFFFH  
0000H  
Code  
0002H  
FFFEH  
0001H  
FIGURE 10. Histogram of 5000 Conversions of a DC Input at  
the Code Transition, 5V operation external clock  
mode. VREF = VCOM = 2.5V.  
15  
ADS8345  
SBAS177C  
www.ti.com  
output of the analog comparator. Thus, during any single  
conversion for an n-bit SAR converter, there are n “windows”  
in which large external transient voltages can easily affect  
the conversion result. Such glitches might originate from  
switching power supplies, nearby digital logic, and high-  
power devices. The degree of error in the digital output  
depends on the reference voltage, layout, and the exact  
timing of the external event. The error can change if the  
external event changes in time with respect to the DCLK  
input.  
2305  
938  
780  
436  
435  
With this in mind, power to the ADS8345 should be clean and  
well bypassed. A 0.1µF ceramic bypass capacitor should be  
placed as close to the device as possible. In addition, a 1µF  
to 10µF capacitor and a 5Ω or 10Ω series resistor may be  
used to low-pass filter a noisy supply.  
64  
28  
8
6
FFFCH FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H 0004H  
Code  
The reference should be similarly bypassed with a 0.1µF  
capacitor. Again, a series resistor and large capacitor can be  
used to low-pass filter the reference voltage. If the reference  
voltage originates from an op amp, make sure that it can  
drive the bypass capacitor without oscillation (the series  
resistor can help in this case). The ADS8345 draws very little  
current from the reference on average, but it does place  
larger demands on the reference circuitry over short periods  
of time (on each rising edge of DCLK during a conversion).  
FIGURE 11. Histogram of 5000 Conversions of a DC Input at  
the Code Center, 2.7V operation external clock  
mode. VREF = VCOM = 1.25V.  
AVERAGING  
The noise of the A/D converter can be compensated by  
averaging the digital codes. By averaging conversion results,  
transition noise will be reduced by a factor of 1/√n, where n  
is the number of averages. For example, averaging 4 conver-  
sion results will reduce the transition noise by 1/2 to  
±0.25LSBs. Averaging should only be used for input signals  
with frequencies near DC.  
The ADS8345 architecture offers no inherent rejection of  
noise or voltage variation in regards to the reference input.  
This is of particular concern when the reference input is tied  
to the power supply. Any noise and ripple from the supply will  
appear directly in the digital results. While high-frequency  
noise can be filtered out as discussed in the previous  
paragraph, voltage variation due to line frequency (50Hz or  
60Hz) can be difficult to remove.  
For AC signals, a digital filter can be used to low-pass filter  
and decimate the output codes. This works in a similar  
manner to averaging: for every decimation by 2, the  
signal-to-noise ratio will improve 3dB.  
The GND pin should be connected to a clean ground point.  
In many cases, this will be the “analog” ground. Avoid  
connections which are too near the grounding point of a  
microcontroller or digital signal processor. If needed, run a  
ground trace directly from the converter to the power-supply  
entry point. The ideal layout will include an analog ground  
plane dedicated to the converter and associated analog  
circuitry.  
LAYOUT  
For optimum performance, care should be taken with the  
physical layout of the ADS8345 circuitry. This is particularly  
true if the reference voltage is LOW and/or the conversion  
rate is HIGH.  
The basic SAR architecture is sensitive to glitches or sudden  
changes on the power supply, reference, ground connec-  
tions, and digital inputs that occur just prior to latching the  
16  
ADS8345  
SBAS177C  
www.ti.com  
PACKAGE DRAWINGS  
DBQ (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
24 PINS SHOWN  
0.012 (0,30)  
0.008 (0,20)  
0.025 (0,64)  
24  
0.005 (0,13)  
M
13  
0.244 (6,20)  
0.228 (5,80)  
0.008 (0,20) NOM  
0.157 (3,99)  
0.150 (3,81)  
Gage Plane  
1
12  
A
0.010 (0,25)  
0°–8°  
0.035 (0,89)  
0.016 (0,40)  
0.069 (1,75) MAX  
Seating Plane  
0.004 (0,10)  
0.010 (0,25)  
0.004 (0,10)  
PINS **  
16  
20  
24  
28  
DIM  
0.197  
(5,00)  
0.344  
(8,74)  
0.344  
(8,74)  
0.394  
(10,01)  
A MAX  
0.188  
(4,78)  
0.337  
(8,56)  
0.337  
(8,56)  
0.386  
(9,80)  
A MIN  
4073301/E 10/00  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-137  
17  
ADS8345  
SBAS177C  
www.ti.com  
PACKAGE DRAWINGS (Cont.)  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°–8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
18  
ADS8345  
SBAS177C  
www.ti.com  
PACKAGE OPTION ADDENDUM  
www.ti.com  
3-Oct-2003  
PACKAGING INFORMATION  
ORDERABLE DEVICE  
STATUS(1)  
PACKAGE TYPE  
PACKAGE DRAWING  
PINS  
PACKAGE QTY  
ADS8345E  
ADS8345E/2K5  
ADS8345EB  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SSOP  
SSOP  
SSOP  
SSOP  
SSOP  
SSOP  
DBQ  
DBQ  
DBQ  
DBQ  
DB  
20  
20  
20  
20  
20  
20  
20  
20  
56  
2500  
56  
ADS8345EB/2K5  
ADS8345N  
2500  
68  
ADS8345N/1K  
ADS8345NB  
DB  
1000  
68  
DB  
ADS8345NB/1K  
DB  
1000  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess  
in which TI products or services are used. Information published by TI regarding third-party products or services  
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.  
Use of such information may require a license from a third party under the patents or other intellectual property  
of the third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without  
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction  
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for  
such altered documentation.  
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that  
product or service voids all express and any implied warranties for the associated TI product or service and  
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.  
Following are URLs where you can obtain information on other Texas Instruments products and application  
solutions:  
Products  
Applications  
Audio  
Amplifiers  
amplifier.ti.com  
www.ti.com/audio  
Data Converters  
dataconverter.ti.com  
Automotive  
www.ti.com/automotive  
DSP  
dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
www.ti.com/telephony  
www.ti.com/video  
microcontroller.ti.com  
Telephony  
Video & Imaging  
Wireless  
www.ti.com/wireless  
Mailing Address:  
Texas Instruments  
Post Office Box 655303 Dallas, Texas 75265  
Copyright 2003, Texas Instruments Incorporated  

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