ADS8371 [BB]
16BIT 750KHZ UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG TO DIGITAL CONVERTER WITH PARALLEL INTERFACE; 16BIT 750kHz的单极性输入，并行接口微功率采样模数转换器
| 型号： | ADS8371 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16BIT 750KHZ UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG TO DIGITAL CONVERTER WITH PARALLEL INTERFACE |
| 文件： | 总32页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
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FEATURES
APPLICATIONS
D
750-KSPS Sample Rate
D
D
D
D
D
Medical Instruments
Optical Networking
Transducer Interface
D
High Linearity:
− +0.9 LSB INL Typ, + 1.5 LSB Max
− −0.4/+0.6 LSB DNL Typ, + 1 LSB Max
High Accuracy Data Acquisition Systems
Magnetometers
D
Onboard Reference Buffer and Conversion
Clock
D
D
D
D
D
D
D
D
0 V to 4.096 V Unipolar Inputs
Low Noise: 88 dB SNR
DESCRIPTION
High Dynamic Range: 110 dB SFDR
Very Low Offset and Offset Drift
Low Power: 130 mW at 750 KSPS
Wide Buffer Supply, 2.7 V to 5.25 V
Flexible 8-/16-Bit Parallel Interface
The ADS8371 is an 16-bit, 750 kHz A/D converter. The
device includes a 16-bit capacitor-based SAR A/D
converter with inherent sample and hold. The ADS8371
offers a full 16-bit interface or an 8-bit bus option using two
read cycles.
Direct Pin Compatible With
ADS8381/ADS8383
The ADS8371 is available in a 48-lead TQFP package and
is characterized over the industrial −40°C to 85°C
temperature range.
D
48-Pin TQFP Package
Output
Latches
and
3-State
Drivers
BYTE
SAR
16-/8-Bit
Parallel DATA
Output Bus
+
_
+IN
−IN
CDAC
Comparator
Clock
REFIN
CONVST
BUSY
CS
Conversion
and
Control Logic
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢔꢗ ꢕ ꢁꢒ ꢙ ꢋꢊ ꢕꢓ ꢁ ꢀꢋꢀ ꢟꢠ ꢡꢢ ꢣ ꢤꢥ ꢦꢟꢢꢠ ꢟꢧ ꢨꢩ ꢣ ꢣ ꢪꢠꢦ ꢥꢧ ꢢꢡ ꢫꢩꢬ ꢭꢟꢨ ꢥꢦꢟ ꢢꢠ ꢮꢥ ꢦꢪꢯ ꢔꢣ ꢢꢮꢩ ꢨꢦꢧ
ꢨ ꢢꢠ ꢡꢢꢣ ꢤ ꢦꢢ ꢧ ꢫꢪ ꢨ ꢟ ꢡꢟ ꢨ ꢥ ꢦꢟ ꢢꢠꢧ ꢫ ꢪꢣ ꢦꢰꢪ ꢦꢪ ꢣ ꢤꢧ ꢢꢡ ꢋꢪꢱ ꢥꢧ ꢊꢠꢧ ꢦꢣ ꢩꢤ ꢪꢠꢦ ꢧ ꢧꢦ ꢥꢠꢮ ꢥꢣ ꢮ ꢲ ꢥꢣ ꢣ ꢥ ꢠꢦꢳꢯ
ꢔꢣ ꢢ ꢮꢩꢨ ꢦ ꢟꢢ ꢠ ꢫꢣ ꢢ ꢨ ꢪ ꢧ ꢧ ꢟꢠ ꢴ ꢮꢢ ꢪ ꢧ ꢠꢢꢦ ꢠꢪ ꢨꢪ ꢧꢧ ꢥꢣ ꢟꢭ ꢳ ꢟꢠꢨ ꢭꢩꢮ ꢪ ꢦꢪ ꢧꢦꢟ ꢠꢴ ꢢꢡ ꢥꢭ ꢭ ꢫꢥ ꢣ ꢥꢤ ꢪꢦꢪ ꢣ ꢧꢯ
Copyright 2003, Texas Instruments Incorporated
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
NO
MISSING
CODES
RESOLU-
TION (BIT)
MAXIMUM
INTEGRAL DIFFERENTIAL
LINEARITY
(LSB)
MAXIMUM
TRANS-
PORT
MEDIA
TEMPER-
ATURE
RANGE
PACKAGE
TYPE
PACKAGE
DESIGNATOR
ORDERING
INFORMATION
MODEL
LINEARITY
(LSB)
QUANTITY
Tape and
reel 250
ADS8371IPFBT
ADS8371IPFBR
ADS8371IBPFBT
ADS8371IBPFBR
48 Pin
TQFP
−40°C to
85°C
ADS8371I
2.5
1.5
−1/1.5
16
16
PFB
PFB
Tape and
reel 1000
Tape and
reel 250
48 Pin
TQFP
−40°C to
85°C
ADS8371IB
1
Tape and
reel 1000
NOTE:
For the most current specifications and package information, refer to our website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
+IN to AGND
−0.4 V to +VA + 0.1 V
−0.4 V to 0.5 V
−0.3 V to 7 V
Voltage
−IN to AGND
+VA to AGND
+VBD to BDGND
+VA to +VBD
−0.3 V to 7 V
Voltage range
−0.3 V to 2.55 V
−0.3 V to +VBD + 0.3 V
−0.3 V to +VBD + 0.3 V
−40°C to 85°C
Digital input voltage to BDGND
Digital output voltage to BDGND
Operating free-air temperature range, T
A
Storage temperature range, T
stg
−65°C to 150°C
150°C
Junction temperature (T max)
J
Power dissipation
thermal impedance
(T Max − T )/θ
J
A
JA
TQFP package
θ
86°C/W
JA
Vapor phase (60 sec)
Infrared (15 sec)
215°C
220°C
Lead temperature, soldering
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
SPECIFICATIONS
A
T
= −40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, V = 4.096 V, f
= 750 kHz (unless otherwise noted)
ref
SAMPLE
ADS8371IB
ADS8371I
TYP
TEST
CONDITIONS
PARAMETER
UNIT
MIN
TYP
MAX
MIN
MAX
Analog Input
Full-scale input voltage (see Note 1)
+IN − −IN
+IN
0
−0.2
−0.2
V
0
−0.2
−0.2
V
V
V
ref
ref
V
ref
+ 0.2
0.2
V
ref
+ 0.2
0.2
Absolute input voltage
−IN
Input capacitance
Input leakage current
System Performance
Resolution
45
1
45
1
pF
nA
16
16
Bits
Bits
No missing codes
Integral linearity (see Notes 2 and 3)
Differential linearity
Offset error
16
−1.5
16
−2.5
−1
−0.8/0.9
−0.4/0.6
0.25
1.5
1
2.5
1.5
1
LSB
−1
LSB
−0.75
−0.075
0.75
0.075
−1
0.5
mV
Gain error (see Note 4)
Noise
−0.15
0.15
%FS
µV RMS
60
75
60
75
At 3FFFFh
output code
Power supply rejection ratio
dB
Sampling Dynamics
Conversion time
Acquisition time
Throughput rate
Aperture delay
1.13
750
1.13
750
µs
µs
0.2
0.2
kHz
ns
4
15
4
15
Aperture jitter
ps
Step response
150
150
150
150
ns
Over voltage recovery
ns
(1)
(2)
(3)
(4)
Ideal input span, does not include gain or offset error.
LSB means least significant bit
This is endpoint INL, not best fit.
Measured relative to an ideal full-scale input (+IN − −IN) of 4.096 V
3
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
SPECIFICATIONS (CONTINUED)
A
T
= −40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, V = 4.096 V, f
= 750 kHz (unless otherwise noted)
ref
SAMPLE
ADS8371IB
TYP
ADS8371I
TYP
UNIT
TEST
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNIT
Dynamic Characteristics
1 kHz
−106
−99
−92
−90
87.7
87.5
87.2
87
−100
−96
−90
−88
87
10 kHz
50 kHz
100 kHz
1 kHz
Total harmonic distortion (THD) (see Note 1)
dB
10 kHz
50 kHz
100 kHz
1 kHz
87
Signal to noise ratio (SNR) (see Note 1)
dB
dB
87
87
87.6
87
87
10 kHz
50 kHz
100 kHz
1 kHz
86
Signal to noise + distortion
(SINAD) (see Note 1)
86
85
85
84
110
100
95
106
97
10 kHz
50 kHz
100 kHz
Spurious free dynamic range (SFDR) (see
Note 1)
dB
92
94
90
−3dB Small signal bandwidth
3
3
MHz
Voltage Reference Input
Reference voltage at REFIN, V
ref
2.5
4.096
500
4.2
1
2.5
4.096
500
4.2
1
V
Reference resistance (see Note 2)
Reference current drain
kΩ
mA
f = 750 kHz
s
(1)
(2)
Calculated on the first nine harmonics of the input frequency
Can vary 20%
4
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
SPECIFICATIONS (CONTINUED)
A
T
= −40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, V = 4.096 V, f
= 750 kHz (unless otherwise noted)
ref
SAMPLE
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
Digital Input/Output
Logic family
CMOS
V
V
V
V
I
I
I
I
= 5 µA
= 5 µA
+VBD−1
−0.3
+V
BD
+ 0.3
0.8
IH
IH
IL
IL
Logic level
V
= 2 TTL loads
= 2 TTL loads
+V
BD
− 0.6
OH
OL
OH
OL
0.4
Straight
Binary
Data format
Power Supply Requirements
+VBD Buffer supply
+VA Analog Supply
2.7
3.3
5
5.25
5.25
28
V
V
Power supply voltage
4.75
(1)
Supply current, 750-kHz sample rate
26
mA
mW
(1)
Power dissipation, 750-kHz sample rate
Temperature Range
130
140
Operating free-air
−40
85
°C
(1)
This includes only +VA current. +VBD current is typical 1 mA with 5 pF load capacitance on all output pins.
5
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
TIMING CHARACTERISTICS
All specifications typical at −40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)
PARAMETER
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
t
t
t
Conversion time
1.13
µs
µs
ns
ns
ns
ns
ns
ns
ns
ps
µs
µs
CONV
ACQ
HOLD
pd1
Acquisition time
0.2
Sampling capacitor hold time
25
45
CONVST low to conversion started (BUSY high)
Propagation delay time, End of conversion to BUSY low
Propagation delay time, from start of conversion (internal state) to rising edge of BUSY
Pulse duration, CONVST low
20
pd2
20
pd3
40
20
20
400
w1
Setup time, CS low to CONVST low
Pulse duration, CONVST high
su1
w2
CONVST falling edge jitter
10
t
t
Pulse duration, BUSY signal low
Min(t )
ACQ
w3
Pulse duration, BUSY signal high
1.13
400
w4
Hold time, First data bus data transition (CS low for read cycle, or RD or BYTE input
changes) after CONVST low
t
h1
40
ns
t
t
t
t
t
t
t
t
t
Delay time, CS low to RD low
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
d1
Setup time, RD high to CS high
su2
w5
en
Pulse duration, RD low time
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
20
20
5
10
d2
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
Pulse duration, RD high
d3
20
w6
w7
h2
Pulse duration, CS high time
20
Hold time, last CS rising edge or changes of RD or BYTE to CONVST falling edge
125
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
t
Max(t )
d5
ns
pd4
t
t
t
t
Setup time, BYTE transition to RD falling edge
Hold time, BYTE transition to RD falling edge
10
10
ns
ns
ns
ns
su3
h3
Disable time, RD High (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid
20
30
dis
d5
t
Setup time, BYTE transition to next BYTE transition
50
65
10
ns
su5
Setup time, from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next
falling edge of CS (when CS is used to abort).
t
700
30
ns
su(AB)
t
Falling time, (CONVST falling edge)
ns
ns
f(CONVST)
t
Setup time, CS falling edge to CONVST falling edge when RD = 0
125
su6
(1)
(2)
(3)
All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2 except for CONVST.
IL IH
r
f
See timing diagrams.
All timing are measured with 20 pF equivalent loads on all data bits and BUSY pins.
6
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
TIMING CHARACTERISTICS
All specifications typical at −40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3)
PARAMETER
MIN
TYP
MAX
UNIT
µs
µs
ns
ns
ns
ns
ns
ns
ns
ps
µs
µs
ns
t
t
t
t
t
t
t
t
t
Conversion time
1.13
CONV
ACQ
HOLD
pd1
Acquisition time
0.2
Sampling capacitor hold time
25
50
CONVST low to conversion started (BUSY high)
Propagation delay time, end of conversion to BUSY low
Propagation delay time, from start of conversion (internal state) to rising edge of BUSY
Pulse duration, CONVST low
25
pd2
25
pd3
40
20
20
400
w1
Setup time, CS low to CONVST low
Pulse duration, CONVST high
su1
w2
CONVST falling edge jitter
10
t
t
t
Pulse duration, BUSY signal low
Min(t )
ACQ
w3
w4
h1
Pulse duration, BUSY signal high
1.13
400
Hold time, first data bus transition (CS low for read cycle, or RD or BYTE input
changes) after CONVST low
40
t
t
t
t
t
t
t
t
t
t
Delay time, CS low to RD low
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d1
Setup time, RD high to CS high
su2
w5
en
Pulse duration, RD low
50
Enable time, RD low (or CS low for read cycle) to data valid
Delay time, data hold from RD high
30
30
10
10
d2
Delay time, BUS18/16 or BYTE rising edge or falling edge to data valid
Pulse duration, RD high time
d3
20
w6
w7
h2
Pulse duration, CS high time
20
Hold time, last CS rising edge or changes of RD, or BYTE to CONVST falling edge
125
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling
edge
Max(td5)
pd4
t
t
t
t
Setup time, BYTE transition to RD falling edge
10
10
ns
ns
ns
ns
su3
Hold time, BYTE transition to RD falling edge
h3
Disable time, RD High (CS high for read cycle) to 3-stated data bus
Delay time, BUSY low to MSB data valid delay time
30
40
dis
d5
t
Setup time, BYTE transition to next BYTE transition
50
70
ns
su5
Setup time, from the falling edge of CONVST (used to start the valid conversion) to the
next falling edge of CONVST (when CS = 0 and CONVST used to abort) or to the next
falling edge of CS (when CS is used to abort).
t
700
30
ns
su(AB)
t
Falling time, (CONVST falling edge)
10
ns
ns
f(CONVST)
t
Setup time, CS falling edge to CONVST falling edge when RD = 0
125
su6
(1)
(2)
(3)
All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2 except for CONVST.
IL IH
r
f
See timing diagrams.
All timing are measured with 10 pF equivalent loads on all data bits and BUSY pins.
7
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
PIN ASSIGNMENTS
PFB PACKAGE
(TOP VIEW)
36 35 34 33 32 31 30 29 28 27 26 25
+VBD
BDGND
BYTE
CONVST
RD
+VBD
DB8
DB9
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
DB10
DB11
DB12
DB13
DB14
DB15
AGND
AGND
+VA
CS
+VA
AGND
AGND
+VA
REFM
REFM
1
2
3
4
5
6
7
8
9 10 11 12
NC − No connection.
8
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
TERMINAL FUNCTIONS
NAME
AGND
NO.
I/O
DESCRIPTION
5, 8, 11, 12,
14, 15, 44, 45
−
Analog ground
Digital ground for buffer supply
BDGND
BUSY
BYTE
25, 38
36
−
O
I
Status output. High when a conversion is in progress.
39
Byte select input. Used for 8-bit bus reading.
0: No fold back
1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant
pins DB[15:8].
CONVST
CS
40
42
I
I
Convert start. The falling edge of this input ends the acquisition period and starts the hold period.
Chip select. The falling edge of this input starts the acquisition period.
8-Bit Bus
16-Bit Bus
BYTE = 0
Data Bus
BYTE = 0
BYTE = 1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
16
17
18
19
20
21
22
23
26
27
28
29
30
31
32
33
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D15 (MSB)
D14
D13
D12
D11
D10
D9
D7
D6
D5
D4
D3
D2
D1
D15 (MSB)
D14
D13
D12
D11
D10
D9
DB8
D8
D0 (LSB)
D8
DB7
D7
All ones
All ones
All ones
All ones
All ones
All ones
All ones
All ones
D7
DB6
D6
D6
DB5
D5
D5
DB4
D4
D4
DB3
D3
D3
DB2
D2
D2
DB1
D1
D1
DB0
D0 (LSB)
D0 (LSB)
−IN
7
I
I
Inverting input channel
Non inverting input channel
No connection
+IN
6
2, 3, 34, 35
1
NC
−
I
REFIN
REFM
RD
Reference input
47, 48
41
I
Reference ground
I
Synchronization pulse for the parallel output. When CS is low, this serves as the output enable and puts
the previous conversion result on the bus.
+VA
4, 9, 10, 13,
43, 46
−
−
Analog power supplies, 5-V dc
+VBD
24, 37
Digital power supply for the buffer
9
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
TIMING DIAGRAMS
t
t
w2
w1
CONVST
t
t
pd1
pd2
t
w4
t
w3
BUSY
t
t
su1
w7
CS
t
†
pd3
CONVERT
t
CONV
t
CONV
t
HOLD
†
SAMPLING
(When CS Toggle)
t
ACQ
t
t
su(AB)
su(AB)
t
su5
BYTE
t
su5
t
su5
t
h1
t
su5
t
su2
t
pd4
t
h2
t
d1
RD
t
t
en
dis
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
DB[7:0]
D[15:8]
D[7:0]
D[7:0]
†
Signal internal to device
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling
10
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
t
w1
t
w2
t
t
pd2
pd1
t
w4
t
w3
BUSY
t
t
w7
su6
su6
t
CS
t
pd3
†
CONVERT
t
CONV
t
CONV
t
HOLD
†
SAMPLING
(When CS Toggle)
t
ACQ
t
t
su(AB)
su(AB)
t
su5
BYTE
t
su5
t
h1
t
su5
t
su5
t
dis
t
su2
t
pd4
t
h2
t
en
RD = 0
t
en
t
en
t
dis
Previous
Previous
D [15:8]
Hi−Z
Hi−Z
Hi−Z
Hi−Z
Hi−Z
D [15:8]
DB[15:8]
D[15:8]
D[7:0]
D[7:0]
Previous
D [7:0]
Previous
D [7:0]
Hi−Z
DB[7:0]
†
Signal internal to device
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND
11
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
t
w1
t
w2
CONVST
t
t
pd1
pd2
t
w4
t
w3
BUSY
CS = 0
t
pd3
†
CONVERT
t
CONV
t
CONV
t
HOLD
t
(ACQ)
†
SAMPLING
(When CS = 0)
t
t
su(AB)
su(AB)
t
su5
BYTE
t
su5
t
h1
t
pd4
t
h2
RD
t
t
en
dis
Hi−Z
Hi−Z
Hi−Z
Hi−Z
DB[15:8]
D[15:8]
D[7:0]
DB[7:0]
D[7:0]
†
Signal internal to device
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling
12
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
t
w2
t
w1
CONVST
t
t
pd2
pd1
t
w4
t
w3
BUSY
CS = 0
†
CONVERT
t
t
CONV
CONV
t
t
pd3
pd3
HOLD
t
t
HOLD
t
(ACQ)
†
SAMPLING
(When CS = 0)
t
t
su(AB)
su(AB)
BYTE
t
su5
t
su5
t
h1
t
h1
t
dis
t
su5
t
su5
RD = 0
t
d5
DB[15:8]
DB[7:0]
Previous D[7:0]
D[7:0]
Next D[15:8]
Next D[7:0]
D[15:8]
D[7:0]
†
Signal internal to device
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read
CS
RD
t
su4
BYTE
t
en
t
d3
t
t
t
en
dis
dis
Hi−Z
Hi−Z
Hi−Z
Valid
Valid
Valid
DB[15:0]
Figure 5. Detailed Timing for Read Cycles
13
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(1)
TYPICAL CHARACTERISTICS
HISTOGRAM (DC CODE SPREAD)
HALF SCALE 4096 CONVERSIONS
2000
+VA = 5 V,
+VBD = 5 V,
1800
T
= 255 C,
= 750 KSPS
A
1600
1400
1200
1000
800
600
400
200
0
f
s
code
Figure 6
GAIN ERROR
vs
FREE-AIR TEMPERATURE
GAIN ERROR
vs
FREE-AIR TEMPERATURE
0.1
0.1
+VA = 5 V,
+VA = 5 V,
+VBD = 5 V,
0.08
0.06
0.04
0.08
+VBD = 5 V,
= 750 KSPS,
f
V
S
ref
f
V
= 750 KSPS,
s
0.06
0.04
= 2.5 V
= 4.096 V
ref
0.02
0.02
0
0.00
−0.02
−0.04
−0.06
−0.08
−0.1
−0.02
−0.04
−0.06
−0.08
−0.1
−40
−15
T
10
35
60
85
−40
−15
T
10
35
60
85
− Free-Air Temperature − °C
− Free-Air Temperature − °C
A
A
Figure 7
Figure 8
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
OFFSET ERROR
vs
OFFSET ERROR
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
1
0.8
0.6
0.4
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
0.8
f
V
= 750 KSPS,
S
f
V
= 750 KSPS,
0.6
S
= 4.096 V
ref
= 2.5 V
ref
0.4
0.2
0.2
0
−0.2
−0.4
−0.6
0.0
−0.2
−0.4
−0.6
−0.8
−0.8
−1
−1
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 9
Figure 10
INTEGRAL NONLINEARITY
vs
DIFFERENTIAL NONLINEARITY
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
0.6
0.4
MAX
MAX
0.5
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
0.2
0
0
f
V
= 750 KSPS,
f
V
= 750 KSPS,
= 4.096 V
S
S
ref
= 4.096 V
ref
−0.5
−0.2
MIN
−1
MIN
35
−0.4
−1.5
−0.6
−40
−15
T
10
60
85
−40
−15
T
A
10
35
60
85
− Free-Air Temperature − °C
− Free-Air Temperature − °C
A
Figure 11
Figure 12
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
INTEGRAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
vs
vs
SAMPLE RATE
SAMPLE RATE
0.5
0.4
0.3
0.2
0.1
0.8
MAX
MAX
0.6
+VA = 5 V,
+VBD = 5 V,
0.4
+VA = 5 V,
T
V
= 255 C,
= 4.096 V
A
+VBD = 5 V,
= 255 C,
0.2
ref
T
A
ref
V
= 4.096 V
0
0
−0.1
−0.2
−0.3
−0.2
−0.4
−0.6
MIN
375
MIN
−0.4
−0.5
−0.8
−1
125
250
500
625
750
125
250
375
500
625
750
Sample Rate − KSPS
Sample Rate − KSPS
Figure 13
Figure 14
GAIN ERROR
vs
OFFSET ERROR
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0.1
0.14
0.135
0.13
T
= 255 C,
= 750 KSPS,
= 4.096 V
T
= 255 C,
= 750 KSPS,
= 4.096 V
A
A
f
V
f
V
0.08
0.06
S
S
ref
ref
0.04
0.02
0.0
−0.02
−0.04
−0.06
0.125
0.12
−0.08
−0.1
4.75
5.25
5
4.75
5
5.25
V
DD
− Supply Voltage − V
V
DD
− Supply Voltage − V
Figure 15
Figure 16
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
SUPPLY CURRENT
vs
DIFFERENTIAL NONLINEARITY
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
25.6
0.6
0.4
0.2
T
= 255 C,
= 750 KSPS,
= 4.096 V
A
MAX
25.4
25.2
f
V
S
ref
T
= 255 C,
= 750 KSPS,
= 4.096 V
A
f
V
S
25
ref
24.8
24.6
24.4
0
−0.2
24.2
MIN
24
−0.4
−0.6
23.8
23.6
4.75
5.25
5
4.75
5.25
5
V
− Supply Voltage − V
V
DD
− Supply Voltage − V
DD
Figure 17
Figure 18
INTEGRAL NONLINEARITY
vs
DIFFERENTIAL NONLINEARITY
vs
SUPPLY VOLTAGE
REFERENCE VOLTAGE
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
MAX
MAX
T
= 255 C,
= 750 KSPS,
= 4.096 V
A
f
V
S
ref
+VBD = 5 V,
+VA = 5 V,
0
f
V
= 750 KSPS,
S
−0.2
= 4.096 V
ref
0
−0.4
−0.6
−0.8
−1
−0.2
MIN
MIN
−0.4
−0.6
−1.2
2.5
2.84
V
3.18
3.52
3.86
4.2
4.75
5
5.25
V
DD
− Supply Voltage − V
− Reference Voltage − V
ref
Figure 19
Figure 20
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
OFFSET ERROR
vs
REFERENCE VOLTAGE
INTEGRAL NONLINEARITY
vs
REFERENCE VOLTAGE
0.8
0.5
0.4
0.3
0.2
+VBD = 5 V,
+VA = 5 V,
0.6
MAX
T
= 255 C,
A
f
S
= 750 KSPS
0.4
0.2
+VBD = 5 V,
+VA = 5 V,
T
= 255 C,
= 750 KSPS
A
f
S
0.1
0
0
−0.2
−0.4
−0.6
−0.8
−0.1
−0.2
−0.3
MIN
3.18
−0.4
−0.5
−1
−1.2
2.5
2.84
3.52
3.86
4.2
2.5
2.84
3.18
3.52
3.86
4.2
V
ref
− Reference Voltage − V
V
ref
− Reference Voltage − V
Figure 21
Figure 22
SIGNAL-TO-NOISE RATIO
vs
TOTAL HARMONIC DISTORTION
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
−80
−85
−90
−95
90
89
88
+VA = 5 V,
+VBD = 5 V,
f = 99 kHz,
i
S
f
= 750 KSPS,
v = 4 V
,
I
pp
V
= 4.096 V
ref
−100
−105
−110
−115
−120
87
+VA = 5 V,
+VBD = 5 V,
f = 99 kHz,
i
S
86
85
f
= 750 KSPS,
v = 4 V
,
I
pp
V
= 4.096 V
ref
−40
−15
T
10
35
60
85
−40
−15
10
35
60
85
T
A
− Temperature − 5 C
− Free-Air Temperature − °C
A
Figure 23
Figure 24
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
SPURIOUS FREE DYNAMIC RANGE
SIGNAL-TO-NOISE AND DISTORTION
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
90
89
88
87
86
85
84
83
82
110
105
100
95
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
f = 99 kHz,
f = 99 kHz,
i
S
i
S
f
= 750 KSPS,
f
= 750 KSPS,
V = 4 V
,
V = 4 V
,
I
pp
= 4.096 V
I
pp
= 4.096 V
V
ref
V
ref
90
85
80
75
70
81
80
−40
−15
10
35
60
85
−40
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 25
Figure 26
SIGNAL-TO-NOISE RATIO
vs
EFFECTIVE NUMBER OF BITS
vs
FREE-AIR TEMPERATURE
INPUT FREQUENCY
90
89
88
87
86
85
15
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
14.8
f = 99 kHz,
T
= 255 C,
= 750 KSPS,
i
S
A
14.6
14.4
f
= 750 KSPS,
f
S
V = 4 V
,
V = 4 V ,
I
pp
= 4.096 V
I
pp
= 4.096 V
V
ref
V
ref
14.2
14
13.8
13.6
13.4
13.2
13
10
100
1
−40
−15
10
35
60
85
f − Input Frequency − kHz
i
T
A
− Free-Air Temperature − °C
Figure 27
Figure 28
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE AND DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
−80
90
89
88
87
86
85
84
83
+VA = 5 V,
+VBD = 5 V,
= 750 KSPS,
+VA = 5 V,
+VBD = 5 V,
f
S
I
−85
−90
f
= 750 KSPS,
S
I
V = 4 V
,
V = 4 V
V
,
pp
pp
V = 4.096 V
ref
= 4.096 V
ref
−95
−100
−105
−110
82
81
80
10
100
10
100
1
1
f − Input Frequency − kHz
i
f − Input Frequency − kHz
i
Figure 29
Figure 30
SPURIOUS FREE DYNAMIC RANGE
EFFECTIVE NUMBER OF BITS
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
120
115
110
105
100
95
15
14.8
14.6
14.4
14.2
14
+VA = 5 V,
+VBD = 5 V,
+VA = 5 V,
+VBD = 5 V,
f
= 750 KSPS,
S
I
f
= 750 KSPS,
S
I
V = 4 V
V
,
pp
V = 4 V
V
,
pp
= 4.096 V
ref
= 4.096 V
ref
13.8
13.6
13.4
13.2
13
90
85
80
10
100
1
1
10
100
f − Input Frequency − kHz
f − Input Frequency − kHz
i
i
Figure 31
Figure 32
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
+VA SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SAMPLE RATE
FREE-AIR TEMPERATURE
26
25.5
25
25.8
+VA = 5.25 V,
+VBD = 5.25 V,
+VA = 5.25 V,
+VBD = 5.25 V,
25.7
25.6
25.5
25.4
25.3
25.2
25.1
f
V
= 750 KSPS,
= 4.096 V
T
V
= 255 C,
= 4.096 V
S
ref
A
ref
24.5
24
23.5
23
22.5
22
21.5
−40
−15
10
35
60
85
125
250
375
500
625
750
Sample Rate − KSPS
T
A
− Free-Air Temperature − °C
Figure 33
Figure 34
INTEGRAL NONLINEARITY
3
+VA = 5 V,
+VBD = 5 V,
2
1
0
T
= 255 C,
A
f
= 750 KSPS,
S
V
= 4.096 V
ref
−1
−2
−3
0
16384
32768
Code
49152
65536
Figure 35
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
DIFFERENTIAL NONLINEARITY
3
+VA = 5 V,
2
1
+VBD = 5 V,
T
= 255 C, f = 750 KSPS,
= 4.096 V
A
S
V
ref
0
−1
−2
−3
0
16384
32768
Code
49152
65536
Figure 36
FFT
0
+VA = 5 V,
+VBD = 3 V,
= 255 C, f = 750 KSPS,
−20
−40
−60
T
A
S
f = 99 kHz, V = 4 V ,
pp
i
I
16384 Points,V = 4.096 V
ref
−80
−100
−120
−140
−160
−180
75000
150000
225000
300000
0
375000
f − Input Frequency − Hz
i
Figure 37
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
APPLICATION INFORMATION
MICROCONTROLLER INTERFACING
ADS8371 to 8-Bit Microcontroller Interface
Figure 38 shows a parallel interface between the ADS8371 and a typical microcontroller using the 8-bit data bus.
The BUSY signal is used as a falling-edge interrupt to the microcontroller.
Analog 5 V
REF 3040
0.1 µF
OUT
AGND
10 µF
100 Ω
Ext Ref Input
0.1 µF
Analog Input
Micro
Controller
Digital 3 V
AD8371
0.1 µF
GPIO
GPIO
GPIO
RD
CS
BDGND
+VBD
BYTE
CONVST
RD
1000 Ω
BDGND
AD[7:0]
DB[15:8]
Figure 38. ADS8371 Application Circuitry
23
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
PRINCIPLES OF OPERATION
The ADS8371 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution which inherently includes a sample/hold function. See Figure 38 for
the application circuit for the ADS8371.
The conversion clock is generated internally. The conversion time of 1.13 µs is capable of sustaining a 750-kHz
throughput.
The analog input is provided to two input pins: +IN and −IN. When a conversion is initiated, the differential input on
these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected
from any internal function.
REFERENCE
The ADS8371 can operate with an external reference with a range from 2.5 V to 4.2 V. The reference voltage on the
input pin 1 (REFIN) of the converter is internally buffered. A clean, low noise, well-decoupled reference voltage on
this pin is required to ensure good performance of the converter. A low noise band-gap reference like the REF3040
can be used to drive this pin. A 0.1-uF decoupling capacitor is required between pin 1 and pin 48 of the converter.
This capacitor should be placed as close as possible to the pins of the device. Designers should strive to minimize
the routing length of the traces that connect the terminals of the capacitor to the pins of the converter. An RC network
can also be used to filter the reference voltage. A 100-Ω series resistor and a 0.1-uF capacitor, which can also serve
as the decoupling capacitor, can be used to filter the reference voltage.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and −IN inputs is captured on the
internal capacitor array. The voltage on the −IN input is limited between –0.2 V and 0.2 V, allowing the input to reject
small signals which are common to both the +IN and −IN inputs. The +IN input has a range of –0.2 V to V + 0.2 V.
ref
The input span (+IN − (−IN)) is limited to 0 V to V
.
ref
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8371 charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage
must be able to charge the input capacitance (45 pF) to an 16-bit settling level within the acquisition time (200 ns)
of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN
and −IN inputs and the span (+IN − (−IN)) should be within the limits specified. Outside of these ranges, the
converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters
should be used.
Care should be taken to ensure that the output impedance of the sources driving the +IN and −IN inputs are matched.
If this is not observed, the two inputs could have different setting times. This may result in offset error, gain error, and
linearity error which changes with temperature and input voltage.
The analog input to the converter needs to be driven with a low noise, high-speed op-amp like the THS4031. An RC
filter is recommended at the input pins to low-pass filter the noise from the source. A series resistor of 15 Ω and a
decoupling capacitor of 200 pF is recommended.
The input to the converter is a unipolar input voltage in the range 0 V to V . The THS4031 can be used in the source
ref
follower configuration to drive the converter.
24
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SLAS390A − JUNE 2003 − REVISED DECEMBER 2003
ADS8371
+IN
Unipolar Input
_
+
15 Ω
THS4031
_
+
200 pF
−IN
50 Ω
Figure 39. Unipolar Input to Converter
In systems where the input is bipolar, the THS4031 can be used in the inverting configuration with an additional DC
bias applied to its + input so as to keep the input to the ADS8371 within its rated operating voltage range. This
configuration is also recommended when the ADS8371 is used in signal processing applications where good SNR
and THD performance is required. The DC bias can be derived from the REF3020 or the REF3040 reference voltage
ICs. The input configuration shown below is capable of delivering better than 87-dB SNR and –90-db THD at an input
frequency of 100 kHz. In case bandpass filters are used to filter the input, care should be taken to ensure that the
signal swing at the input of the bandpass filter is small so as to keep the distortion introduced by the filter minimal.
In such cases, the gain of the circuit shown in Figure 40 can be increased to keep the input to the ADS8371 large
to keep the SNR of the system high. Note that the gain of the system from the + input to the output of the THS4031
in such a configuration is a function of the gain of the AC signal. A resistor divider can be used to scale the output
of the REF3020 or REF3040 to reduce the voltage at the DC input to THS4031 to keep the voltage at the input of
the converter within its rated operating range.
ADS8371
Vdc
Vac
_
+
100 Ω
THS4031
+IN
360 Ω
_
+
33 nF
−IN
360 Ω
Figure 40. Bipolar Input to Converter
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their requirements.
The ADS8371 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 40 ns (after the 40 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The BUSY output is brought high
immediately following CONVST going low. BUSY stays high throughout the conversion process and returns low when
the conversion has ended. Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with
the falling edge of CS when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST
goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus
with the conversion.
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Digital Inputs
The converter switches from sample to hold mode at the falling edge of the CONVST input pin. A clean and low jitter
falling edge is important to the performance of the converter. A sharp falling transition on this pin can affect the voltage
that is acquired by the converter. A falling transition time in the range of 10 ns to 30 ns is required to achieve the rated
performance of the converter. A resistor of approximately 1000 Ω (10% tolerance) can be placed in series with the
CONVST input pin to satisfy this requirement.
The other digital inputs to the ADS8371 do not require any resistors in series with them. However, certain precautions
are necessary to ensure that transitions on these inputs do not affect converter performance. It is recommended that
all activity on the input pins happen during the first 400 ns of the conversion period. This allows the error correction
circuits inside the device to correct for any errors that these activities cause on the converter output. For example,
when the converter is operated with CS and RD tied to ground, the signal CONVST can be brought low to initiate
a conversion and brought high after a duration not exceeding 400 ns. Figure 41 shows the recommended timing for
the CONVST input with RD and CS tied low.
t
t
acq
conv
(1)
125 ns
(1)
730 ns
400 ns
w1<400ns
t
CONVST
CS = 0
RD = 0
BUSY
(1)
Quiet Zone (No bus activity)
Figure 41. Timing for CONVST When CS = RD = BDGND
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A similar precaution applies when RD is used to three-state the output buffers after a data-read operation. A minimum
quite period of 125 ns is also required from the instant the data is changed on the bus (such as the falling or rising
edge of RD, the falling or rising edge of BYTE, and the falling is made available on the data bus pins to the sampling
instant (falling edge of CONVST). Figure 42 shows the timing of the input control signals that allow these conditions
to be satisfied.
t
t
acq
conv
(1)
730 ns
(1)
125 ns
400 ns
t
< 400 ns
w1
CONVST
CS = 0
t
h1
< 400 ns
t
h2
> 125 ns
RD
BUSY
(1)
Quiet Zone (No bus activity)
Figure 42. Bus Activity Split to Avoid Quiet Zone
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If the RD pin is brought high to three-state the data buses, the three-stating operation should occur 125 ns before
the end of the acquisition phase. Figure 43 shows the recommended timing for using the ADS8381 in this mode of
operation. The same principle applies to other bus activities such as BYTE.
t
t
acq
conv
(1)
125 ns
(1)
730 ns
400 ns
t
< 400 ns
w1
CONVST
CS = 0
t
h2
> 125 ns
RD
BUSY
(1)
Quiet Zone (No bus activity)
Figure 43. Read Timing if the Bus Needs to be Three-Stated
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Reading Data
The ADS8371 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active when
CS and RD are both low. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for
multiword read operations. BYTE is used whenever lower bits on the bus are output on the higher byte of the bus.
Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
ANALOG VALUE
(+V
DIGITAL OUTPUT
STRAIGHT BINARY
)
ref
Least significant bit (LSB)
+Full scale
(+V )/65536
BINARY CODE
HEX CODE
FFFF
ref
(+V ) – 1 LSB
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
ref
(+V )/2
Midscale
8000
7FFF
0000
ref
Midscale – 1 LSB
Zero
(+V )/2 – 1 LSB
ref
0 V
The output data is a full 16-bit word (D15−D0) on DB15–DB0 pins (MSB−LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15−DB8. In this case
two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins
DB15−DB8, then bringing BYTE high. When BYTE is high, the low bits (D7−D0) appear on pins DB15−D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Table 2. Conversion Data Readout
DATA READ OUT
BYTE
DB15−DB8 PINS DB7−DB0 PINS
High
Low
D7−D0
All one’s
D7−D0
D15−D8
RESET
The device can be reset through the use of the combination fo CS and CONVST. Since the BUSY signal is held at
high during the conversion, either one of these conditions triggers an internal self-clear reset to the converter.
D
D
Issue a CONVST when CS is low and internal CONVERT state is high. The falling edge of CONVST starts a
reset.
Issue a CS (select the device) while internal CONVERT state is high. The falling edge of CS causes a reset.
Once the device is reset, all output latches are cleared (set to zeroes) and the BUSY signal is brought low. A new
sampling period is started at the falling edge of the BUSY signal immediately after the instant of the internal reset.
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LAYOUT
For optimum performance, care should be taken with the physical layout of the ADS8371 circuitry.
As the ADS8371 offers single-supply operation, it will often be used in close proximity with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the
higher the switching speed, the more difficult it is to achieve good performance from the converter.
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any
single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages
can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,
or high power devices.
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external
event.
On average, the ADS8371 draws very little current from an external reference as the reference voltage is internally
buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass
capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor is recommended from pin 1 (REFIN) directly
to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under the device.
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog
ground. Avoid connections which are too close to the grounding point of a microcontroller or digital signal processor.
If required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists
of an analog ground plane dedicated to the converter and associated analog circuitry.
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from
the connection for digital logic until they are connected at the power entry point. Power to the ADS8371 should be
clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible.
See Table 3 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some
situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up
of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency
noise.
Table 3. Power Supply Decoupling Capacitor Placement
POWER SUPPLY PLANE
CONVERTER ANALOG SIDE
CONVERTER DIGITAL SIDE
SUPPLY PINS
Pin pairs that require shortest path to decoupling capacitors
Pins that require no decoupling
(4,5), (8,9), (10,11), (13,15),
(43,44), (45,46)
(24,25)
37, 38
12, 14
30
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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