AFE1115E-1/1KG4_技术文档

®

AFE1115

®

HDSL/MDSL ANALOG FRONT END WITH VCXO

● +5V ONLY (5V or 3.3V Digital)

FEATURES

● SCALEABLE DATA RATE

● COMPLETE HDSL ANALOG INTERFACE

● 300mW POWER DISSIPATION

● E1, T1 AND MDSL OPERATION

● 56-PIN SSOP

● VCXO AND VCXO CONTROL CIRCUITRY

DESCRIPTION

Burr-Brown’s Analog Front End greatly reduces the

size and cost of an HDSL (High bit rate Digital

Subscriber Line) system by providing all of the active

analog circuitry needed to connect an HDSL digital

signal processor to an external compromise hybrid and

a HDSL line transformer. The transmit and receive

filter responses automatically change with clock fre-

quency—allowing the AFE1115 to operate over a

range of data rates from 196kbps to 1.168Mbps.

Crystal Oscillator) control DAC and VCXO circuitry.

The transmit section generates, filters, and buffers

outgoing 2B1Q data. The receive section filters and

digitizes the symbol data received on the telephone

line. Data to the VCXO and symbol data are sent to the

AFE1115 via two serial interfaces; the receive data is

available as a 14-bit parallel word. This IC operates on

a single 5V supply. The digital circuitry in the unit can

be connected to a supply from 3.3V to 5V. It is housed

in a small 56-pin SSOP package.

Functionally, this unit consists of a transmit and a

receive section with a VCXO (Voltage Controlled

vcDATA

vcDAC

VCXO

vcSCLK

DAC

VCXO Output

vcLE

VCXO Input

Oscillator

VCXO Output Clock

txLINE+

txLINE–

Pulse

Former

Filter

Output

Buffer

REF_P

V_CM

PLL_OUT

Voltage

Reference

PLL_IN

Transmit

Control

txDATA+

REF_N

txSCLK

txCLK

rxSYNC

Receive

rxLOOP

Control

rxLINE+

rxLINE–

rxHYB+

rxHYB–

2

rxGAIN

Delta-Sigma

Modulator

14

Decimation

rxDATA

Filter

International Airport Industrial Park

•

Mailing Address: PO Box 11400, Tucson, AZ 85734

FAXLine: (800) 548-6133 (US/Canada Only)

• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

®

PDS-1384

Printed in U.S.A. July, 1997

AFE1115

1

SBWS005

SPECIFICATIONS

Typical at 25°C, AV_DD= +5V, DV_DD= +3.3V, f_tx= 584kHz (E1 rate), unless otherwise specified.

AFE1115E

TYP

PARAMETER

COMMENTS

MIN

MAX

UNITS

RECEIVE CHANNEL

Number of Inputs

Input Voltage Range

Common-Mode Voltage

Input Impedance All Inputs

Input Capacitance

Differential

Balanced Differential⁽¹⁾

2

±3.0

+2.5

V

See Typical Performance Curves

10

pF

Input Gain Matching

Resolution

Line Input vs Hybrid Input

±2

%

Bits

14

Programmable Gain

Settling Time for Gain Change

Gain + Offset Error

Output Data Coding

Output Data Rate, rxSYNC⁽³⁾

Three Gains: –3dB, 3dB, and 9dB

–3

+9

dB

6

5

Symbol Periods

%FSR⁽²⁾

Tested at Each Gain Range

Two’s Complement

98

584

kHz

TRANSMIT CHANNEL

Transmit Clock Rate, f_tx

T1 Transmit –3dB Point

T1 Rate Power^{(4, 5)}

E1 Transmit –3dB Point

E1 Transmit Power^{(4, 5)}

Pulse Output

Symbol Rate

Bellcore TA-NWT-3017 Compliant

See Test Method Section

ETSI RTR/TM-03036 Compliant

See Test Method Section

98

13

584

14

kHz

dBm

kHz

dBm

196

292

14

See Typical Performance Curves

Common-Mode Voltage, V_CM

Output Resistance⁽⁶⁾

AV_DD/2

1

V

Ω

DC to 1MHz

TRANSCEIVER PERFORMANCE

Uncancelled Echo⁽⁷⁾

rxGAIN = –3dB, Loopback Enabled

rxGAIN = –3dB, Loopback Disabled

rxGAIN = 3dB, Loopback Disabled

rxGAIN = 9dB, Loopback Disabled

–67

–71

–73

dB

VCXO PERFORMANCE

VCXO Control DAC Resolution

VCXO Control DAC Output

VCXO Performance

8

Bits

V

Positive Full Scale Output

Negative Full Scale Output

See VCXO Circuit and Layout Section

4.5

0.5

DIGITAL INTERFACE⁽⁶⁾

Logic Levels

V_IH

V_IL

V_OH

V_OL

|I_IH| < 10µA

|I_IL| < 10µA

I_OH= –20µA

I_OL= 20µA

DV_DD–1

–0.3

DV_DD–0.5

DV_DD+0.3

+0.8

V

+0.4

POWER

Analog Power Supply Voltage

Digital Power Supply Voltage

Power Dissipation^{(4, 5, 8)}

PSRR

Specification

Operating Range

Specification

5

V

4.75

3.15

5.25

3.3

Operating Range

AV_DD= 5V, DV_DD= 3.3V,

AV_DD= DV_DD= 5V

V

300

350

60

mW

dB

TEMPERATURE RANGE

Operating⁽⁶⁾

–40

+85

°C

NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common-

mode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol

rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP

and txLINEN). (5) See the Test Method section of this data sheet for more information. (6) Guaranteed by design and characterization. (7) Uncancelled Echo is a

measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications sections

of this data sheet for more information. (8) Power dissipation includes only the power dissipated with in the component and does not include power dissipated in the

external loads. See the Discussion of Specifications section for more information.

®

AFE1115

2

PIN CONFIGURATION

PACKAGE/ORDERING INFORMATION

PACKAGE

DRAWING TEMPERATURE

PRODUCT

PACKAGE

NUMBER⁽¹⁾

RANGE

vcOUT

vcINP

1

2

3

4

5

6

7

8

9

56 DGND

55 vcSCLK

54 vcDATA

53 vcLATCH

52 PLL_IN

AFE1115E

56-Pin Plastic SSOP

346

–40°C to +85°C

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix C of Burr-Brown IC Data Book.

vcCLK

DVDD

Unused Pin

txCLK

ELECTROSTATIC

DISCHARGE SENSITIVITY

51 PLL_OUT

50 AV_DD

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

txSCLK

txDATA

49 AGND

48 AGND

47 vcDAC

46 AGND

45 txLINE+

44 AV_DD

rxDATA0 10

rxDATA1 11

rxDATA2 12

rxDATA3 13

rxDATA4 14

rxDATA5 15

GNDD 16

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

43 txLINE–

42 AGND

41 AV_DD

AFE1115E

DV_DD17

40 vrREF

39 V_CM

rxDATA6 18

rxDATA7 19

rxDATA8 20

rxDATA9 21

rxDATA10 22

rxDATA11 23

rxDATA12 24

rxDATA13 25

Unused Pin 26

rxSYNC 27

rxGAIN0 28

38 vrREF

37 AGND

36 AGND

35 rxLINE+

34 rxLINE–

33 rxHYB+

32 rxHYB–

31 AV_DD

30 rxLOOP

29 rxGAIN1

®

3

AFE1115

PIN DESCRIPTIONS

PIN #

TYPE

NAME

DESCRIPTION

1

2

Output

Input

vcOUT

vcINP

VCXO Output

VCXO Input

3

4

5

6

7

8

9

Output

Power

NC

Input

vcCLK

DVDD

Unused Pin

txCLK

txSCLK

txDATA

rxDATA0

rxDATA1

rxDATA2

rxDATA3

rxDATA4

rxDATA5

GNDD

VCXO Output Clock

Digital Supply (+3.3 to +5V)

Transmit Baud Clock (XMTLE signal) (1168kHz for E1)

Transmit Serial Clock

Transmit Data Input

ADC Output Bit-0

ADC Output Bit-1

ADC Output Bit-2

ADC Output Bit-3

ADC Output Bit-4

ADC Output Bit-5

Digital Ground

Digital Supply (+3.3 to +5V)

ADC Output Bit-6

ADC Output Bit-7

ADC Output Bit-8

ADC Output Bit-9

ADC Output Bit-10

ADC Output Bit-11

ADC Output Bit-12

Input

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

Output

Ground

Power

Output

NC

Input

Power

Input

Ground

Output

Power

Ground

Output

Power

Output

Ground

Output

Ground

Power

Output

Input

DV_DD

rxDATA6

rxDATA7

rxDATA8

rxDATA9

rxDATA10

rxDATA11

rxDATA12

rxDATA13

Unused Pin

rxSYNC

rxGAIN0

rxGAIN1

rxLOOP

AV_DD

rxHYB–

rxHYB+

rxLINE–

rxLINE+

AGND

vrREFP

V_CM

vrREFN

AV_DD

AGND

txLINE–

AV_DD

txLINE+

AGND

vcDAC

AGND

AV_DD

ADC Output Bit-13

(DV_DDmay be connected for pinout compatibility with AFE1105)

ADC Sync Signal (392kHz for T1, 584kHz for E1)

Receive Gain Control Bit-0

Receive Gain Control Bit-1

Loopback Control Signal (loopback is enabled by positive signal)

Analog Supply (+5V)

Negative Input from Hybrid Network

Positive Input from Hybrid Network

Negative Line Input

Positive Line Input

Analog Ground

Positive Reference Output

Common-mode Voltage (buffered)

Negative Reference Output

Analog Supply (+5V)

Analog Ground

Negative Line Output

Analog Supply (+5V)

Positive Line Output

Analog Ground

VCXO Control

Analog Ground

PLL Ground

PLL Supply

PLL Filter Output

PLL Filter Input

VCXO Control Latch Enable

VCXO Control Data

VCXO Control Serial Clock

Digital Ground

PLL_OUT

PLL_IN

vcLATCH

vcDATA

vcSCLK

DGND

Input

Ground

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

®

AFE1115

4

TYPICAL PERFORMANCE CURVES

At Output of Pulse Transformer

The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AV_DD= +5V, DV_DD= +3.3V, unless otherwise specified.

POWER SPECTRAL DENSITY LIMIT

–20

–38dBm/Hz for T1

–40

–80dB/decade

T1

–40dBm/Hz for E1

E1

–60

–80

–118dBm/Hz

for T1

196kHz

292kHz

–120dBm/Hz

for E1

–100

–120

1K

10K

100K

Frequency (Hz)

1M

10M

CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer.

0.4T 0.4T

B = 1.07

C = 1.00

D = 0.93

QUATERNARY SYMBOLS

NORMALIZED

LEVEL

+3

+1

–1

–3

A

B

C

0.01

1.07

1.00

0.0264

2.8248

2.6400

0.0088

0.9416

0.8800

–0.0088

–0.9416

–0.8800

–0.0264

–2.8248

–2.6400

–2.4552

–0.0792

0.0264

0.4224

0.1320

DON'T DELETE TABLE

UNTIL^D_EKNOWN ²IF^.455T²EEPLE IS LEAVING IT IN?

0.93

0.8184

–0.8184

0.03

–0.01

–0.16

–0.05

0.0792

–0.0264

–0.4224

–0.1320

0.0264

–0.0088

–0.1408

–0.0440

–0.0264

0.0088

0.1408

0.0440

F

G

H

1.25T

A = 0.01

E = 0.03

A = 0.01

F = –0.01

–1.2T

H = –0.05

14T

F = –0.01

50T

G = –0.16

–0.6T 0.5T

CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at Transformer Output.

INPUT IMPEDANCE vs BIT RATE

200

150

100

T1 = 784kbps,

45kΩ

E1 = 1168kbps,

30kΩ

50

0

100

300

500

700

900

1100

1300

Bit Rate (kbps)

CURVE 3. Input Impedance of rxLINE and rxHYB.

®

5

AFE1115

in remote units for clock recovery. The VCXO is formed

with the on-board circuitry plus external crystal and varactor

diodes. The VCXO control DAC receives control data through

a serial interface which sets a voltage level at the output of

the DAC. The DAC output controls the frequency of the

VCXO. To achieve specified analog performance when

using the VCXO, the crystal frequency of the VCXO must

be 48x the baud rate.

THEORY OF OPERATION

The transmit channel consists of a switched-capacitor pulse

forming network followed by a differential line driver. The

pulse forming network receives symbol data through a serial

interface and generates a standard 2B1Q output waveform.

The output meets the pulse mask and power spectral density

requirements defined in European Telecommunications Stan-

dards Institute document RTR/TM-03036 for E1 mode and

in sections 6.2.1 and 6.2.2.1 of Bellcore technical advisory

TA-NWT-001210 for T1 mode. The differential line driver

uses a composite output stage combining class B operation

(for high efficiency driving large signals) with class AB

operation (to minimize crossover distortion).

rxLOOP INPUT

rxLOOP is the loopback control signal. When enabled, the

rxLINE+ and rxLINE– inputs are disconnected from the

AFE. The rxHYB+ and rxHYB– inputs remain connected.

Loopback is enabled by applying a positive signal (Logic 1)

to rxLOOP.

The receive channel is designed around a fourth-order delta

sigma A/D converter. It includes a difference amplifier

designed to be used with an external compromise hybrid for

first order analog echo cancellation. A programmable gain

amplifier with gains of –3dB to +9dB is also included. The

delta sigma modulator operating at a 24X oversampling ratio

produces a parallel 14-bit output at symbol rates up to

584kHz. The basic functionality of the AFE1115 is illus-

trated in Figure 1 shown below.

ECHO CANCELLATION IN THE AFE

The rxHYB input is designed to be subtracted from the

rxLINE input for first order echo cancellation. To accom-

plish this, note that the rxLINE input is connected to the

same polarity signal at the transformer (positive to positive

and negative to negative) while the rxHYB input is con-

nected to opposite polarity through the compromise hybrid

(negative to positive and positive to negative) as shown in

Figure 2.

The receive channel operates by summing the two differen-

tial inputs, one from the line (rxLINE) and the other from the

compromise hybrid (rxHYB). These two inputs are con-

nected so that the hybrid signal is subtracted from the line

signal. This connection is described in the paragraph titled

“Echo Cancellation in the AFE”. The equivalent gain for

each input in the difference amp is one. The resulting signal

then passes to a programmable gain amplifier which can be

set for gains of –3dB through +9dB. The ADC converts the

signal to a 14-bit digital word, rxD13-rxD0.

RECEIVE DATA CODING

The data from the receive channel A/D converter is coded in

two’s complement.

ANALOG INPUT

OUTPUT CODE (rxDATA)

Positive Full Scale

Mid Scale

Negative Full Scale

01111111111111

00000000000000

10000000000000

An independent VCXO control DAC and VCXO circuitry is

also included on the chip. This VCXO is designed to be used

vcDATA

vcDAC

VCXO

DAC

VCXO Output

vcSCLK

VCXO Input

vcLE

VCXO

VCXO Output Clock

Transformer

Switched Capacitor

Pulse Former

Telephone

Wire Pair

Line Driver

Hybrid

DSP

PLL

∆Σ

ADC

Programmable

Gain Amp

Digital

Filter

Difference

Amplifier

AFE1115

FIGURE 1. Functional Block Diagram of AFE1115 Circuit.

®

AFE1115

6

0.1µF

txPLL_OUT

txPLL_IN

REF_P

V_CM

REF_N

1kΩ

Parasitic Capacitance

Must be Minimized at

These Points.

200Ω

0.1µF

DV_DD

68.1kΩ

VCXO Input, 2

BB809

150pF

68.1kΩ

VCXO Output, 1

150pF

1kΩ

68.1kΩ

vcDAC, 47

0.1µF

1:2.3 Transformer

Tip

VCXO Output Clock, 3

vcDATA

txLINE_P

txLINE_N

0.01µF

vcSCLK

Ring

vcLE

–

+

0.01µF

Input Antialias Filter

fc 2xSymbol Rate

Compromise

Hybrid

txDAT

–

750Ω

txCLK

rxHYB+

rxSYNC

rxGAIN

rxLOOP

rxG1

AFE1115

100pF

750Ω

rxD13

rxHYB–

rxLINE–

750Ω

PGND

DGND

AGND

100pF

750Ω

rxLINE+

DV_DD

AV_DD

AV_DDAV_DDAV_DD

5V to 3.3V Digital

0.1µF

5V Analog

1 - 10µF

0.1µF 0.1µF 0.1µF

0.1µF

5 - 10Ω resistor may be

needed for isolation

FIGURE 2. Basic Connection Diagram.

RECEIVE CHANNEL PROGRAMMABLE

GAIN AMPLIFIER

rxHYBAND rxLINE INPUT ANTI-ALIASING FILTERS

An external input anti-aliasing filter is needed on the hybrid

and line inputs as shown in the Basic Connection Diagram

above. The –3dB frequency of the input anti-aliasing filter

for the rxLINE and rxHYB differential inputs should be

approximately 1MHz for E1 and T1 symbol rates. Suggested

values for the filter are 750Ω for each of the two input

resistors and 100pF for the capacitor. Together the two

750Ω resistors and the 100pF capacitor result in a 3dB

frequency of just over 1MHz. The 750Ω input resistors will

result in a minimal voltage divider loss with the input

impedance of the AFE1115.

The gain of the amplifier at the input of the Receive Channel

is set by two gain control pins, rxGAIN1 and rxGAIN0. The

resulting gain between –3dB and +9dB is shown below.

rxGAIN1

rxGAIN0

GAIN

–3dB

+3dB

+9dB

0

1

0

1

0

SCALEABLE DATA RATE

For speed less than E1, the anti-aliasing filters will give best

performance with 3dB frequency approximately equal to

two times the symbol rate. For instance, a 3dB frequency of

400kHz may be used for a single line symbol rate of 196k

symbols per second.

The AFE1115 scales operation with the clock frequency. All

internal filters and the pulse former change frequency with

the clock speed so that the unit can be used at different

frequencies just by changing the clock speed.

®

7

AFE1115

rxHYB AND rxLINE INPUT COMMON-MODE

OPTIONAL VOLTAGE

0.1µF

375Ω

The AFE1115 will meet specifications with the application

circuit shown in the Basic Connection Diagram (Figure 2)

above. However, slightly improved performance may be

obtained with the Hybrid input (rxHYB) and the Line input

(rxLINE) set to a common mode voltage of 1.5V. The

negative reference output pin (vrREFN, pin 40) provides a

good 1.5V level to use to set the common-mode voltage.

The circuit shown in Figure 3 can be used to set the

common-mode voltage of the Line input to 1.5V.

rxLINE–

2kΩ

to vrREFN

(1.5V)

to Line

AFE

100pF

2kΩ

0.1µF

375Ω

rxLINE+

A similar circuit can be used to set the Hybrid input to 1.5V.

Another option for the Hybrid input is to design the external

compromise hybrid so that the signal into the rsHYB inputs

is centered at 1.5V. If the compromise hybrid circuit is AC

coupled to the rxHYB inputs, an external pull-up resistor to

vrREFN may be needed to center the input at 1.5V.

FIGURE 3. Optional rxLINE Input Common-mode Voltage

Control.

TRANSMIT DATA TIMING

t₁

txSCLK

(tx serial clock)

t₂

t₃

t₄

t₅

txCLK

(baud clock)

t₆

t₇

txDATA

(tx data input)

MSB

Bit 1

LSB

Bit 16

Bit 2

Bit 3

t₈t₉

VCXO CONTROL TIMING

t₁

vcSCLK

(serial clock)

t₂

t₃

t₄

t₅

vcLE

(latch enable)

t₆

t₇

vcDATA

(data)

MSB

Bit 1

LSB

Bit 16

Bit 2

Bit 3

t₈t₉

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

t₉

Serial Clock Period

Serial Clock LOW

Serial Clock HIGH

35

15

10

15

10

ns

Delay of 16th clock rising edge to falling edge of txCLK or vcLE

Dealy of txCLK or vcLE to the next rising edge of Serial Clock

txCLK or vcLE HIGH

txCLK or vcLE LOW

DATA setup time

DATA hold time

FIGURE 4. Timing Diagram.

®

AFE1115

8

TRANSMIT SYMBOL DATA

VCXO CONTROL D/A CONVERTER DATA

During each symbol period transmit symbol data are sent to

the AFE1115 in serial format through the txDATA input pin.

A 16 bit word is sent to the AFE1115 to determine the

symbol that is transmitted by the AFE1115. The symbol data

is contained in the first three bits of the data, the remaining

13 bits of the 16 bit word are ignored.

During each symbol period VCXO control D/A converter

data is sent to the AFE1115 in serial format through the

vcDATA input pin. A 16 bit word is sent to the AFE1115 to

determine the output of the VCXO control D/A converter.

The VCXO control D/A converter is connected to the

VCXO circuit to control the VCXO frequency. The D/A

converter input is contained in the first eight bits of the data,

the remaining eight bits of the 16 bit word are ignored.

The most significant bit (MSB) is the transmit enable bit.

When the MSB is a logic 0, a zero symbol only is transmit-

ted regardless of the state of the other two bits. When the

MSB is a logic 1, bits 2 and 3 determine the symbol

transmitted as shown in the table below.

INPUT CODE (vcDATA)

MSB

ANALOG OUTPUT

01111111XXXXXXXX

00000000XXXXXXXX

10000000XXXXXXXX

Negative Full Scale (+0.5V)

Mid Scale (+2.5V)

MSB - BIT 1

BIT 2

BIT 3

2B1Q SYMBOL

Positive Full Scale (+4.5V)

0

1

X

1

0

X

1

0

1

0

O

+3

+1

–1

–3

TABLE II. VCXO Control DAC Output. X = Don’t Care.

TABLE I. Transmit Symbol Data (txDATA). X = Don’t Care.

RECEIVE TIMING

t₁₆

T = one symbol period

txCLK

t₁₅

t₁₀

rxSYNC

t₁₁

t₁₂

Data 1

rxDATA

Data 1a

Data 2

t₁₄

t₁₃

NOTES: (1) rxSYNC can shift to one of 48 discrete delay times from the leading edge of txCLK. (2) Timing

is valid for load capacitance of 10pF or less. (3) It is recommended that rxDATA is read on the rising edge of

rxSYNC. (4) Data 1a is an interpolated value between Data 1 and Data 2.

FIGURE 5. Receive Timing Diagram.

PARAMETER

DESCRIPTION

MIN

TYP

MAX

VALUE

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

rxSYNC Pulse Width

T/24

Delay of rxSYNC from rising edge of txCLK, n = 0 to 47

Nominal Time at Which rxDATA Changes from Data 1 to Data 1a

Nominal Time at Which rxDATA Changes from Data 1a to Data 2

Uncertainty of t12 and t13

nT/48 – T/96

nT/48 + T/96

(n + 1.5) T/48

(n + 25.5) T/48

20

ns

txCLK Pulse Width

T/16

1.7

15T/16

10.2

Symbol Period, T

µs

TABLE III. Receive Timing (n = Delay Increments from txCLK).

9

®

AFE1115

RECEIVE TIMING

Symbol sequences are generated by the tester and applied

both to the AFE and to the input of an adaptive filter. The

output of the adaptive filter is subtracted from the AFE

output to form the uncancelled echo signal. Once the filter

taps have converged, the RMS value of the uncancelled echo

is calculated. Since there is no far-end signal source or

additive line noise, the uncancelled echo contains only noise

and linearity errors generated in the transmitter and receiver.

The rxSYNC signal controls portions of the A/D converter’s

decimation filter and the data output timing of the A/D

converter. It is generated at the symbol rate by the user and

must be synchronized with txCLK. The leading edge of

rxSYNC can occur at the leading edge of txCLK or it can be

shifted by the user in increments of 1/48 of a symbol period

to one of 47 discrete delay times after the leading edge of

txCLK.

The data sheet value for uncancelled echo is the ratio of the

RMS uncancelled echo (referred to the receiver input through

the receiver gain) to the nominal transmitted signal (13.5dBm

into 135Ω, or 1.74Vrms). This echo value is measured under

a variety of conditions: with loopback enabled (line input

disabled); with loopback disabled under all receiver gain

ranges; and with the line shorted (S₁closed in Figure 6).

The bandwidth of the A/D converter decimation filter is

equal to one half of the symbol rate. The A/D converter data

output rate is 2X the symbol rate. The specifications of the

AFE1115 assume that one A/D converter output is used per

symbol period and the other output is ignored. The Receive

Timing Diagram above suggests using the rxSYNC pulse to

read the first data output in a symbol period. Either data

output may be used. Both data outputs may be used for more

flexible post-processing.

POWER DISSIPATION

Approximately 75% of the power dissipation in the AFE1115

is in the analog circuitry, and this component does not

change with clock frequency. However, the power dissipa-

tion in the digital circuitry does decrease with lower clock

frequency. In addition, the power dissipation in the digital

section is decreased with operation from a smaller supply

voltage, such as 3.3V. (The analog supply, must remain in

the range 4.75V to 5.25V.)

DISCUSSION OF

SPECIFICATIONS

UNCANCELLED ECHO

The key measure of transceiver performance is uncancelled

echo. This measurement is made as shown in the diagram of

Figure 6 and the measurement is made as follows. The AFE

is connected to an output circuit including a typical 1:2.3

line transformer. The line is simulated by a 135Ω resistor.

The power dissipation listed in the specifications section

applies under these normal operating conditions: 5V Analog

Power Supply; 3.3V Digital Power Supply; E1 baud rate;

11.6Ω

1:2

5.6Ω

Transmit

Data

txDAT_P

txLINE_P

txLINE_N

135Ω

S₁

1.5kΩ

rxHYB_P

3kΩ

100pF

AFE1115

rxHYB_N

1.5Ω

750Ω

rxLINE_P

100pF

rxLINE_N

750Ω

Uncancelled

Echo

rxD13 - rxD0

FIGURE 6. Uncancelled Echo Test Diagram.

®

AFE1115

10

13.5dBm delivered to the line; and a pseudo-random

equiprobable sequence of HDSL pulses. The power dissipa-

tion specifications includes all power dissipated in the

AFE1115, it does not include power dissipated in the exter-

sible. The placement of the Tantalum capacitor is not as

critical, but should be close to the pin. In each case, the

capacitor should be connected between AV_DDand AGND

(pins 49 and 50). The capacitors should be placed in quiet

analog areas rather than noisy digital areas.

nal

load.

The external power is 16.5dBm, 13.5dBm to the line and

13.5dBm to the impedance matching resistors. The external

load power of 16.5dBm is 45mW. The typical power dissi-

pation in the AFE1115 under various conditions is shown in

In most systems, it will be natural to derive AV_DDfor the

phase-locked loop (PLL) from the AV_DDsupply. A 5Ω to

10Ω resistor should be used to connect PLL AV_DD(pin 49)

to the analog supply. This resistor in combination with the

10µF capacitor form a lowpass filter—keeping glitches on

the analog supply from affecting the phase locked loop.

Ideally, the phase-locked loop power supply would originate

from the analog supply (via the 5Ω to 10Ω resistor) near the

power connector for the printed circuit board. Likewise, the

PLL ground should connect to a large PCB trace or small

ground plane which returns to the power supply connector

underneath the PLL AV_DDsupply path. The PLL “ground

plane” should also extend underneath PLL_INand PLL_OUT

(pins 51 and 52).

TYPICAL POWER

BIT RATE

PER AFE1115

(Symbols/sec)

DISSIPATION

IN THE AFE1115

(mW)

DVDD

(V)

1168 (E1)

784 (T1)

292 (1/4 E1)

3.3

5

3.3

5

3.3

5

300

350

290

330

280

300

TABLE IV. Typical Power Dissipation.

The remaining portion of the AFE1115 should be considered

analog. The four non-PLL AGND pins (pins 36, 37, 42, and

46) should be connected directly to a common analog

ground plane and all non-PLL AV_DDpins should be con-

nected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply.

Table IV.

LAYOUT

The analog front end of an HDSL system has a number of

conflicting requirements. It must accept and deliver digital

outputs at fairly high rates of speed, generate a VCXO clock,

phase-lock to a high-speed digital clock, and convert the line

input to a high-precision (14-bit) digital output. Thus, there

are really four sections of the AFE1115: the digital section,

the phase-locked loop, the VCXO and the analog section.

Ideally, all ground planes and traces and all power planes

and traces should return to the power supply connector

before being connected together (if necessary). Each ground

and power pair should be routed over each other, should not

overlap any portion of another pair, and the pairs should be

separated by a distance of at least 0.25 inch (6mm). One

exception is that the digital and analog ground planes should

be connected together underneath the AFE1115 by a small

trace.

DIGITAL LAYOUT

The power supply for the digital section of the AFE1115 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with a ceramic 0.1µF capacitor placed as

close as possible to digital ground (DGND, pin 16) and

digital power (DV_DD, pin 17). Ideally, both a digital power

supply plane and a digital ground plane should run to and

underneath the digital pins of the AFE1115 (pins 7 through

30). However, DV_DDmay be supplied by a wide printed

circuit board trance. A digital ground plane underneath all

digital pins is strongly recommended. The VCXO circuit

needs special attention for layout. There is a portion of the

external VCXO circuitry which needs to be as far away as

possible from a ground or power plane or other traces. See

the discussion below in the section titled VCXO Circuit and

Layout.

VCXO CIRCUIT AND LAYOUT

The VCXO circuitry is shown in Figure 7. The basic VCXO

circuit consists of on-chip control DAC, amplifiers, Schmidt

triggers, and clock buffer along with an external crystal and

varactor diodes. The control DAC output (vcDAC) varies

the capacitance of the varactor diodes (D1 and D2), which

controls the frequency at which the crystal circuit oscillates.

The buffered clock output is available at pin 3, VCXO Clock

Output.

Important Note: To achieve specified analog performance

when using VCXO, the crystal frequency of the VCXO must

be 48x the baud rate. In addition, the txCLK and the

rxSYNC control signals must be derived from the VCXO

clock so that the edges of the control signal are synchronized

with the 48x crystal frequency. If these recommendations

are followed, the key internal analog decisions are made at

the time of minimum noise. As an example, for an E1 rate

of 1168kbps, the symbol rate is 584k symbols per second. In

this case the VCXO crystal frequency should be 48 x 584k

= 28.032MHz. Likewise, for T1, the crystal frequency should

be 18.816MHz.

ANALOG LAYOUT

The phase-locked loop is powered from AV_DD(pin 50) and

its ground is referenced to AGND (pin 49). Note that AV_DD

must be in the 4.75V to 5.25V range. This portion of the

AFE1115 should be decoupled with both 10µF Tantalum

capacitor and a 0.1µF ceramic capacitor. The ceramic ca-

pacitor should be placed as close to the AFE1115 as pos-

®

11

AFE1115

The performance of the VCXO is critically dependent on the

external components and printed circuit board layout that is

used. The varactor diodes and the crystal are particularly

important components.

Figure 8 shows an example of a printed circuit board layout

of the sensitive VCXO circuitry for the circuit shown in

Figure 7. There should be no ground planes, power planes or

other traces in the white area indicated around the two

sensitive points. The balance of the circuit board should be

covered by ground planes where possible. With the circuit

shown in Figure 7, these typical specifications were achieved.

The printed circuit board layout containing the two varactor

diodes, D1 and D2, in the VCXO external circuitry is critical

to the performance of the VCXO. In particular, the two

connection points of the varactor diodes shown in the Figure

7 must have very low parasitic capacitance to ground to

achieve the best tuning range possible. To achieve lowest

parasitic capacitance to ground, there must be no ground

plane or other PCB traces near these two points. Ground

planes and other traces should be kept 1 cm away from these

two points where possible.

Pull Range at 20MHz

±125ppm

Frequency Range of Crystal that can be used

Crystal Frequency

10MHz to 28MHz

48x baud rate

Parasitic capacitance must be minimized

at these points. No other traces or ground

plane should be inside the dotted box.

AFE1115

DV_DD

68.1kΩ

R₂

D2

VCXO Input, 2

150pF

D1

VCXO Output, 1

68.1kΩ

R₄

68.1kΩ

150pF

R_L

R₅

vcDAC, 47

0.1µF

Buffered VCXO Clock Output

VCXO Clock Output, 3

R_L= 1kΩ for 5V Operation

R_L= 600Ω for 3.3V Operation

D1 = D2 = Philips Semiconductor BB809

FIGURE 7. VCXO Circuitry.

No ground/power planes

or other traces in this area

Sensitive Points

Ground

Plane

To AFE1115 Pin #47

To AFE1115 Pin #2

FIGURE 8. VCXO Circuit Layout, Approximately Two Times Actual Size.

®

AFE1115

12

PACKAGE OPTION ADDENDUM

www.ti.com

14-Oct-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

SSOP

Drawing

AFE1115E-1/1K

OBSOLETE

DL

56

TBD

Call TI

AFE1115E-1/1KG4

DL

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

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型号：	AFE1115E-1/1KG4
厂家：	BURR-BROWN CORPORATION
描述：	HDSL/MDSL Analog Front End with VCXO 56-SSOP 石英晶振压控振荡器
文件：	总14页 (文件大小：177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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