DAC1221 [BB]
16-Bit Low Power DIGITAL-TO-ANALOG CONVERTER; 16位低功耗数位类比转换器
| 型号： | DAC1221 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16-Bit Low Power DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总14页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC1221
DAC1221
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit Low Power
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● 16-BIT MONOTONICITY GUARANTEED
● PROCESS CONTROL
OVER –40°C TO +85°C
● ATE PIN ELECTRONICS
● CLOSED-LOOP SERVO-CONTROL
● SMART TRANSMITTERS
● PORTABLE INSTRUMENTS
● VCO CONTROL
● LOW POWER: 1.2mW
● VOLTAGE OUTPUT
● SETTLING TIME: 2ms to 0.012%
● MAX LINEARITY ERROR: 30ppm
● ON-CHIP CALIBRATION
The DAC1221 features a synchronous serial interface.
In single converter applications, the serial interface can
be accomplished with just two wires, allowing low-
cost isolation. For multiple converters, a CS signal
allows for selection of the appropriate D/A converter.
DESCRIPTION
The DAC1221 is a Digital-to-Analog (D/A) converter
offering 16-bit monotonic performance over the speci-
fied temperature range. It utilizes delta-sigma technol-
ogy to achieve inherently linear performance in a
small package at very low power. The output range is
two times the external reference voltage. On-chip
calibration circuitry dramatically reduces offset and
gain errors.
The DAC1221 has been designed for closed-loop
control applications in the industrial process control
market, and high resolution applications in the test and
measurement market. It is also ideal for remote appli-
cations, battery-powered instruments, and isolated sys-
tems. The DAC1221 is available in a SSOP-16 package.
XIN
XOUT
VREF
C1 C2A C2B C3
Clock Generator
Microcontroller
Second-Order
∆∑
Modulator
First-Order
Switched
Capacitor Filter
Second-Order
Continuous
Time Post Filter
Instruction Register
Command Register
Data Register
VOUT
Offset Register
Full-Scale Register
Modulator Control
Serial
Interface
SDIO
SCLK
CS
DVDD
DGND
AVDD
AGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1519B
Printed in U.S.A. May, 2000
SPECIFICATIONS
All specifications TMIN to TMAX, AVDD = DVDD = +3V, fXIN = 2.5MHz, VREF = +1.25V, C1 = 2.2nF, C2 = 150pF, C3 = 6.8nF, unless otherwise noted.
DAC1221E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Monotonicity
Linearity Error(1)
Offset Error(2)
Offset Error Drift(3)
Midscale Error(2)
Midscale Error Drift(3)
Gain Error(2)
16
Bits
ppm of FSR
µV
µV/°C
µV
±30
±190
VOUT = 20mV, CALPIN = 1(6)
VOUT = VREF, CALPIN = 1(6)
CALPIN = 1(6)
50
±20
50
µV/°C
%
0.015
Gain Error Drift(3)
Power-Supply Rejection Ratio
3
57
ppm/°C
dB
at DC, dB = –20log(∆VOUT/∆VDD
)
ANALOG OUTPUT
Output Voltage(4)
Output Current(1)
0
2 • VREF
±0.25
500
V
mA
pF
Capacitive Load
Short-Circuit Current
Short-Circuit Duration
±10
Indefinite
mA
GND or VDD
DYNAMIC PERFORMANCE
Settling Time(1,5)
Output-Noise Voltage
To ±0.012%
1Hz to 2kHz
1.8
45
2
ms
µVrms
REFERENCE INPUT
Input Voltage
Input Impedance
1.125
1.25
1
1.375
V
MΩ
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels (all except XIN
VIH
VIL
VOH
VOL
Input-Leakage Current
XIN Frequency Range (fXIN
Data Format
TTL-Compatible CMOS
DVDD + 0.3
)
2.0
–0.3
2.4
V
V
V
V
µA
MHz
0.8
IOH = –0.8mA
IOL = 1.6mA
0.4
±10
2.5
)
1.0
User Programmable
Offset Two’s Complement
or Straight Binary
POWER SUPPLY REQUIREMENTS
Power-Supply Voltage
Supply Current
2.7
3.3
V
Analog Current
Digital Current
320
70
µA
µA
Power Dissipation
Normal Mode
Sleep Mode
1.2
0.25
1.6
mW
mW
TEMPERATURE RANGE
Specified Performance
–40
+85
°C
NOTES: (1) Valid from AGND + 20mV to 2 • VREF. (2) Applies after calibration. (3) Recalibration can remove these errors. (4) Ideal output voltage. (5) Using external
low-pass filter with 2kHz corner frequency. (6) See Command Register for description of CALPIN.
®
2
DAC1221
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
Top View
SSOP
1
2
DVDD
XOUT
XIN
Digital Supply, +3V nominal
Digital, System Clock Output
Digital, System Clock Input
Digital Ground
3
DVDD
XOUT
XIN
1
2
3
4
5
6
7
8
16 SCLK
15 SDIO
14 CS
4
DGND
AVDD
DNC
C3
5
Analog Supply, +3V nominal
Do Not Connect
6
7
Analog, Filter Capacitor
Analog, Filter Capacitor
Analog, Filter Capacitor
Analog, Filter Capacitor
Analog Output Voltage
Analog, Reference Input
Analog Ground
DGND
AVDD
DNC
C3
13 AGND
12 VREF
11 VOUT
10 C2A
8
C2B
DAC1221E
9
C1
10
11
12
13
14
15
16
C2A
VOUT
VREF
AGND
CS
C2B
9
C1
Digital, Chip Select Input
Digital, Serial Data Input/Output
Digital, Clock Input for Serial Data Transfer
SDIO
SCLK
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
AVDD to DVDD ................................................................................... ±0.3V
AVDD to AGND ........................................................................ –0.3V to 4V
DVDD to DGND ....................................................................... –0.3V to 4V
AGND to DGND ............................................................................... ±0.3V
VREF Voltage to AGND .......................................................... 1.0V to 1.5V
Digital Input Voltage to DGND .............................. –0.3V to DVDD + 0.3V
Digital Output Voltage to DGND ........................... –0.3V to DVDD + 0.3V
Package Power Dissipation............................................. (TJMAX – TA)/θJA
Maximum Junction Temperature (TJMAX) ..................................... +150°C
Thermal Resistance, θJA
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
bemoresusceptibletodamagebecauseverysmallparametric
changes could cause the device not to meet its published
specifications.
SSOP-16 ............................................................................... 200°C/W
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PACKAGE
SPECIFIED
DRAWING
NUMBER
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DAC1221E
"
SSOP-16
"
322
"
–40°C to +85°C
DAC1221E
"
DAC1221E
DAC1221E/2K5
Rails
Tape and Reel
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “DAC1221E/2K5” will get a single 2500-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC1221
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DVDD = +3.0V, fXIN = 2.5MHz, VREF = 1.25V, C1 = 2.2nF, C2 = 150pF and C3 = 6.8nF.
FULL SCALE OUTPUT SWING
POWER SUPPLY REJECTION RATIO vs FREQUENCY
70
60
50
40
30
20
10
0
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
10
100
1000
10000
100000
Time (ms)
Frequency (Hz)
SETTLING TIME: 20mV to FS
SETTLING TIME: FS to 20mV
300
0
1500
1200
900
600
300
0
–300
–600
–900
–1200
–1500
–300
0
2
4
6
8
10
0
2
4
6
8
10
Time (ms)
Time (ms)
OFFSET vs TEMPERATURE
OUTPUT NOISE VOLTAGE vs FREQUENCY
4
2
10000
1000
100
10
0
(can be corrected with calibration)
–2
–4
–6
1
–50
–25
0
25
50
75
100
10
100
1000
10000
10000
Temperature (°C)
Frequency (Hz)
®
4
DAC1221
TYPICAL PERFORMANCE CURVES
At TA = +25°C, AVDD = DVDD = +3.0V, fXIN = 2.5MHz, VREF = 1.25V, C1 = 2.2nF, C2 = 150pF and C3 = 6.8nF.
GAIN ERROR vs TEMPERATURE
LINEARITY ERROR vs CODE
0.020
0.015
25
20
15
10
5
(can be corrected with calibration)
0.010
0.005
0.000
–0.005
–0.010
–0.015
0
–5
–50
–25
0
25
50
75
100
0
0.2
0.4
0.6
0.8
1
Temperature (°C)
16-Bit Input Code Normalized
®
5
DAC1221
THEORY OF OPERATION
ANALOG OPERATION
The DAC1221 is a precision, high dynamic range, self-
calibrating, 16-bit, delta-sigma digital-to-analog converter.
It contains a second-order delta-sigma modulator, a first-
order switched-capacitor filter, a second-order continuous-
time post filter, a microcontroller including the Instruction,
Command and Calibration registers, a serial interface, and a
clock generator circuit.
The system clock is divided down to provide the sample
clock for the modulator. The sample clock is used by the
modulator to convert the multi-bit digital input into a 1-bit
digital output stream. The use of a 1-bit DAC provides
inherent linearity. The digital output stream is then con-
verted into an analog signal via the 1-bit DAC and then
filtered by the 1st-order switched-capacitor filter.
The design topology provides low system noise and good
power-supply rejection. The modulator frequency of the
delta-sigma D/A converter is controlled by the system clock.
The output of the switched-capacitor filter feeds into the
continuous time filter. The continuous time filter uses exter-
nal capacitors, C1 and C2, to adjust the settling time. The
connections for capacitors are shown in Figure 1. C1 con-
nects to VREF. C2 connects between the C2 pins. C3 is
connected between C3 and VREF, and is used for calibration.
The DAC1221 also includes complete onboard calibration
that can correct for internal offset and gain errors.
The calibration registers are fully readable and writable.
This feature allows for system calibration. The various
settings, modes, and registers of the DAC1221 are read or
written via a synchronous serial interface. This interface
operates as an externally clocked interface.
DEFINITION OF TERMS
DAC1221
Differential Nonlinearity Error—The differential
nonlinearity error is the difference between an actual step
width and the ideal value of 1 LSB. If the step width is
exactly 1 LSB, the differential nonlinearity error is zero.
A differential nonlinearity specification of less than 1 LSB
guarantees monotonicity.
VREF
12
11
C1
2.2nF
C2A
C1
7
8
10
9
C3
C2B
C3
6.8nF
Drift—The drift is the change in a parameter over tempera-
ture.
Full-Scale Range (FSR)—This is the magnitude of the
C2
150pF
typical analog output voltage range which is 2 • VREF
.
For example, when the converter is configured with a 1.25V
reference, the full-scale range is 2.5V.
NOTE: C1 and C2 should be NPO type capacitors.
Gain Error—This error represents the difference in the
slope between the actual and ideal transfer functions.
Linearity Error—The linearity error is the deviation of the
actual transfer function from an ideal straight line between
the data end points.
FIGURE 1. Capacitor Connections.
Least Significant Bit (LSB) Weight—This is the ideal
change in voltage that the analog output will change with a
change in the digital input code of 1 LSB.
CALIBRATION
The DAC1221 offers a self-calibration mode which auto-
matically calibrates the output offset and gain. The calibra-
tion is performed once and then normal operation is re-
sumed. In general, calibration is recommended immediately
after power-on and whenever there is a “significant” change
in the operating environment. The amount of change which
should cause re-calibration is dependent on the application.
Where high accuracy is important, re-calibration should be
done on changes in temperature and power supply.
Monotonicity—Monotonicity assures that the analog output
will increase or stay the same for increasing digital input
codes.
Offset Error—The offset error is the difference between the
expected and actual output, when the output is zero. The
value is calculated from measurements made when
VOUT = 20mV.
Settling Time—The settling time is the time it takes the
output to settle to its new value after the digital code has
been changed.
After a calibration has been accomplished, the Offset Cali-
bration Register (OCR) and the Full-Scale Calibration Reg-
ister (FCR) contain the results of the calibration.
f
XIN—The frequency of the crystal oscillator or CMOS-
Note that the values in the calibration registers will vary
from configuration to configuration and from part to part.
compatible input signal at the XIN input of the DAC1221.
®
6
DAC1221
Self Calibration
REFERENCE INPUT
A self-calibration is performed after the bits “01” have been
written to the Command Register Operation Mode bits
(MD1 and MD0). This initiates a self-calibration on the next
clock cycle. The offset correction code is determined by a
repeated sequence of auto-zeroing the calibration compara-
tor to the offset reference and then comparing the DAC
output to the offset reference value. The end result is the
averaged, Offset Two’s Complement adjusted, and placed in
the OCR. The gain correction is done in a similar fashion,
except the correction is done against VREF to eliminate
common-mode errors. The FCR result represents the gain
code and is not Offset Two’s Complement adjusted.
The reference input voltage of 1.25V can be directly con-
nected to VREF pin.
The recommended reference circuit for the DAC1221 is
shown in Figure 2.
DIGITAL OPERATION
SYSTEM CONFIGURATION
The DAC1221 is controlled by 8-bit instruction codes (INSR)
and 16-bit command codes (CMR) via the serial interface,
which is externally clocked.
The calibration function takes between 300ms and 500ms
(for fXIN = 2.5MHz) to complete. Once calibration is initi-
ated, further writing of register bits is disabled until calibra-
tion completes. The status of calibration can be verified by
reading the status of the Command Register Operation Mode
bits (MD1 and MD0). These bits will return to normal mode
“00” when calibration is complete.
The DAC1221 Microcontroller (MC) consists of an ALU
and a register bank. The MC has three states: power-on
reset, calibration, and normal operation. In the power-on
reset state, the MC resets all the registers to their default
states. In the calibration state, the MC performs offset and
gain self-calibration. In the normal state, the MC performs
D/A conversions.
It is recommended that the output be connected during
calibration. The output isolation is controlled by the CALPIN
bit in the CMR register. Setting the CALPIN bit will connect
the output and clearing the bit will disconnect and isolate the
output. Although it is recommended to connect the output
during calibration, the load impedance should be such that
the DAC1221 is not required to sink any current, but is able
to source up to the specified maximum.
The DAC1221 has five internal registers, as shown in Table I.
Two of these, the Instruction Register (INSR) and the
Command Register (CMR), control the operation of the
converter. The Instruction Register utilizes an 8-bit instruc-
tion code to control the serial interface to determine whether
the next operation is either a read or a write, to control the
word length, and to select the appropriate register to
read/write. Communication with the DAC1221 is controlled
via the INSR. Under normal operation, the INSR is written
as the first part of each serial communication. The instruc-
tion that is sent determines what type of communication will
occur next. It is not possible to read the INSR. The Com-
mand Register has a 16-bit command code to set up the
Output Mode
The output of the DAC1221 can be synchronously reset.
By setting the CLR bit in the CMR, the data input register
is cleared to zero. This will result in an output of 0V when
DF = 1, or VREF when DF = 0.
The settling time is determined by the DISF and ADPT bits
of the command register. The default state of DISF = 0 and
ADPT = 0 enables fast settling, unless the output step is
small (≈ 40mV). However, the DAC1221 can be forced to
always use fast settling if the ADPT bit is set to 1. If DISF
is set to 1, all fast settling is disabled.
INSR
DIR
Instruction Register
Data Input Register
8 Bits
16 Bits
16 Bits
24 Bits
24 Bits
CMR
OCR
FCR
Command Register
Offset Calibration Register
Full-Scale Calibration Register
The CRST bit of the CMR can be used to reset the offset and
calibration registers. By setting the CRST bit, the contents of
the calibration registers are reset to 0.
TABLE I. DAC1221 Registers.
+3V
+3V
0.10µF
7
87.6kΩ
20kΩ
2
3
100Ω
6
To VREF Pin
OPA336
1
+
10µF
0.1µF
+
10µF
0.10µF
4
REF1004-1.2
FIGURE 2. Recommended External Voltage Reference Circuit for Best Low Noise Operation with the DAC1221.
®
7
DAC1221
DAC1221 operation mode, settling mode and data format.
The Data Input Register (DIR) contains the value for the
next conversion. The Offset and Full-Scale Calibration Reg-
isters (OCR and FCR) contain data used for correcting the
internal conversion value after it is placed into the DIR. The
data in these two registers may be the result of a calibration
routine, or they may be values which have been written
directly via the serial interface.
or the write operation for the CMR register. If the next
location is reserved in Table III, the results are unknown.
Reading or writing continues until the number of bytes
specified by MB1 and MB0 have been transferred.
A3
A2
A1
A0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Input Register Byte 1 MSB
Data Input Register Byte 0 LSB
Reserved
INSTRUCTION REGISTER (INSR)
Reserved
Command Register Byte 1 MSB
Command Register Byte 0 LSB
Reserved
Each serial communication starts with the 8 bits of INSR
being sent to the DAC1221. The read/write bit, the number
of bytes (n), and the starting register address are defined in
Table II. When the n bytes have been transferred, the
instruction is complete. A new communication cycle is
initiated by sending a new INSR (under restrictions outlined
in the Interfacing section).
Reserved
Offset Cal Register Byte 2 MSB
Offset Cal Register Byte 1
Offset Cal Register Byte 0 LSB
Reserved
Full-Scale Cal Register Byte 2 MSB
Full-Scale Cal Register Byte 1
Full-Scale Cal Register Byte 0 LSB
Reserved
MSB
LSB
R/W
MB1
MB0
0
A3
A3
A1
A0
NOTE: INSR is a write-only register with the MSB (Most Significant Byte and
Bit) written first, independent of the BD bit.
TABLE III. A3 - A0 Addressing.
TABLE II. Instruction Register.
COMMAND REGISTER (CMR)
The CMR controls all of the functionality of the DAC1221.
The new configuration is latched in on the negative transi-
tion of SCLK for the last bit of the last byte of data being
written to the command register. The organization of the
CMR is comprised of 16 bits of information in 2 bytes of 8
bits each.
R/W (Read/Write) Bit—For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
shown:
R/W
0
1
Write
Read
MSB
Byte 1
0
ADPT CALPIN
1
1
0
CRST
MD1
0
Byte 0
DISF
LSB
MD0
MB1, MB0 (Multiple Bytes) Bits—These two bits are used
to control the word length (number of bytes) of the read or
write operation, as shown:
0
CLR
DF
BD
MSB
TABLE IV. Command Register.
ADPT (Adaptive Filter Disable) Bit—The ADPT bit de-
termines if the adaptive filter is enabled or disabled. When
the Adaptive Filter is enabled, the DAC1221 does fast
settling only when there is an output step of larger than
≈ 40mV. For small changes in the data, fast settling is not
necessary. When ADPT = 1, the Adaptive Filter is disabled
and the DAC1221 will not look at the size of a step to
determine the necessity of using fast settling. In either case,
fast settling can be defeated if DISF = 1.
MB1
MB0
0
0
1
0
1
0
1 Byte
2 Bytes
3 Bytes
A3 – A0 (Address) Bits—These four bits select the begin-
ning register location that will be read from or written to, as
shown in Table III. Each subsequent byte will be read from
or written to the next higher location (increment address). If
the BD bit in the Command register is set, each subsequent
byte will be read from or written to the next lower location
(decrement address). This bit does not affect INSR register
ADPT
0
1
Enabled (default)
Disabled
®
8
DAC1221
CALPIN (Calibration Pin) Bit—The CALPIN bit deter-
mines if the output is isolated or connected during calibration.
Care must be observed in reading the Command Register if
the state of the BD bit is unknown. If a two byte read is
started at address 0100 with BD = 0, it will read 0100, then
0101. However, if BD = 1, it will read 0100, then 0011. If
the BD bit is unknown, all reads of the command register are
best performed as read commands of one byte.
CALPIN
0
1
Output Isolated (default)
Output Connected
MSB (Bit Order) Bit—The MSB bit controls the order in
which bits within a byte of data are read or written (either
most significant bit first or least significant bit first), as
follows:
CRST (Calibration Reset) Bit—The CRST bit resets the
offset and full-scale calibration registers, as shown:
MSB
CRST
0
1
MSB First (default)
LSB First
0
1
OFF (default)
Reset
MD1 – MD0 (Operating Mode) Bits—The Operating
Mode bits control the calibration functions of the DAC1221.
The Normal Mode is used to perform conversions. The Self-
Calibration Mode is a one-step calibration sequence that
calibrates both the offset and full scale.
CLR (Clear) Bit—The CLR bit synchronously resets the
data input register to zero. The analog output will be based
on the DF bit—if 1, the output will be 0V; if 0, the output
will be VREF
.
DF (Data Format) Bit—The DF bit controls the format of
the input data, shown in hexadecimal (either Offset Two’s
Complement or Straight Binary), as shown:
MD1
MD0
0
0
1
1
0
1
0
1
Normal Mode
Self-Cal
Sleep (default)
Reserved
Input Code
Offset Two's
Complement
Straight
Binary
VOUT
DF = 0
DF = 1
Offset Calibration Register (OCR)
(default)
The OCR is a 24-bit register containing the offset correction
factor that is used to apply a correction to the digital input
before it is transferred to the modulator. The results of the
self-calibration process will be written to this register.
8000
0000
7FFF
0000
8000
FFFF
0
VREF
2 • VREF
The OCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate calibration,
a calibration can be performed, the results averaged, and a
more precise offset calibration value written back to the
OCR.
DISF (Disable Fast Settling) Bit—The DISF bit disables
the fast settling option. If this bit is zero the fast settling
performance is determined by the ADPT bit.
DISF
The actual OCR value will change from part to part and with
configuration, temperature, and power supply.
0
1
Fast Settling (default)
Disable Fast Settling
In addition, be aware that the contents of the OCR are not
used to directly correct the digital input. Rather, the correc-
tion is a function of the OCR value. This function is linear
and two known points can be used as a basis for interpolat-
ing intermediate values for the OCR.
BD (Byte Order) Bit—The BD bit controls the order in
which bytes of data are transferred (either most significant
byte first (MSBF) or least significant byte first (LSBF)), as
shown:
The results of calibration are averaged, Offset Two's Comple-
ment adjusted, and placed in the OCR.
BD bit:
register
INSR
0 (default)
1
0 (default)
1
MSB
Byte 2
read
write
OCR23 OCR22 OCR21 OCR20 OCR19 OCR18 OCR17 OCR16
write only
write only
MSBF
MSBF
Byte 1
CMR
DIR
MSBF
MSBF
MSBF
MSBF
LSBF
LSBF
LSBF
LSBF
MSBF
MSBF
MSBF
MSBF
MSBF
LSBF
LSBF
LSBF
OCR15 OCR14 OCR13 OCR12 OCR11 OCR10 OCR9
OCR8
LSB
Byte 0
OCR
FCR
OCR7
OCR6
OCR5
OCR4
OCR3
OCR2
OCR1
OCR0
TABLE V. Offset Calibration Register.
®
9
DAC1221
Full-Scale Calibration Register (FCR)
The FCR is a 24-bit register which contains the full-scale
correction factor that is applied to the digital input before it
is transferred to the modulator. The contents of this register
will be the result of a self-calibration, or written to by the
user.
SLEEP MODE
The Sleep Mode is entered after the bit combination 10 has
been written to the CMR Operation Mode bits (MD1 and
MD0). This mode ends when these bits are changed to a
value other than 10.
Communication with the DAC1221 can continue during
Sleep Mode. When a new mode (other than Sleep) has been
entered, the DAC1221 will execute a very brief internal
power-up sequence of the analog and digital circuitry. In
addition, the settling of the external VREF and other circuitry
must be taken into account to determine the amount of time
required to resume normal operation.
The FCR is both readable and writable via the serial inter-
face. For applications requiring a more accurate calibration,
a calibration can be performed, the results averaged, and a
more precise value written back to the FCR.
The actual FCR value will change from part to part and with
configuration, temperature, and power supply.
Once serial communication is resumed, the Sleep Mode is
exited by changing the MD1 - MD0 bits to any other mode.
When a new mode (other than Sleep) has been entered, the
DAC1221 will execute a very brief internal power-up se-
quence of the analog and digital circuitry. In addition, the
settling of the external VREF and other circuitry must be
taken into account to determine the amount of time required
to resume normal operation.
In addition, be aware that the contents of the FCR are not
used to directly correct the digital input. Rather, the correc-
tion is a function of the FCR value. This function is linear
and two known points can be used as a basis of interpolating
intermediate values for the FCR. The contents of the FCR
are in unsigned binary format. This is not affected by the DF
bit in the Command Register.
MSB
Byte 2
SERIAL INTERFACE
FCR23 FCR22 FCR21 FCR20 FCR19 FCR18 FCR17 FCR16
Byte 1
The DAC1221 includes a flexible serial interface which can
be connected to microcontrollers and digital signal proces-
sors in a variety of ways. Along with this flexibility, there is
also a good deal of complexity. This section describes the
trade-offs between the different types of interfacing methods
in a top-down approach—starting with the overall flow and
control of serial data, moving to specific interface examples,
and then providing information on various issues related to
the serial interface.
FCR15 FCR14 FCR13 FCR12 FCR11 FCR10 FCR9
FCR8
LSB
Byte 0
FCR7
FCR6
FCR5
FCR4
FCR3
FCR2
FCR1
FCR0
TABLE VI. Full-Scale Calibration Register.
Data Input Register (DIR)
The DIR is a 16-bit register which contains the digital input
value (see Table VII). The register is latched on the falling
edge of the last bit of the last byte sent. The contents of the
DIR are then loaded into the modulator. This means that the
DIR register can be updated after sending 1 or 2 bytes, which
is determined by the MB1 and MB0 bits in the Instruction
Register. The contents of the DIR can be Offset Two’s
Complement or Straight Binary.
Reset, Power-On Reset and Brown-Out
The DAC1221 contains an internal power-on reset circuit. If
the power supply ramp rate is greater than 50mV/ms, this
circuit will be adequate to ensure the device powers up
correctly. Due to oscillator settling considerations, commu-
nication to and from the DAC1221 should not occur for at
least 25ms after power is stable.
If this requirement cannot be met or if the circuit has brown-
out considerations, the timing diagram of Figure 3 can be
used to reset the DAC1221. This accomplishes the reset by
controlling the duty cycle of the SCLK input.
MSB
Byte 1
DIR14 DIR13 DIR12
Byte 0
DIR15
DIR11 DIR10
DIR9
DIR1
DIR8
LSB
DIR0
DIR7
DIR6
DIR5
DIR4
DIR3
DIR2
Sleep mode is the default state after power on or reset. The
output is high impedance during sleep mode.
TABLE VII. Data Input Register.
®
10
DAC1221
I/O Recovery
condition. They only become active when serial data is
being transmitted from the DAC1221. If the DAC1221 is in
the middle of a serial transfer and the SDIO is an output,
taking CS HIGH will not tri-state the output signal.
If serial communication stops during an instruction or data
transfer for longer than 100ms (for fXIN = 2.5MHz), the
DAC1221 will reset its serial interface. This will not affect
the internal registers. The main controller must not continue
the transfer after this event, but must restart the transfer from
the beginning. This feature is very useful if the main control-
ler can be reset at any point. After reset, simply wait 200ms
(for fXIN = 2.5MHz) before starting serial communication.
If there are multiple serial peripherals utilizing the same
serial I/O lines and communication may occur with any
peripheral at any time, the CS signal must be used. The CS
signal is then used to enable communication with the
DAC1221.
Isolation
The serial interface of the DAC1221 provides for simple
isolation methods. An example of an isolated two-wire
interface is shown in Figure 4.
TIMING
The maximum serial clock frequency cannot exceed the
DAC1221 XIN frequency divided by 10. Table VIII and
Figures 5 through 9 define the basic digital timing character-
istics of the DAC1221. Figure 5 and the associated timing
symbols apply to the XIN input signal. Figures 6 through 9
and associated timing symbols apply to the serial interface
signals (SCLK, SDIO, and CS). The serial interface is
discussed in detail in the Serial Interface section.
Using CS
The serial interface may make use of the CS signal, or this
input may simply be tied LOW. There are several issues
associated with choosing to do one or the other. The CS
signal does not directly control the tri-state condition of the
SDIO output. These signals are normally in the tri-state
t1: > 512 • tXIN
< 800 • tXIN
Reset On
Falling Edge
t2: > 10 • tXIN
t2
t2
t3: > 1024 • tXIN
< 1800 • tXIN
SCLK
t4: ≥ 2048 • tXIN
t1
t3
t4
< 2400 • tXIN
FIGURE 3. Resetting the DAC1221.
Isolated
Power
DVDD
Opto
Coupler
8051
P1.1
P1.0
DAC1221
C1X
5.6pF
1
DVDD
SCLK 16
SDIO 15
CS 14
Opto
Coupler
2
XOUT
XIN
XTAL
3
C2X
5.6pF
4
DGND
AVDD
DNC
C3
AGND 13
VREF 12
VOUT 11
C2A 10
AVDD
VREF
5
6
7
8
= Isolated
= DGND
= AGND
C1
C3
C2B
C1
9
C2
FIGURE 4. Isolation for Two-Wire Interface.
®
11
DAC1221
SYMBOL
DESCRIPTION
MIN
NOM
MAX
2.5
UNITS
fXIN
tXIN
t1
XIN Clock Frequency
XIN Clock Period
1
400
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
XIN Clock High
0.4 • tXIN
0.4 • tXIN
5 • tXIN
5 • tXIN
40
t2
XIN Clock LOW
t3
SCLK HIGH
t4
SCLK LOW
t5
Data In Valid to SCLK Falling Edge (Setup)
SCLK Falling Edge to Data In Not Valid (Hold)
Data Out Valid After Rising Edge of SCLK (Hold)
SCLK Rising Edge to New Data Out Valid (Delay)(1)
t6
20
t7
0
t8
50
t9
Falling Edge of Last SCLK for INSR to Rising Edge of First
SCLK for Register Data
13 • tXIN
ns
ns
t10
t11
t12
t13
t14
Falling Edge of CS to Rising Edge of SCLK
Falling Edge of Last SCLK for INSR to SDIO as Output
SDIO as Output to Rising Edge of First SCLK for Register Data
Falling Edge of Last SCLK for Register Data to SDIO Tri-State
11 • tXIN
8 • tXIN
ns
ns
ns
ns
ns
10 • tXIN
6 • tXIN
4 • tXIN
4 • tXIN
Falling Edge of Last SCLK for Register Data to Rising Edge
of First SCLK of next INSR (CS Tied LOW)
41 • tXIN
t15
Rising Edge of CS to Falling Edge of CS (Using CS)
22 • tXIN
ns
NOTE: (1) With 10pF load.
TABLE VIII. Digital Timing Characteristics.
t3
t4
t5
tXIN
SCLK
SDIO
t1
t2
t6
t7
XIN
t8
FIGURE 5. XIN Clock Timing.
FIGURE 6. Serial Input/Output Timing.
t9
t14
SCLK
SDIO
SDIO
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
IN7
Write Register Data
IN0
OUTM
OUT1 OUT0
Read Register Data
FIGURE 7. Serial Interface Timing (CS always LOW).
t15
CS
t10
t10
t9
SCLK
SDIO
IN7
IN7
IN1
IN1
IN0
INM
IN1
IN0
IN7
Write Register Data
IN0
OUTM
OUT1 OUT0
IN7
SDIO
Read Register Data
FIGURE 8. Serial Interface Timing (using CS).
®
12
DAC1221
CS
t11
t12
t10
SCLK
SDIO
t13
IN7
IN0
OUT MSB
OUT0
t9
SDIO is an input
SDIO is an output
FIGURE 9. SDIO Input to Output Transition Timing.
From Read
flowchart
To Write
flowchart
Start
Start
Writing
Reading
CS taken HIGH
for t15 periods
minimum
CS taken HIGH
for t15 periods
minimum
(or CS tied LOW)
(or CS tied LOW)
CS
CS
state
state
HIGH
HIGH
LOW
CS
state
LOW
External device
generates 8 serial
clock cycles and
transmits instruction
register data
CS
state
HIGH
HIGH
External device
generates 8
serial clock cycles
and transmits
instruction register
data via SDIO
LOW
LOW
via SDIO
External device
generates n
serial clock cycles
and transmits
specified
SDIO input to
output transition
register data
via SDIO
External device
generates n serial
clock cycles and
receives specified
register data via SDIO
Yes
No
Is next
instruction
a read?
More
instructions?
SDIO transitions to
tri-state condition
Yes
No
End
To Read
flowchart
Yes
No
Is next
instruction
a Write?
More
instructions?
Yes
No
End
To Write
flowchart
FIGURE 10. Flowchart for Writing and Reading Register Data.
13
®
DAC1221
GROUNDING
LAYOUT
The analog and digital sections of the design should be
carefully and cleanly partitioned. Each section should have
its own ground plane with no overlap between them. AGND
should be connected to the analog ground plane, as well as
all other analog grounds. DGND should be connected to the
digital ground plane, and all digital signals referenced to this
plane.
POWER SUPPLIES
The DAC1221 requires the digital supply (DVDD) to be no
greater than the analog supply (AVDD) +0.3V. In the majority
of systems, this means that the analog supply must come up
first, followed by the digital supply and VREF. Failure to
observe this condition could cause permanent damage to the
DAC1221.
The DAC1221 pinout is such that the converter is cleanly
separated into an analog and digital portion. This should
allow simple layout of the analog and digital sections of the
design.
Inputs to the DAC1221, such as SDIO or VREF, should not
be present before the analog and digital supplies are on.
Violating this condition could cause latch-up. If these sig-
nals are present before the supplies are on, series resistors
should be used to limit the input current.
For a single converter system, AGND and DGND of the
DAC1221 should be connected together, underneath the
converter. Do not join the ground planes. Instead, connect
the two with a moderate signal trace. For multiple convert-
ers, connect the two ground planes at one location, as central
to all of the converters as possible. In some cases, experi-
mentation may be required to find the best point to connect
the two planes together. The printed circuit board can be
designed to provide different analog/digital ground connec-
tions via short jumpers. The initial prototype can be used to
establish which connection works best.
The best scheme is to power the analog section of the design
and AVDD of the DAC1221 from one +3V supply, and the
digital section (and DVDD) from a separate +3V supply. The
analog supply should come up first. This will ensure that
SCLK, SDIO, CS and VREF do not exceed AVDD, that the
digital inputs are present only after AVDD has been estab-
lished, and that they do not exceed DVDD
.
The analog supply should be well regulated and low noise.
For designs requiring very high resolution from the DAC1221,
power supply rejection will be a concern. See the “PSRR vs
Frequency” curve in the Typical Performance Curves sec-
tion of this data sheet for more information.
DECOUPLING
Good decoupling practices should be used for the DAC1221
and for all components in the design. All decoupling capaci-
tors, and specifically the 0.1µF ceramic capacitors, should
be placed as close as possible to the pin being decoupled. A
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic
capacitor, should be used to decouple AVDD to AGND. At a
minimum, a 0.1µF ceramic capacitor should be used to
decouple DVDD to DGND, as well as for the digital supply
on each digital component.
The requirements for the digital supply are not as strict.
However, high frequency noise on DVDD can capacitively
couple into the analog portion of the DAC1221. This noise
can originate from switching power supplies, very fast
microprocessors, or digital signal processors.
If one supply must be used to power the DAC1221, the
AVDD supply should be used to power DVDD. This connec-
tion can be made via a 10Ω resistor which, along with the
decoupling capacitors, will provide some filtering between
DVDD and AVDD. In some systems, a direct connection can
be made. Experimentation may be the best way to determine
the appropriate connection between AVDD and DVDD
.
®
14
DAC1221
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