DAC715PK [BB]
16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface; 16位数字 - 模拟转换器，具有16位总线接口
| 型号： | DAC715PK |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 16-BIT DIGITAL-TO-ANALOG CONVERTER with 16-Bit Bus Interface |
| 文件： | 总11页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC715
DAC715
DAC715
16-BIT DIGITAL-TO-ANALOG CONVERTER
with 16-Bit Bus Interface
FEATURES
● HIGH-SPEED 16-BIT PARALLEL DOUBLE-
DESCRIPTION
The DAC715 is a complete monolithic digital-to-
analog converter including a +10V temperature com-
pensated reference, current-to-voltage amplifier, 16-bit
parallel interface that is double buffered, and an asyn-
chronous clear function which immediately sets the
output voltage to one-half of full-scale.
BUFFERED INTERFACE
● VOLTAGE OUTPUT: 0 to +10V
● 13-, 14-, 15-BIT LINEARITY GRADES
● 16-BIT MONOTONIC OVER
TEMPERATURE (L GRADE)
The output voltage range is 0 to +10V while operating
from ±12V or ±15V supplies. The gain and bipolar
offset adjustments are designed so that they can be set
via external potentiometers or external D/A converters.
The output amplifier is protected against short circuit to
ground.
● POWER DISSIPATION: 600mW max
● GAIN AND OFFSET ADJUST: Convenient
for Auto-Cal D/A Converters
● 28-LEAD DIP AND SOIC PACKAGES
The 28-pin DAC715 is available in a 0.3" plastic DIP
and wide-body plastic SOIC package. The DAC715P,
U, PB, and UB are specified over the –40°C to +85°C
temperature range while the DAC715PK, UK, PL, and
UL are specified over the 0°C to +70°C range.
D0
D15
A1
A0
Input Latch
16
WR
CLR
D/A Latch
16
Reference
Circuit
16-Bit D/A Converter
VOUT
VREF OUT
+10V
Offset Adjust
Gain Adjust
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1995 Burr-Brown Corporation
PDS-1306D
Printed in U.S.A. July, 1997
SPECIFICATIONS
ELECTRICAL
At TA = +25°C, VCC = ±15V, and after a 10-minute warm-up, unless otherwise noted.
DAC715P, U
TYP
DAC715PB, UB
TYP
DAC715PK, UK
TYP
DAC715PL, UL
TYP
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
INPUT
RESOLUTION
16
✻
✻
✻
Bits
DIGITAL INPUTS
Input Code
Binary Two’s Complement
+2.0 +VCC – 1.4
✻
✻
✻
Logic Levels(1): VIH
VIL
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
µA
0
+0.8
±10
±10
IIH (VI = +2.7V)
IIL (VI = +0.4V)
µA
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error
TMIN to TMAX
Differential Linearity Error
TMIN to TMAX
±4
±8
±4
±8
±2
±4
±2
±4
±2
±2
±2
±2
±2
±2
±1
±1
LSB
LSB
LSB
LSB
Monotonicity Over Temp
Gain Error(3)
13
14
15
16
Bits
%
%
±0.1
±0.2
±0.1
±0.2
±0.003
±0.1
±0.15
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
TMIN to TMAX
Offset Error(3)
% FSR(2)
% FSR
% FSR/%VCC
PPM FSR/%VCC
TMIN to TMAX
Power Supply Sensitivity Of Full Scale
±30
✻
DYNAMIC PERFORMANCE
Settling Time (to ±0.003%FSR,
5kΩ ll 500pF Load)(4)
10V Output Step
6
4
10
10
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
µs
µs
V/µs
1 LSB Output Step(5)
Output Slew Rate
Total Harmonic Distortion + Noise
0dB, 1001Hz, fS = 100kHz
–20dB, 1001Hz, fS = 100kHz
–60dB, 1001Hz, fS = 100kHz
SINAD
0.005
0.03
3.0
✻
✻
✻
✻
✻
✻
✻
✻
✻
%
%
%
1001Hz, fS = 100kHz
87
2
15
✻
✻
✻
✻
✻
✻
✻
✻
✻
dB
nV-s
nV-s
Digital Feedthrough(5)
Digital-to-Analog Glitch Impulse(5)
Output Noise Voltage
(includes Reference)
120
✻
✻
✻
nV√Hz
ANALOG OUTPUT
Output Voltage Range
+VCC, –VCC = ±11.4V
Output Current
Output Impedance
Short Circuit to ACOM
Duration
0 to +10
±5
✻
✻
✻
✻
✻
✻
V
mA
Ω
0.1
✻
✻
✻
✻
✻
✻
Indefinite
REFERENCE VOLTAGE
Voltage
TMIN to TMAX
Output Resistance
Source Current
Short Circuit to ACOM, Duration
+9.975
+9.960
+10.000
1
+10.025
+10.040
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
Ω
2
✻
✻
✻
mA
Indefinite
POWER SUPPLY REQUIREMENTS
Voltage: +VCC
–VCC
+11.4
–16.5
+15
–15
+16.5
–11.4
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
Current (no load, ±15V Supplies)
+VCC
–VCC
Power Dissipation
13
22
525
15
25
600
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
mA
mA
mW
TEMPERATURE RANGE
Specification All Grades
–40
–60
+85
+150
✻
✻
✻
✻
0
✻
+70
✻
✻
✻
✻
✻
°C
°C
Storage
Thermal Resistance θJA
DIP Package
SOIC Package
75
75
✻
✻
✻
✻
✻
✻
°C/W
°C/W
✻
Specifications are the same as grade to the left.
NOTES: (1) Digital inputs are TTL and +5V CMOS compatible over the specification temperature range. (2) FSR means Full Scale Range. For example, for
a
0 to +10V output, FSR = 10V.
(3) Errors externally adjustable to zero. (4) Maximum represents greater than the 3σ limit. Not 100% tested for this parameter. (5) For the worst case code changes: FFFFH to 0000H and 0000H to
FFFFH. These are Binary Two’s Complement (BTC) codes. (6) Typical supply voltages times maximum currents.
®
2
DAC715
ABSOLUTE MAXIMUM RATINGS(1)
TIMING DIAGRAM
+VCC to COMMON ...................................................................... 0V, +17V
–VCC to COMMON ...................................................................... 0V, –17V
+VCC to –VCC ........................................................................................................................... 34V
Digital Inputs to COMMON .....................................................–1V to +VCC
External Voltage Applied to BPO and Range Resistors..................... ±VCC
VREF OUT ...................................................... Indefinite Short to COMMON
VOUT ............................................................ Indefinite Short to COMMON
Power Dissipation .......................................................................... 750mW
Storage Temperature ...................................................... –60°C to +150°C
Lead Temperature (soldering, 10s)................................................ +300°C
tAW
tAH
A0, A1
tDW
D0-D15
WR
tDH
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
tWP
PACKAGE INFORMATION
TIMING SPECIFICATIONS
PACKAGE DRAWING
TA = –40°C to +85°C, +VCC = +12V or +15V, –VCC = –12V or –15V.
PRODUCT
PACKAGE
NUMBER(1)
SYMBOL
PARAMETER
MIN
MAX UNITS
DAC715P
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
246
217
246
217
246
217
246
217
DAC715U
DAC715PB
DAC715UB
DAC715PK
DAC715UK
DAC715PL
DAC715UL
tDW
tAW
tAH
tDH
Data Valid to End of WR
A0, A1 Valid to End of WR
A0, A1 Hold after End of WR
Data Hold after end of WR
Write Pulse Width
50
50
10
10
50
ns
ns
ns
ns
ns
ns
(1)
tWP
tCP
CLEAR Pulse Width
200
NOTES: (1) For single-buffered operation, tWP is 80ns min. Refer to page 10.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
TRUTH TABLE
A0
A1
WR
CLR
DESCRIPTION
ORDERING INFORMATION
0
1
1
0
X
X
1
0
1
0
X
X
1 → 0 → 1
1 → 0 → 1
1 → 0 → 1
1
1
1
1
1
0
Load Input Latch
Load D/A Latch
No Change
Latches Transparent
No Change
DIFFERENTIAL
LINEARITY
ERROR MAX
0
1
X
TEMPERATURE
RANGE
PRODUCT
PACKAGE
at +25°C
Reset D/A Latch
DAC715P
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
Plastic DIP
Plastic SOIC
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
±4LSB
±4LSB
±2LSB
±2LSB
±2LSB
±2LSB
±1LSB
±1LSB
DAC715U
DAC715PB
DAC715UB
DAC715PK
DAC715UK
DAC715PL
DAC715UL
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formancedegradationtocompletedevicefailure.Burr-Brown
Corporationrecommendsthatallintegratedcircuitsbehandled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC715
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN
LABEL
DESCRIPTION
1
2
3
4
5
6
7
8
9
DCOM
ACOM
VOUT
Offset Adjust
VREF OUT
Gain Adjust
+VCC
Digital Ground
Analog Ground
0 to +10V D/A Output
Offset Adjust
Voltage Reference Output
Gain Adjust
+12V to +15V Supply
–12V to –15V Supply
CLEAR. Sets D/A output to Half Scale
(Active Low)
Write (Active Low)
Enable for D/A latch (Active Low)
Enable for Input latch (Active Low)
Data Bit 15 (Most Significant Bit)
Data Bit 14
Data Bit 13
Data Bit 12
Data Bit 11
Data Bit 10
Data Bit 9
Data Bit 8
Data Bit 7
Data Bit 6
DCOM
ACOM
1
2
3
4
5
6
7
8
9
28 D0 (LSB)
27 D1
26 D2
25 D3
24 D4
23 D5
22 D6
21 D7
20 D8
19 D9
18 D10
17 D11
16 D12
15 D13
VOUT
–VCC
CLR
Offset Adjust
VREF OUT
Gain Adjust
+VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
WR
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DAC715
–VCC
CLR
WR 10
A1 11
A0 12
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (Least Significant Bit)
D15 (MSB) 13
D14 14
D0
®
4
DAC715
TYPICAL PERFORMANCE CURVES
At TA = +25°C, and VCC = ±15V, unless otherwise noted.
POWER SUPPLY REJECTION vs
POWER SUPPLY RIPPLE FREQUENCY
1k
LOGIC vs V LEVEL
2.0
–VCC
100
10
1
1.0
WR, A0, A1
CLR
+VCC
0
DATA
–1.0
–2.0
0.1
10
100
1k
10k
100k
1M
–0.85
0
0.85 1.7 2.55 3.4 4.25 5.1 5.95 6.8
V Digital Input
Frequency (Hz)
FULL-SCALE OUTPUT SWING
SETTLING TIME, +10V TO 0V
2500
2000
1500
1000
500
+5V
0V
0
–500
–1000
–1500
–2000
–2500
Time (10µs/div)
Time (1µs/div)
Spectral Noise Density
SETTLING TIME, 0V TO +10V
1000
2500
2000
1500
1000
500
+5V
0V
100
10
1
0
–500
–1000
–1500
–2000
–2500
1
10
100
1k
10k
100k
1M
10M
Time (1µs/div)
Frequency (Hz)
®
5
DAC715
DIGITAL FEEDTHROUGH
DISCUSSION OF
SPECIFICATIONS
LINEARITY ERROR
When the D/A is not selected, high frequency logic activity
on the digital inputs is coupled through the device and shows
up as output noise. This noise is digital feedthrough.
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points of
the transfer characteristic.
OPERATION
The DAC715 is a monolithic integrated-circuit 16-bit D/A
converter complete with 16-bit D/A switches and ladder
network, voltage reference, output amplifier and micropro-
cessor bus interface.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from
1LSB of an output change from one adjacent state to the
next. A DLE specification of ±1/2LSB means that the output
step size can range from 1/2LSB to 3/2LSB when the digital
input code changes from one code word to the adjacent code
word. If the DLE is more positive than –1LSB, the D/A is
said to be monotonic.
INTERFACE LOGIC
The DAC715 has double-buffered data latches. The input
data latch holds a 16-bit data word before loading it into the
second latch, the D/A latch. This double-buffered organiza-
tion permits simultaneous update of several D/A converters.
All digital control inputs are active low. Refer to the block
diagram shown in Figure 1.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values.
Monotonicity of DAC715 is guaranteed over the specifica-
tion temperature range to 13-, 14-, 15-, and 16-bits for
performance grades DAC715P/U, DAC715PB/UB,
DAC715PK/UK, and DAC715PL/UL respectively.
All latches are level-triggered. Data present when the enable
inputs are logic “0” will enter the latch. When the enable
inputs return to logic “1”, the data is latched.
The CLR input resets both the input latch and the D/A latch
to give a half scale output.
LOGIC INPUT COMPATIBILITY
SETTLING TIME
The DAC715 digital inputs are TTL compatible (1.4V switch-
ing level), low leakage, and high impedance. Thus the inputs
are suitable for being driven by any type of 5V logic family,
such as CMOS logic. An equivalent circuit for the digital
inputs is shown in Figure 2.
Settling time is the total time (including slew time) for the
D/A output to settle to within an error band around its final
value after a change in input. Settling times are specified to
within ±0.003% of Full Scale Range (FSR) for an output
step change of 10V and 1LSB. The 1LSB change is mea-
sured at the Major Carry (FFFFH to 0000H, and 0000H to
FFFFH: BTC codes), the input transition at which worst-case
settling time occurs.
The inputs will float to logic “0” if left unconnected. It is
recommended that any unused inputs be connected to DCOM
to improve noise immunity.
Digital inputs remain high impedance when power is off.
TOTAL HARMONIC DISTORTION
Total harmonic distortion is defined as the ratio of the square
root of the sum of the squares of the values of the harmonics
to the value of the fundamental frequency. It is expressed in
% of the fundamental frequency amplitude at sampling rate
fS.
INPUT CODING
The DAC715 is designed to accept binary two’s comple-
ment (BTC) input codes. For unipolar analog output con-
figuration, a digital input of 7FFFH gives a full scale output,
8000H gives a zero output, and 0000H gives half scale output.
SIGNAL-TO-NOISE
AND DISTORTION RATIO (SINAD)
INTERNAL REFERENCE
SINAD includes all the harmonic and outstanding spurious
components in the definition of output noise power in
addition to quantizing and internal random noise power.
SINAD is expressed in dB at a specified input frequency and
sampling rate, fS.
The DAC715 contains a +10V reference. The reference
output may be used to drive external loads, sourcing up to
2mA. The load current should be constant, otherwise the
gain of the converter will vary.
OUTPUT VOLTAGE SWING
DIGITAL-TO-ANALOG GLITCH IMPULSE
The output amplifier of the DAC715 is committed to a 0 to
+10V output range. It will provide a 0 to +10V output swing
while operating on ±11.4V or higher voltage supplies.
The amount of charge injected into the analog output from
the digital inputs when the inputs change state. It is mea-
sured at half scale at the input codes where as many as
possible switches change state—from FFFFH to 0000H.
®
6
DAC715
VREF OUT
5
+VCC
7
– VCC
8
Gain Adjust
6
170Ω
15kΩ
+10V
Reference
Offset
Adjust
4
3
10kΩ
5kΩ
+2.5V
–VCC
D/A Switches
CLR
9
VOUT
16-Bit D/A Latch
16-Bit Input Latch
A1 11
A0 12
WR 10
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
2
1
DCOM
D0
D15
ACOM
LSB
MSB
FIGURE 1. DAC715 Block Diagram.
Range of
Gain Adjust
≈ ±0.3%
+ Full Scale
+VCC
ESD Protection Circuit
R = 1kΩ: A0, A1, WR, CLR
3kΩ: D0...D15
Full Scale
Range
Gain Adjust
Rotates the Line
R
Digital
Input
6.8V
5pF
–VCC
Range of
Offset Adjust
Zero
Offset Adj.
Translates
the Line
≈ ±0.3%
8000H
0000H
Digital Input
7FFFH
FIGURE 2. Equivalent Circuit of Digital Inputs.
FIGURE 3. Relationship of Offset and Gain Adjustments.
GAIN AND OFFSET ADJUSTMENTS
Figure 3 illustrates the relationship of offset and gain adjust-
ments for a unipolar connected D/A converter. Offset should
be adjusted first to avoid interaction of adjustments. See
Table I for calibration values and codes. These adjustments
have a minimum range of ±0.3%.
Offset Adjustment
Apply the digital input code that produces zero output
voltage and adjust the offset potentiometer or the offset
adjust D/A converter for 0V.
®
7
DAC715
DAC715 CALIBRATION VALUES
1 LEAST SIGNIFICANT BIT = 152µV
1
2
DCOM
ACOM
VOUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DIGITAL INPUT CODE
BINARY TWO’S
COMPLEMENT, BTC
ANALOG
OUTPUT
(V)
DESCRIPTION
3
7FFFH
|
4000H
|
0001H
9.999847
Full Scale –1LSB
4
7.5
3/4 Scale
Half Scale + 1LSB
Half Scale
5
VREF OUT
5.000152
6
+12V to +15V
–12V to –15V
0000H
5
4.999847
2.5
7
+VCC
–VCC
FFFFH
|
C000H
|
8000H
Half Scale – 1LSB
1/4 Scale
8
+
0.01µF
9
10
11
12
13
14
0.01µF
0
Zero
+
TABLE I. Digital Input and Analog Output Voltage Calibra-
tion Values.
Gain Adjustment
Apply the digital input that gives the maximum positive
voltage output. Adjust the gain potentiometer or the gain
adjust D/A converter for this positive full scale voltage.
FIGURE 4. Power Supply Connections.
well as at +VCC. The capacitors should be located close to the
package.
INSTALLATION
GENERAL CONSIDERATIONS
The DAC715 has separate ANALOG COMMON and DIGI-
TAL COMMON pins. The current through DCOM is mostly
switching transients and are up to 1mA peak in amplitude.
The current through ACOM is typically 5µA for all codes.
Due to the high-accuracy of the DAC715, system design
problems such as grounding and contact resistance become
very important. A 16-bit converter with a 10V full-scale
range has a 1LSB value of 152µV. With a load current of
5mA, series wiring and connector resistance of only 60mΩ
will cause a voltage drop of 300µV. To understand what this
means in terms of a system layout, the resistivity of a typical
1 ounce copper-clad printed circuit board is 1/2 mΩ per
square. For a 5mA load, a 10 milliinch wide printed circuit
conductor 60 milliinches long will result in a voltage drop of
150µV.
Use separate analog and digital ground planes with a single
interconnection point to minimize ground loops. The analog
pins are located adjacent to each other to help isolate analog
from digital signals. Analog signals should be routed as far
as possible from digital signals and should cross them at
right angles. A solid analog ground plane around the D/A
package, as well as under it in the vicinity of the analog and
power supply pins, will isolate the D/A from switching
currents. It is recommended that DCOM and ACOM be
connected directly to the ground planes under the package.
The analog output of DAC715 has an LSB size of 152µV
(–96dB). The noise floor of the D/A must remain below this
level in the frequency range of interest. The DAC715’s noise
spectral density (which includes the noise contributed by the
internal reference) is shown in the Typical Performance
Curves section.
If several DAC715s are used or if DAC715 shares supplies
with other components, connecting the ACOM and DCOM
lines together once at the power supplies rather than at each
chip may give better results.
Wiring to high-resolution D/A converters should be routed
to provide optimum isolation from sources of RFI and EMI.
The key to elimination of RF radiation or pickup is small
loop area. Signal leads and their return conductors should be
kept close together such that they present a small capture
cross-section for any external field. Wire-wrap construction
is not recommended.
LOAD CONNECTIONS
Since the reference point for VOUT and VREF OUT is the ACOM
pin, it is important to connect the D/A converter load
directly to the ACOM pin. Refer to Figure 5.
Lead and contact resistances are represented by R1 through
R3. As long as the load resistance RL is constant, R1 simply
introduces a gain error and can be removed by gain adjust-
ment of the D/A or system-wide gain calibration. R2 is part
of RL if the output voltage is sensed at ACOM.
POWER SUPPLY AND
REFERENCE CONNECTIONS
In some applications it is impractical to return the load to the
ACOM pin of the D/A converter. Sensing the output voltage
at the SYSTEM GROUND point is reasonable, because
there is no change in DAC715 ACOM current, provided that
Power supply decoupling capacitors should be added as
shown in Figure 4. Best performance occurs using a 1 to
10µF tantalum capacitor at –VCC. Applications with less
critical settling time may be able to use 0.01µF at –VCC as
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DAC715
R3 is a low-resistance ground plane or conductor. In this case
you may wish to connect DCOM to SYSTEM GROUND as
well.
converters outputs are at approximately half scale, 0V.
DIGITAL INTERFACE
BUS INTERFACE
GAIN AND OFFSET ADJUST
Connections Using Potentiometers
The DAC715 has a 16-bit double-buffered data interface
with control lines for easy connection to a 16-bit bus. The
double-buffered feature permits update of several D/As
simultaneously.
GAIN and OFFSET adjust pins provide for trim using
external potentiometers. 15-turn potentiometers provide suf-
ficient resolution. Range of adjustment of these trims is at
least ±0.3% of Full Scale Range. Refer to Figure 6.
A0 is the enable control for the DATA INPUT LATCH. A1
is the enable for the D/A LATCH. WR is used to strobe data
into latches enabled by A0, and A1. Refer to the block
diagram of Figure 1 and to Timing Diagram on page 3.
Using D/A Converters
The GAIN ADJUST and OFFSET ADJUST circuits of
the DAC715 have been arranged so that these points may
be easily driven by external D/A converters. Refer to
Figure 7. 12-bit D/A converters provide an OFFSET adjust
resolution and a GAIN adjust resolution of 30µV to 50µV
per LSB step.
CLR sets the INPUT DATA LATCH and D/A LATCH to
0000H (5V at the D/A output).
SINGLE-BUFFERED OPERATION
Nominal values of GAIN and OFFSET occur when the D/A
DAC715
10kΩ
5kΩ
VREF
R1
VOUT
Bus
Interface
Sense
Output
RL
DCOM
ACOM
R2
Alternate Ground
Sense Connection
R3
To +VCC
0.01µF(1)
0.01µF
Analog
Power
Supply
System Ground
To –VCC
NOTE: (1) Locate close to DAC715 package.
FIGURE 5. System Ground Considerations for High-Resolution D/A Converters.
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9
DAC715
To operate the DAC715 interface as a single-buffered latch,
the DATA INPUT LATCH is permanently enabled by
connecting A0 to DCOM. If A1 is not used to enable the
D/A, it should be connected to DCOM also. For this mode
of operation, the width of WR will need to be at least 80ns
minimum to pass data through the DATA INPUT LATCH
and into the D/A LATCH.
The digital interface of the DAC715 can be made transpar-
ent by asserting AO, A1, and WR LOW, and asserting CLR
HIGH.
TRANSPARENT INTERFACE
Internal
+10V Reference
VREF OUT
5
P1
1kΩ
170Ω
R1
100Ω
Gain Adjust
+VCC
6
4
R2
2MΩ
Offset Adjust
P2
15kΩ
10kΩ – 100kΩ
10kΩ
–VCC
5kΩ
R3
27kΩ
≈ +2.5V
3
+10V VOUT
IDAC
0-2mA
For no external adjustments, pins 4 and 6 are not connected.
External resistors R1 - R4 are standard ±1% values. Range of
adjustment at least ±0.03% FSR.
2
ACOM
FIGURE 6. Manual Offset and Gain Adjust Circuits.
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DAC715
Internal
+10V Reference
VREF OUT
R1
392Ω
170Ω
Gain Adjust
R2
33kΩ
10kΩ
5kΩ
Offset Adjust
15kΩ
–10 to 10V
DAC
R3
1MΩ
–10 to 10V
DAC
0 to 2mA
VOUT
R1 - R3 tolerance: ±1%, Range of
adjustment at least ±0.3% FSR.
DAC715
FIGURE 7. Gain and Offset Adjustment Using D/A Converters.
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DAC715
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