DAC7528U [BB]
CMOS Dual 8-Bit Buffered Multiplying DIGITAL-TO-ANALOG CONVERTER; CMOS双8位缓冲乘法数位类比转换器
| 型号： | DAC7528U |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | CMOS Dual 8-Bit Buffered Multiplying DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总8页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DAC7528
CMOS Dual 8-Bit Buffered Multiplying
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● DOUBLE BUFFERED DATA LATCHES
● SINGLE 5V SUPPLY OPERATION
● ±1/2 LSB LINEARITY
The DAC7528 contains two, 8-bit multiplying digital-
to-analog converters (DACs). Separate on-chip latches
hold the input data for each DAC to allow easy
interface to microprocessors.
● FOUR-QUADRANT MULTIPLICATION
● DACs MATCHED TO 1%
Each DAC operates independently with separate refer-
ence input pins and internal feedback resistors. Excel-
lent converter-to-converter matching is maintained.
The DAC7528 operates from a single +5V power
supply. The inputs are TTL-compatible. Package
options include 20-pin plastic DIP and SOIC.
APPLICATIONS
● DIGITALLY CONTROLLED FILTERS
● DISK DRIVES
● AUTO CALIBRATION
● MOTOR CONTROL SYSTEMS
● PROGRAMMABLE GAIN/ATTENUATION
● X-Y GRAPHICS
VREF A
4
VDD
RFB
A
17
14
3
2
Data
Inputs
DB0 (LSB)
OUT A
Input
Buffer
Latch
DAC A
DB7 (MSB)
7
AGND
1
DAC7528
DAC A/
DAC B
19 RFB B
6
CS 15
WR 16
Control
Logic
OUT B
20
DAC B
Latch
DGND
5
18
VREF B
International Airport Industrial Park
•
Mailing Address: PO Box 11400
•
Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd.
• Tucson, AZ 85706
Tel: (520) 746-1111
•
Twx: 910-952-1111
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1993 Burr-Brown Corporation
PDS-1219A
Printed in U.S.A. June, 1994
SPECIFICATIONS
ELECTRICAL
At VDD = +5V; VREFA, B = + 10V; IOUT = GND = 0V: T = Full Temperature Range specification under Absolute Maximum Ratings unless otherwise noted.
DAC7528P, U
DAC7528PB, UB
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DC ACCURACY (1)
Resolution
Relative Accuracy
Differential Nonlinearity
FS Gain Error (2)
N
INL
DNL
8
8
Bits
LSB
LSB
LSB
LSB
ppm/°C
%FSR/%
%FSR/%
nA
nA
nA
±1
±1
±2
±1/2
±1/2
±1
±2
–
–
–
–
–
Guaranteed Monolithic Over Temp
TA = +25°C
T
A = TMIN to TMAX
±4
Gain Tempco (2)(3)
Supply Rejection
±2
0.001
0.001
±35
0.01
0.01
±50
±200
±50
±200
–
–
–
PSR
∆VDD = ±5%, TA = +25°C
A = TMIN to TMAX
DACA = 0016, TA = +25°C
A = TMIN to TMAX
DACB = 0016, TA = +25°C
A = TMIN to TMAX
T
Output Leakage Current (OUTA)
Output Leakage Current (OUTB)
T
–
–
T
nA
REFERENCE INPUT
Input Resistance
Input Resistance Match
(VREFA, VREFB
)
8
10
15
±1
–
–
–
–
–
kΩ
%
(VREFA, VREFB
)
DYNAMIC PERFORMANCE (4)
Output Current Settling Time to 1/2 LSB
Enable Pins Low TA = +25°C
Load = 100Ω/13pF, TA = TMIN to TMAX
Enable Pins Low TA= +25°C
180
200
80
–
–
–
–
ns
ns
ns
Digital-to-Analog Propagation Delay
to 90% of Output
Digital-to-Analog Impulse
AC Feedthrough
(VREFA to OUTA)
AC Feedthrough
(VREFB to OUTB)
Channel-to-Channel Isolation
(VREFA to OUTB)
Channel-to-Channel Isolation
(VREFB to OUTA)
Load = 100Ω/13pF, TA
=
TMIN to TMAX
100
ns
125
nVs
dB
dB
dB
dB
dB
V
REFA = 20Vpp Sinewave, TA = +25°C
100kHz,VREFB = 0V, TA = TMIN to TMAX
REFA = 20Vpp Sinewave, TA = +25°C
100kHz, VREFB = 0V, TA = TMIN to TMAX
REFA = 20Vpp Sinewave, 100kHz,
VREFB = 0V, Both DACs = FF16
VREFB = 20Vpp Sinewave 100kHz,
VREFA = 0V, Both DACs = FF16
–70
–65
–70
–65
V
V
–90
–90
–
–
dB
Digital Crosstalk
Harmonic Distortion
Measured With Code Transition 0016 to FF16
VIN = 6Vrms at 1kHz
30
–85
–
–
nVs
dB
THD
ANALOG OUTPUTS (4)
OUTA capacitance
COUTA
COUTB
DAC = 0016
DAC = FF16
DAC = 0016
DAC = FF16
50
120
50
–
–
–
–
pF
pF
pF
pF
OUTB capacitance
120
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
IIN
2.4
–
V
V
µA
µA
pF
0.8
±1
±10
10
–
–
–
–
TA = +25°C
A = TMIN to TMAX
All Digital Inputs
T
Input Capacitance (4)
CIN
POWER REQUIREMENTS
Supply Current
IDD
Digital Inputs = VIH or VIL, TA = +25°C
1
1
100
500
–
–
–
–
mA
mA
µA
µA
T
A = TMIN to TMAX
Digital Inputs = 0V or VDD, TA = +25°C
A = TMIN to TMAX
T
SWITCHING CHARACTERISTICS (100% tested) See Timing Diagram
Chip Select To Write Setup Time
Chip Select To Write Hold Time
DAC Select To Write Setup Time
DAC Select To Write Hold Time
Write Pulse Width
tCS
tCH
tAS
tAH
tWR
tDS
tDH
TA = +25°C
A = TMIN to TMAX
TA = +25°C
A = TMIN to TMAX
TA = +25°C
A = TMIN to TMAX
TA = +25°C
A = TMIN to TMAX
TA = +25°C
A = TMIN to TMAX
TA = +25°C
A = TMIN to TMAX
TA = +25°C
200
230
20
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
T
T
T
T
T
30
200
230
20
30
180
200
110
130
0
Data Setup Time
Data Hold Time
NOTES: (1) Specifications apply to both DACs. (2) Gain error is measured using internal feedback resistor. Full Scale Range (FSR) = VREF. (3) Guaranteed, but
not tested. (4) These characteristics are for design guidance only and are not subject to test.
®
2
DAC7528
DICE INFORMATION
8
7
6
5
4
3
PAD FUNCTION PAD FUNCTION PAD FUNCTION
1
2
3
4
5
6
7
VDD
8
9
RFB A
15
16
17
18
19
20
21
DB4
DB3
DB2
DB1
DB0
CS
VREF B
RFB B
VREF B
DGND
10
9
2
OUTB
AGNDB
AGNDA
OUTA
11 DAC A/DAC B
12
13
14
DB7
DB6
DB5
WR
10
1
21
20
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
11
12
Die Size
Die Thickness
Min. Pad Size
104 x 124
20 ±3
4 x 4
2.6 x 3.1
0.51 ±0.08
0.10 x 0.10
19
13
14
15
16
17
18
DAC7528 TOPOGRAPHY
ELECTRICAL, (DICE)
At VDD = +5V; VREFA, B = +10V; IOUT = GND = 0V: T = Full Temperature Range specification under Absolute Maximum Ratings unless otherwise noted.
DAC7528AD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (1)
Resolution
Relative Accuracy
Differential Nonlinearity
FS Gain Error (2)
N
INL
DNL
8
Bits
LSB
LSB
±1
±1
±2
Guaranteed Monolithic Over Temp
TA = +25°C
LSB
T
A = TMIN to TMAX
±4
LSB
Gain Tempco (2, 3)
Supply Rejection
±2
0.001
0.001
±35
0.01
0.01
±50
±200
±50
±200
ppm/°C
%FSR/%
%FSR/%
nA
nA
nA
PSR
∆VDD = ±5%, TA = +25°C
A = TMIN to TMAX
DACA = 0016 TA = +25°C
A = TMIN to TMAX
DACB = 0016 TA = +25°C
A = TMIN to TMAX
T
Output Leakage Current (OUTA)
Output Leakage Current (OUTB)
T
T
nA
REFERENCE INPUT
Input Resistance
Input Resistance Match
(VREF A, VREF B
(VREF A, VREF B
)
)
8
10
15
±1
kΩ
%
NOTES: (1) Specifications apply to both DACs. (2) Gain error is measured using internal feedback resistor. Full Scale Range (FSR) = VREF. (3) Guaranteed, but not
tested. (4) These characteristics are for design guidance only and are not subject to test.
PACKAGE INFORMATION
PIN CONFIGURATION
PACKAGE DRAWING
NUMBER(1)
Top View
DIP/SOIC
MODEL
PACKAGE
20
19
18
17
16
15
14
13
12
11
1
2
AGND
OUT A
OUT B
RFB B
VREF B
VDD
DAC7528P
DAC7528PB
DAC7528U
DAC7528UB
20-Pin Plastic DIP
20-Pin Plastic DIP
20-Pin SOIC
222
222
221
221
3
RFB A
20-Pin SOIC
4
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
VREF A
5
DGND
WR
DAC7528
6
DAC A/DAC B
(MSB) DB7
DB6
CS
ORDERING INFORMATION
7
DB0 (LSB)
DB1
MODEL
INL
PACKAGE
TEMPERATURE RANGE
8
DAC7528P
±1LSB
20-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
9
DAC7528PB ±1/2LSB 20-Pin Plastic DIP
DAC7528U
DAC7528UB ±1/2LSB
DB5
DB2
±1LSB
20-Pin SOIC
20-Pin SOIC
10
DB4
DB3
®
3
DAC7528
ABSOLUTE MAXIMUM RATINGS
WRITE CYCLE TIMING DIAGRAM
VDD to GND ................................................................................. 0V, +7V
tCS
tCH
CS
VDD
0
VREFA, B to GND ................................................................................ ±25V
R
FA,B to GND ................................................................................... ±25V
Digital Input Voltage Range ................................................ –0.3V to VDD
Output Voltage (pins 2, 20) ................................................ –0.3V to VDD
Operating Temperature Range U,P ................................–40°C to +85°C
DICE ............................... 0°C to +70°C
Junction Temperature .................................................................. +150°C
Storage Temperature..................................................... –60°C to +150°C
Lead Temperature (soldering, 10s) ............................................. +300°C
θJA U package ........................................................................ 105°C/W
P package........................................................................... 85°C/W
θJC U package ......................................................................... 60°C/W
P package.......................................................................... 35°C/W
tAS
tAH
DAC A/DAC B
VDD
0
tWR
WR
VDD
0
tDS
tDH
VDD
0
Data In
(DB0-DB7)
VIH
VIL
Data
In Stable
NOTES: θJA is specified for worst case mounting conditions, i.e., θJA is
specified for device in socket for PDIP package.
NOTE: All input signal rise and fall times are measured from 10% to 90%
of VDD. VDD = +5V, tr = tf = 20ns; VDD = +15V, tr = tf = 40ns. Timing
measurement reference level is (VIH + VIL)/2.
CAUTION: (1) Do not apply voltages higher than VDD or less than GND
potential on any terminal except VREFA, B (pins 4 and 18) and RFBA, B (pins
3 and 19). (2) The digital control inputs are zener-protected: however,
permanent damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam at all times until ready
to use. (3) Use proper antistatic handling procedures. (4) Absolute
Maximum Ratings apply to both packaged devices and DICE. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device.
MODE SELECTION TABLE
DAC A/DAC B
CS
WR
DAC A
DAC B
L
L
L
H
X
L
L
X
H
WRITE
HOLD
HOLD
HOLD
HOLD
WRITE
HOLD
HOLD
H
X
X
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Digital Inputs: All digital inputs of the DAC7528 incorpo-
rate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500Ω)
applied to each digital input.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
Analog Pins: Each analog pin has been tested to Burr-
Brown's analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500Ω) ap-
plied to each pin. RFB A, VREF A, RFB B, and VREF B show
some sensitivity.
TYPICAL PERFORMANCE CURVES
At VDD = +5V; VREFA,B = +10V; IOUT = GND = 0V: T = Full Temperature Range Specification under Absolute Maximum Ratings unless otherwise noted.
SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE
DAC7528 GAIN TC
5
4
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
3
2
1
0
–1
–2
–3
–4
–5
VDD = +5V
0
1.0
2.0
3.0
4.0
–40
–20
0
20
40
60
80
100
VIN (V)
Temperature (°C)
®
4
DAC7528
CIRCUIT DESCRIPTION
DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full scale errors have been
adjusted to zero.
Figure 1 shows a simplified schematic of one half of a
DAC7528. The current from the VREF pin is switched
A
between IOUT A and AGND by 8 single-pole double-throw
CMOS switches. This maintains a constant current in each
leg of the ladder regardless of the input code. The input
resistance at VREF A is therefore constant and can be driven
by either a voltage or current, AC or DC, positive or
negative polarity, and have a voltage range up to ±20V.
DIFFERENTIAL NONLINEARITY
VREF A
R
R
R
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
guarantees monotonicity.
RFB A
R
2R
2R
2R
2R
2R
IOUT A
GAIN ERROR
AGND
Gain error is the difference between the full-scale DAC
output and the ideal value. The ideal full scale output value
for the DAC7528 is –(255/256)VREF. Gain error may be
adjusted to zero using external trims as shown in Figure 4.
DB7
(MSB)
DB6
DB5
DB0
(LSB)
FIGURE 1. Equivalent Circuit for DAC A.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
RFB A, compensates for the temperature drift of the ON
resistance of the ladder switches.
OUTPUT LEAKAGE CURRENT
The current which appears at IOUT A and IOUT B with the
DAC loaded with all zeros.
Figure 2 shows an equivalent circuit for DAC A. COUT is the
output capacitance due to the N-channel switches and varies
from about 30pF to 70pF with digital input code. The current
source ILKG is the combination of surface and junction
leakages to the substrate. ILKG approximately doubles every
10°C. RO is the equivalent output resistance of the D/A and
it varies with input code.
OUTPUT CAPACITANCE
The parasitic capacitance measured from IOUT A or IOUT B to
AGND.
CHANNEL-TO-CHANNEL ISOLATION
The AC output error due to capacitive coupling from DAC
A to DAC B or DAC B to DAC A.
R
RFB A
IOUT A
VREF A
AC FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from VREF
to IOUT with the DAC loaded with all zeros.
ILKG
DIN VREF
COUT
RO
x
R
256
R
AGND
OUTPUT CURRENT SETTLING TIME
FIGURE 2. Simplified Circuit Diagram for DAC A.
The time required for the output current to settle to within
±0.195% of final value for a full scale step.
INSTALLATION
DIGITAL-TO-ANALOG IMPULSE
ESD PROTECTION
The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to digital-to-analog glitch is
charge injected by digital logic switching transients.
All digital inputs of the DAC7528 incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500Ω).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
DIGITAL CROSSTALK
Glitch impulse measured at the output of one DAC but
caused by a full scale transition on the other DAC. The
integrated area of the glitch pulse is measured in nanovolt-
seconds.
®
5
DAC7528
POWER SUPPLY CONNECTIONS
VDDVREF A
+5V
DIN
VOUT = –
VREF
The DAC7528 is designed to operate on VDD = +5V +10%.
For optimum performance and noise rejection, power supply
decoupling capacitors CD should be added as shown in the
application circuits. These capacitors (1µF tantalum recom-
mended) should be located close to the D/A. AGND and
DGND should be connected together at one point only, pre-
ferably at the power supply ground point. Separate returns
minimize current flow in low-level signal paths if properly
connected. Output op amp analog common (+ input) should
be connected as near to the AGND pin of the DAC7528 as
possible.
256
+
CD
1µF
RFB A
C1
IOUT A
10pF
–
DAC A
A1
+
VOUT A
DAC7528
RFB B
IOUT B
C2
10pF
–
DAC B
A2
+
VOUT B
AGND
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling be-
tween the VREF lines and the IOUT lines. Similarly, capacitive
coupling between DACs may compromise the channel-to-
channel isolation. Coupling from any of the digital control or
data lines might degrade the glitch and digital crosstalk
performance. Solder the DAC7528 directly into the PC
board without a socket. Sockets add parasitic capacitance
(which can degrade AC performance).
A1, A2 OPA602 or 1/2 OPA2107.
DGND
VREF B
FIGURE 3. Unipolar Configuration 2 Quadrant Multiplica-
tion.
amplifier.
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 4 may be used. Resistors R2 and R4
induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R1 and R3 provide a
variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the
error produced by R2 and R4.
AMPLIFIER OFFSET VOLTAGE
The output amplifier used with the DAC7528 should have
low input offset voltage to preserve the transfer function
linearity. The voltage output of the amplifier has an error
component which is the offset voltage of the op amp multi-
plied by the “noise gain” of the circuit. This “noise gain” is
equal to (RF/RO + 1) where RO is the output impedance of
the D/A IOUT terminal and RF is the feedback network
impedance. The nonlinearity occurs due to the output im-
pedance varying with code. If the 0 code case is excluded
(where RO = infinity), the RO will vary from R to 3R
providing a “noise gain” variation between 4/3 and 2. In
addition, the variation of RO is nonlinear with code, and the
largest steps in RO occur at major code transitions where the
worst differential nonlinearity is also likely to be experi-
enced. The nonlinearity seen at the amplifier output is
2VOS – 4VOS/3 = 2VOS/3. Thus, to maintain good
nonlinearity the op amp offset should be much less than
1/2LSB.
BIPOLAR CONFIGURATION
Figure 5 shows the DAC7528 in a typical bipolar (four-
quadrant) multiplying configuration. The analog output val-
ues versus digital input code are listed in Table II.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602, a dual amplifier such as the
OPA2107, or a quad amplifier like the OPA404. C1 and C2
provide phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier.
The bipolar offset resistors R1–R3 and R4–R6 should be
ratio-matched to 0.195% to ensure the specified gain error
performance.
UNIPOLAR CONFIGURATION
Figure 3 shows DAC7528 in a typical unipolar (two-quad-
rant) multiplying configuration. The analog output values
versus digital input code are listed in Table I. The opera-
tional amplifiers used in this circuit can be single amplifiers
such as the OPA602, or a dual amplifier such as the OPA2107.
C1 and C2 provide phase compensation to minimize settling
time and overshoot when using a high speed operational
®
6
DAC7528
APPLICATION INFORMATION
VDD
+5V
VIN A
DATA INPUT
MSB
ANALOG OUTPUT
R1
100Ω
VREF A
LSB
1111 1111
1000 0000
0000 0001
0000 0000
–VREF (255/256)
–VREF (255/256) = –1/2VREF
–VREF (1/256)
+
CD
1µF
R2
RFB A
0V
C1 10pF
–
47Ω
TABLE I. Unipolar Output Code.
IOUT A
DAC A
A1
+
VOUT A
DATA INPUT
ANALOG OUTPUT
R4
DAC7528
RFB B
MSB
LSB
1111 1111
1000 0001
1000 0000
0111 1111
0000 0000
+VREF (127/128)
+VREF (1/128)
0V
–VREF (1/128)
–VREF (127/128)
C2 10pF
–
A2
+
47Ω
IOUT B
DAC B
AGND
VOUT B
TABLE II. Bipolar Output Code.
VREF B
A1, A2 OPA602 or 1/2 OPA2107.
R3
100Ω
DGND
VIN B
FIGURE 4.Unipolar Configuration with Gain Trim.
+5V
R1
VDD
20kΩ
VREF A
R2
20kΩ
–
+
CD
1µF
VOUT A
A2
R3
+
10kΩ
RFB A
IOUT A
C1
10pF
–
+
A1
DAC A
A1–A4, OPA602 or 1/2 OPA2107.
DAC7528
RFB B
IOUT B
AGND
C2
10pF
–
A3
+
DAC B
R4
20kΩ
R5
10kΩ
R6
20kΩ
–
DGND
VOUT B
A4
+
VREF B
FIGURE 5. Bipolar Configuration 4 Quadrant Multiplication.
®
7
DAC7528
APPLICATIONS CIRCUIT: 8-BIT PLUS SIGN DAC
+15V
2
+10V
The DACs are loaded with same 8-bit word,
except that one code is inverted first.
If sign bit = 1; invert DAC B’s data.
If sign bit = 0; invert DAC A’s data.
6
REF102
+5V
VDD
4
CD
1µF
VREF A
RFB A
C1
10pF
IOUT A
R
DAC A
A1
R
R
2
3
±10V
9 Bits
DAC7528
6
RFB B
C2
10pF
IOUT B
R
INA105
DAC B
A2
AGND
1
VREF B
A1 OPA602 or 1/2 OPA2107.
DGND
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no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
8
DAC7528
相关型号：
DAC7541AJPG4
PARALLEL, WORD INPUT LOADING, 0.6us SETTLING TIME, 12-BIT DAC, PDIP18, GREEN, PLASTIC, DIP-18
TI
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