DCP011512DP-U [BB]
DC-DC Unregulated Power Supply Module, 2 Output, 1W, Hybrid, PLASTIC, DIP-14;
| 型号： | DCP011512DP-U |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | DC-DC Unregulated Power Supply Module, 2 Output, 1W, Hybrid, PLASTIC, DIP-14 转换器 |
| 文件： | 总20页 (文件大小：451K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DCP01B SERIES
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
Miniature, 1W Isolated
UNREGULATED DC/DC CONVERTERS
FEATURES
DESCRIPTION
D
D
D
D
D
D
D
Up To 85% Efficiency
The DCP01B series is a family of 1W, unregulated,
isolated DC/DC converters. Requiring a minimum of
external components and including on-chip device
protection, the DCP01B series provides extra features
such as output disable and synchronization of switching
frequencies.
Thermal Protection
Device-to-Device Synchronization
Short-Circuit Protection
EN55022 Class B EMC Performance
UL1950 Recognized Component
JEDEC DIP-14 and SOP-14 Packages
The use of a highly-integrated package design results in
highly reliable products with a power density of 40W/in3
(2.4W/cm3). This combination of features and small sizes
makes the DCP01B suitable for a wide range of
applications.
APPLICATIONS
D
D
D
D
D
Point-of-Use Power Conversion
Ground Loop Elimination
Data Acquisition
Industrial Control and Instrumentation
Test Equipment
SYNCOUT
÷
2
800kHz
VOUT
Reset
Oscillator
Power
0V
Stage
Watch−dog/
start−up
SYNCIN
PSU
Thermal
Shutdown
IBIAS
VS
Power Controller IC
0V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2000−2004, Texas Instruments Incorporated
www.ti.com
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
SUPPLEMENTAL ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
DCP01B SERIES UNIT
DCP01 05 05 (D) (B) (
)
5V models
15V models
24V models
7
18
V
V
Basic Model Number: 1W Product
Voltage Input:
Input voltage
5V In
Voltage Output:
5V Out
29
V
Storage temperature
−40 to +125
+270
°C
°C
Dual Output:
Lead temperature (soldering, 10s)
Model Revision:
Package Code:
P = DIP−14
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
P−U = SOP−14 (Gullwing)
ORDERING INFORMATION(1)
SPECIFIED
PACKAGE
DESIGNATOR
PACKAGE
MARKING
TRANSPORT
MEDIA
TEMPERATURE
RANGE
(2)
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
(3)
SINGLE VOLTAGE
DIP-14
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
DCP010505BP
DCP010505BP−U
DCP010512BP
DCP010505BP
Rails
Tape and Reel
Rails
DCP010505
DCP010512
DCP010515
DCP012405
(4)
SOP-14
DCP010505BP−U/700
DCP010512BP
DIP-14
(4)
SOP-14
DCP010512BP−U
DCP010515BP
DCP010512BP−U/700
DCP010515BP
Tape and Reel
Rails
DIP-14
(4)
SOP-14
DCP010515BP−U
DCP012405BP
DCP010515BP−U/700
DCP012405BP
Tape and Reel
Rails
DIP-14
(4)
SOP-14
DCP012405BP−U
DCP012405BP−U/700
Tape and Reel
(3)
DUAL VOLTAGE
DIP-14
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
NVA
DUA
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
DCP010505DBP
DCP010505DBP−U
DCP010512DBP
DCP010512DBP−U
DCP010515DBP
DCP010515DBP−U
DCP011512DBP
DCP010505DBP
DCP010505DBP−U/700
DCP010512DBP
Rails
Tape and Reel
Rails
DCP010505
DCP010512
DCP010515
DCP011512
DCP011515
(4)
SOP-14
DIP-14
(4)
SOP-14
DCP010512DBP−U/700
DCP010515DBP
Tape and Reel
Rails
DIP-14
(4)
SOP-14
DCP010515DBP−U/700
DCP011512DBP
Tape and Reel
Rails
DIP-14
(4)
SOP-14
DCP011512DBP−U
DCP011515DBP
DCP011512DBP−U/700
DCP011515DBP
Tape and Reel
Rails
DIP-14
(4)
SOP-14
DCP011515DBP−U
DCP012415DBP
DCP012415DBP−U
DCP011515DBP−U/700
DCP012415DBP
Tape and Reel
Rails
DIP-14
DCP012415
(1)
(4)
SOP-14
DCP012415DBP−U/700
Tape and Reel
All devices also available in tray quatities. For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet,
or refer to our web site at www.ti.com.
Models with a (/) are available only in Tape and Reel in the quantities indicated (for example, /700 indicates 700 devices per reel). Ordering 700 pieces of
“DCP010505BP−U/700”will get a single 700-piece Tape and Reel.
Single voltage versions have six active pins; dual voltage versions have seven active pins.
SOP package is gullwing surface-mount.
(2)
(3)
(4)
2
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS
At T = +25°C, V = nominal, C = 2.2µF, and C
= 0.1µF, unless otherwise noted.
A
S
IN
OUT
DCP01B SERIES
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output
Power
Ripple
100% full load
0.97
20
W
O/P capacitor = 1µF, 50% load
Room to cold
mV
PP
0.046
0.016
%/°C
%/°C
Voltage vs Temperature
Room to hot
Input
Voltage range on V
−10
+10
%
S
Isolation
1s flash test
1
1
kVrms
kVrms
Voltage
(1)
60s test, UL1950
Line Regulation
%
change
of V
Minimum V ≤ I constant ≤ typical V
S
S
O
(2)
Voltage Source (V )
S
1
15
Typical V ≤ I constant ≤ maximum V
S
S
O
S
Switching/Synchronization
Oscillator frequency (f
Sync input low
)
Switcing frequency = f /2
OSC
800
kHz
V
OSC
0.4
Sync input current
Disable time
V
= +2V
75
2
µA
µs
pF
SYNC
Capacitance loading on SYNC pin
IN
External
3
Reliability
Demonstrated
MSL 3−(U) versions T = +55°C
−40
−40
+70
°C
A
Thermal Shutdown
IC temperature at shutdown
Shutdown current
Temperature Range
Operating
+150
3
°C
mA
+100
°C
(1)
During UL1950 recognition tests only.
Line regulation is measured at constant load current. Line regulation = (V
(2)
at I
OUT
fixed)/V . Variation % = V min to V typ, V typ to V max.
OUT
S
S
S
S
S
ELECTRICAL CHARACTERISTICS PER DEVICE
At T = +25°C, V = nominal, C = 2.2µF, and C
= 0.1µF, unless otherwise noted.
A
S
IN
OUT
NO LOAD
CURRENT
(mA)
BARRIER
CAPACITANCE
(pF)
INPUT VOLTAGE
(V)
OUTPUT VOLTAGE
(V)
LOAD REGULATION
(%)
EFFICIENCY
(%)
V
S
V
NOM
= V Typical
S
I
Q
C
ISO
(3)
(4)
75% LOAD
10% TO 100% LOAD
0% LOAD
100% LOAD
V
ISO
= 750V
TYP
3.6
RMS
PRODUCT
DCP010505B
DCP010505DB
DCP010512B
DCP010512DB
DCP010515B
DCP010515DB
DCP011512DB
DCP011515DB
DCP012405B
DCP012415DB
MIN
4.5
TYP
5
MAX
5.5
MIN
TYP
5
MAX
5.25
TYP
19
18
21
19
26
19
11
MAX
31
32
38
37
42
41
39
39
23
35
TYP
20
22
29
40
34
42
19
20
14
17
TYP
80
81
85
82
82
85
78
80
77
76
4.75
±4.25
11.4
4.5
5
5.5
±5
±5.75
12.6
3.8
4.5
5
5.5
12
5.1
4.5
5
5.5
±11.4
14.25
±12
15
±12.6
15.75
±15.75
±12.6
±15.75
5.25
4.0
4.5
5
5.5
3.8
4.5
5
5.5
±14.25
±11.4
±15
±12
±15
5
4.7
13.5
13.5
21.6
21.6
15
15
24
24
16.5
16.5
26.4
26.4
2.5
±14.25
4.75
12
13
10
2.5
2.5
±14.25
±15
±15.75
3.8
(3)
100% load current = 1W/V typical.
S
(4)
Load regulation = (V
at 10% load − V
at 100% load)/V
at 75% load.
OUT
OUT
OUT
3
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
PIN ASSIGNMENTS (Single Voltage Version)
PIN ASSIGNMENTS (Dual Voltage Version)
NVA and DUA
PACKAGES
(TOP VIEW)
NVA and DUA
PACKAGES
(TOP VIEW)
1
2
14
SYNCIN
VS
1
2
14
SYNCIN
VS
0V
0V
DCP01B
DCP01DB
5
6
7
0V
+VOUT
NC
0V
5
6
7
+VOUT
8
SYNCOUT
−
8
VOUT
SYNCOUT
Terminal Functions (Single Voltage)
Terminal Functions (Dual Voltage)
TERMINAL
TERMINAL
NAME
NO.
1
I/O
I
DESCRIPTION
Voltage input
NAME
NO.
1
I/O
I
DESCRIPTION
Voltage input
V
V
S
S
0V
0V
+V
2
I
Input side common
Output side common
+Voltage out
0V
0V
+V
−V
2
I
Input side common
Output side common
+Voltage out
5
O
O
5
O
O
O
O
I
6
6
OUT
OUT
OUT
NC
7
Not connected
7
−Voltage out
SYNC
8
O
I
Unrectified transformer output
Synchronization pin
SYNC
8
Unrectified transformer output
Synchronization pin
OUT
OUT
SYNC
14
SYNC
14
IN
:
IN
:
NOTE I = input and O = output.
NOTE I = input and O = output.
4
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
At T = 25°C, unless otherwise noted.
A
DCP010505B
OUTPUT RIPPLE vs LOAD (20MHz BW)
DCP010505B VOUT vs VS
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
50
45
40
35
30
25
20
15
10
5
µ
1 F Ceramic
µ
4.7 F Ceramic
µ
10 F Ceramic
0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VS (V)
10
20
30
40
50
60
70
80
90
100
Load (%)
DCP010505B VOUT vs LOAD
DCP010505B EFFICIENCY vs LOAD
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
85
80
75
70
65
60
55
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCP010505DB VOUT vs LOAD
DCP010505DB EFFICIENCY vs LOAD
5.8
5.7
5.6
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
85
80
75
70
65
60
55
+VOUT
−
VOUT
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
5
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
At T = 25°C, unless otherwise noted.
A
DCP010512B VOUT vs LOAD
DCP010512B EFFICIENCY vs LOAD
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
90
85
80
75
70
65
60
55
50
10
10
10
20
20
20
30
40
50
60
70
80
90
90
90
100
100
100
10
10
10
20
20
20
30
40
50
60
70
80
80
80
90
100
Load (%)
Load (%)
DCP010512DB VOUT vs LOAD
DCP010512DB EFFICIENCY vs LOAD
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
85
80
75
70
65
60
55
50
+VOUT
−
VOUT
30
40
50
60
70
90 100
30
40
50
60
70
80
Load (%)
Load (%)
DCP010515B VOUT vs LOAD
DCP010515B EFFICIENCY vs LOAD
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
85
80
75
70
65
60
55
50
30
40
50
60
70
90
100
30
40
50
60
70
80
Load (%)
Load (%)
6
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
At T = 25°C, unless otherwise noted.
A
DCP010515DB VOUT vs LOAD
DCP010515DB EFFICIENCY vs LOAD
18
17
16
15
14
90
85
80
75
70
65
60
55
50
+VOUT
−
VOUT
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCP012405B VOUT vs LOAD
DCP012405B EFFICIENCY vs LOAD
5.60
5.50
5.40
5.30
5.20
5.10
5.00
4.90
4.80
90
80
70
60
50
40
30
20
10
0
10
20
30
40
50
60
70
80
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCP010505B
CONDUCTED EMISSIONS (125% Load)
DCP010505B
CONDUCTED EMISSIONS (8% Load)
60
50
40
30
20
10
0
60
50
40
30
20
10
0
−
−
−
10
10
−
20
20
0.15
1
10
30
0.15
1
10
30
Frequency (MHz)
Frequency (MHz)
7
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
At T = 25°C, unless otherwise noted.
A
DCP011512DBP
EFFICIENCY vs LOAD
DCP011512DBP VOUT vs LOAD
13.50
13.00
12.50
12.00
11.50
11.00
10.50
80
75
70
65
60
55
50
45
40
35
30
+VOUT
−
VOUT
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90 100
Load (%)
Load (%)
DCP011515DBP
EFFICIENCY vs LOAD
DCP011515DBP VOUT vs LOAD
90
80
70
60
50
40
30
17.00
16.50
16.00
15.50
15.00
14.50
14.00
13.50
13.00
+VOUT
−
VOUT
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
DCP012415DBP EFFICIENCY vs LOAD
DCP012415DBP VOUT vs LOAD
16.50
16.00
15.50
15.00
14.50
14.00
13.50
90
80
70
60
50
40
30
20
+VOUT
−
VOUT
10
20
30
40
50
60
70
80
90
100
10
20
30
40
50
60
70
80
90
100
Load (%)
Load (%)
8
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
If synchronized devices are used, it should be noted that
at startup, all devices will draw maximum current
simultaneously. This can cause the input voltage to dip. If
it dips below the minimum input voltage (4.5V), the devices
may not start up. A 2.2µF capacitor should be connected
close to the input pins.
FUNCTIONAL DESCRIPTION
OVERVIEW
The DCP01B offers up to 1W of unregulated output power
with a typical efficiency of up to 85%. This is achieved
through highly integrated packaging technology and the
implementation of a custom power stage and control IC.
The circuit design uses an advanced BiCMOS/DMOS
process. For additional information, refer to the application
notes located in the DCP01B product folder at www.ti.com.
If more than eight devices are to be synchronized, it is
recommended that the SYNCIN pins are driven by an
external device. Details are contained in Application
Report SBAA035, External Synchronization of the
DCP01/02 Series of DC/DC Converters, available for
download at www.ti.com.
POWER STAGE
CONSTRUCTION
This uses a push-pull, center-tapped topology switching at
400kHz (divide-by-2 from 800kHz oscillator).
The DCP01B basic construction is the same as standard
ICs. There is no substrate within the molded package. The
DCP01B is constructed using an IC, rectifier diodes, and
a wound magnetic toroid on a leadframe. Since there is no
solder within the package, the DCP01B does not require
any special PCB assembly processing. This results in an
isolated DC/DC converter with inherently high reliability.
OSCILLATOR AND WATCHDOG
The onboard 800kHz oscillator generates the switching
frequency via a divide-by-2 circuit. The oscillator can be
synchronized to other DCP01B circuits or an external
source, and is used to minimize system noise.
A watchdog circuit checks the operation of the oscillator
circuit. The oscillator can be stopped by pulling the SYNC
pin low. The output pins will be tri-stated. This will occur in
2µs.
ADDITIONAL FUNCTIONS
DISABLE/ENABLE
The DCP01B can be disabled or enabled by driving the
SYNC pin using an open drain CMOS gate. If the SYNCIN
pin is pulled low, the DCP01B will be disabled. The disable
time depends upon the external loading; the internal
disable function is implemented in 2µs. Removal of the
pull-down will cause the DCP01B to be enabled.
THERMAL SHUTDOWN
The DCP01B is protected by a thermal shutdown circuit.
If the on-chip temperature exceeds 150°C, the device will
shut down. Once the temperature falls below 150°C,
normal operation will resume. If the thermal condition
continues, operation will randomly cycle on and off. This
will continue until the temperature is reduced.
Capacitive loading on the SYNCIN pin should be
minimized in order to prevent a reduction in the oscillator
frequency.
SYNCHRONIZATION
DECOUPLING
In the event that more than one DC/DC converter is
needed onboard, beat frequencies and other electrical
interference can be generated. This is due to the small
variations in switching frequencies between the DC/DC
converters.
Ripple Reduction
A high switching frequency of 400kHz allows simple
filtering. To reduce ripple, it is recommended that at least
a 1µF capacitor is used on VOUT. Dual outputs should have
both the positive and negative buses decoupled to VOUT
ground (pin 5). The required 2.2µF low equivalent series
resistance (ESR) ceramic capacitor on the input of the 5V
to 15V versions, and the ≥ 0.47µF low-ESR ceramic
capacitor on the 24V versions help reduce ripple and
noise. See Application Bulletin SBVA012, DC-to-DC
Converter Noise Reduction, available for download at
www.ti.com.
The DCP01B overcomes this by allowing devices to be
synchronized to one another. Up to eight devices can be
synchronized by connecting the SYNCIN pins together,
taking care to minimize the stray capacitance. Stray
capacitance (> 3pF) will have the effect of reducing the
switching frequency, or even stopping the oscillator circuit.
9
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
The outputs on dual output DCP01B versions can also be
connected in series to provide two times the magnitude of
Connecting the DCP01B in Series
Multiple DCP01B isolated 1W DC/DC converters can be
connected in series to provide nonstandard voltage rails.
This is possible by using the floating outputs provided by
the DCP01B galvanic isolation.
V
OUT, as shown in Figure 2. For example, a dual 15V
DCP01B could be connected to provide a 30V rail.
Connecting the DCP01B in Parallel
Connect the positive VOUT from one DCP01B to the
negative VOUT (0V) of another, as shown in Figure 1. If the
SYNCIN pins are tied together, the self-synchronization
feature of the DCP01B will prevent beat frequencies on the
voltage rails. The SYNCIN feature of the DCP01B allows
easy connection in series, which reduces separate filtering
components.
If the output power from one DCP01B is not sufficient, it is
possible to parallel the outputs of multiple DCP01B
converters (see Figure 3). Again, the SYNCIN feature
allows easy synchronization to prevent power-rail beat
frequencies at no additional filtering cost.
VSUPPLY
VOUT 1
VS
(1)
CIN
SYNCIN
0V
COUT
DCP
DCP
01B
01B
0V
VOUT 2
0V
VOUT1 + VOUT2
VS
(1)
CIN
COUT
SYNCIN
0V
µ
CIN requires a low−ESR ceramic capacitor: 5V to 15V version is 2.2 F;
NOTE: (1)
COM
µ
µ
24V version is minimum 0.47 F. COUT = 1.0 F.
Figure 1. Connecting the DCP01B in Series
VSUPPLY
+VOUT
VS
0V
+VOUT
(1)
COUT
(1)
CIN
−
VOUT
0V
−
VOUT
DCP
01B
(1)
COUT
µ
CIN requires a low−ESR ceramic capacitor: 5V to 15V version is 2.2 F;
NOTE: (1)
COM
µ
µ
24V version is minimum 0.47 F. COUT = 1.0 F.
Figure 2. Connecting Dual Outputs in Series
VSUPPLY
VOUT
VS
(1)
(1)
CIN
SYNCIN
0V
COUT
DCP
DCP
01B
01B
0V
2 x Power Out
VS
VOUT
(1)
(1)
COUT
CIN
SYNCIN
0V
0V
µ
IN requires a low−ESR ceramic capacitor: 5V to 15V version is 2.2 F;
C
NOTE: (1)
COM
µ
µ
24V version is minimum 0.47 F. COUT = 1.0 F.
Figure 3. Connecting Multiple DCP01Bs in Parallel
10
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
cycle so that all devices discharge together. A subsequent
charge cycle is only restarted when the last device has
finished its discharge cycle.
APPLICATION INFORMATION
The DCP01B, DCV01, and DCP02 are three families of
miniature DC/DC converters providing an isolated
unregulated voltage output. All are fabricated using a
CMOS/DMOS process with the DCP01B replacing the
familiar DCP01 family that was fabricated from a bipolar
process. The DCP02 is essentially an extension of the
DCP01B family providing a higher power output with a
significantly improved load regulation, and the DCV01 is
tested to a higher isolation voltage.
OPTIMIZING PERFORMANCE
Optimum performance can only be achieved if the device
is correctly supported. By the very nature of a switching
converter, it requires power to be instantly available when
it switches on. If the converter has DMOS switching
transistors, the fast edges will create a high current
demand on the input supply. This transient load placed on
the input is supplied by the external input decoupling
capacitor, thus maintaining the input voltage. Therefore,
the input supply does not see this transient (this is an
analogy to high-speed digital circuits). The positioning of
the capacitor is critical and must be placed as close as
possible to the input pins and connected via a
low-impedance path.
TRANSFORMER DRIVE CIRCUIT
Transformer drive transistors have a characteristically low
value of transistor on resistance (RDS); thus, more power
is transferred to the transformer. The transformer drive
circuit is limited by the base current available to switch on
the power transistors driving the transformer and their
characteristic current gain (beta), resulting in a slower
turn-on time. Consequently, more power is dissipated
within the transistor. This results in a lower overall
efficiency, particularly at higher output load currents.
The optimum performance is primarily dependent on two
factors:
1. Connection of the input and output circuits for
minimal loss.
SELF-SYNCHRONIZATION
2. The ability of the decoupling capacitors to maintain
the input and output voltages at a constant level.
The input synchronizations facility (SYNCIN), allows for
easy synchronizing of multiple devices. If two to eight
devices (maximum) have their respective SYNCIN pins
connected together, then all devices will be synchronized.
PCB Design
The copper losses (resistance and inductance) can be
minimized by the use of mutual ground and power planes
(tracks) where possible. If that is not possible, use wide
tracks to reduce the losses. If several devices are being
powered from a common power source, a star-connected
system for the track must be deployed; devices must not
be connected in series, as this will cascade the resistive
losses. The position of the decoupling capacitors is
important. They must be as close to the devices as
possible in order to reduce losses. See the PCB Layout
section for more details.
Each device has its own onboard oscillator. This is
generated by charging a capacitor from a constant current
and producing a ramp. When this ramp passes a
threshold, an internal switch is activated that discharges
the capacitor to a second threshold before the cycle is
repeated.
When several devices are connected together, all the
internal capacitors are charged simultaneously.
When one device passes its threshold during the charge
cycle, it starts the discharge cycle. All the other devices
sense this falling voltage and, likewise, initiate a discharge
11
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
Decoupling Ceramic Capacitors
Input Capacitor and the effects of ESR
All capacitors have losses due to their internal equivalent
series resistance (ESR), and to a lesser degree their
equivalent series inductance (ESL). Values for ESL are
not always easy to obtain. However, some manufacturers
provide graphs of Frequency versus Capacitor
Impedance. These will show the capacitors’ impedance
falling as frequency is increased (see Figure 4). As the
frequency is increased, the impedance will stop
decreasing and begin to rise. The point of minimum
impedance indicates the capacitors’ resonant frequency.
This frequency is where the components of capacitance
and inductance reactance are of equal magnitude. Beyond
this point, the capacitor is not effective as a capacitor.
If the input decoupling capacitor is not ceramic with
< 20mΩ ESR, then at the instant the power transistors
switch on, the voltage at the input pins will fall momentarily.
Should the voltage fall below approximately 4V, the DCP
will detect an under-voltage condition and switch the DCP
drive circuits to the off state. This is carried out as a
precaution against a genuine low input voltage condition
that could slow down or even stop the internal circuits from
operating correctly. This would result in the drive
transistors being turned on too long, causing saturation of
the transformer and destruction of the device.
Following detection of a low input voltage condition, the
device switches off the internal drive circuits until the input
voltage returns to a safe value. Then the device tries to
restart. If the input capacitor is still unable to maintain the
input voltage, shutdown recurs. This process is repeated
until the capacitor is charged sufficiently to start the device
correctly. Otherwise, the device will be caught up in a loop.
Z
XL
Normal startup should occur in approximately 1ms from
power being applied to the device. If a considerably longer
startup duration time is encountered, it is likely that either
(or both) the input supply or the capacitors are not
performing adequately.
0
Frequency
fO
Where:
XC is the reactance due to the capacitance,
XL is the reactance due to the ESL
fO the resonant frequency
For 5V to 15V input devices, a 2.2µF low-ESR ceramic
capacitor will ensure a good startup performance, and for
the remaining input voltage ranges, 0.47µF ceramic
capacitors are good. Tantalum capacitors are not
recommended, since most do not have low-ESR values
and will degrade performance. If tantalum capacitors must
be used, close attention must be paid to both the ESR and
voltage as derated by the vendor.
2
2
Z =
−
(XC XL) + (ESR)
√
Figure 4. Capacitor Impedance vs Frequency
At fO, XC = XL; however, there is a 180° phase difference
resulting in cancellation of the imaginary component. The
resulting effect is that the impedance at the resonant point
is the real part of the complex impedance; namely, the
value of the ESR. The resonant frequency must be well
above the 800kHz switching frequency of the DCP and
DCVs.
Output Ripple Calculation Example
DCP020505: Output voltage 5V, Output current 0.4A. At
full output power, the load resistor is 12.5Ω. Output
capacitor of 1µF, ESR of 0.1Ω. Capacitor discharge time
1% of 800kHz (ripple frequency):
The effect of the ESR is to cause a voltage drop within the
capacitor. The value of this voltage drop is simply the
product of the ESR and the transient load current, as
shown in Equation (1):
t
DIS = 0.0125µs
t = C × RLOAD
t = 1 × 10−6 × 12.5 = 12.5µs
VDIS = VO(1 − EXP(−tDIS/τ))
VDIS = 5mV
(
)
VIN + VPK * ESR ITR
(1)
Where:
V
IN is the voltage at the device input.
By contrast the voltage dropped due to the ESR:
VESR = ILOAD × ESR
VPK is the maximum value of the voltage on the
capacitor during charge.
VESR = 40mV
I
TR is the transient load current.
Ripple voltage = 45mV
The other factor that affects the performance is the value
of the capacitance. However, for the input and the full wave
outputs (single-output voltage devices), the ESR is the
dominant factor.
Clearly, increasing the capacitance will have a much
smaller effect on the output ripple voltage than reducing
the value of the ESR for the filter capacitor.
12
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
The Sync pin, when not being used, is best left as a floating
pad. A ground ring or annulus connected around the pin
will prevent noise being conducted onto the pin. If the Sync
pin is being connected to one or more Sync pins, then the
linking trace should be narrow and must be kept short in
length. In addition, no other trace should be in close
proximity to this trace because that will increase the stray
capacitance on this pin, and that will effect the
performance of the oscillator.
DUAL OUTPUT VOLTAGE DCP AND DCVs
The voltage output for the dual DCPs is half wave rectified;
therefore, the discharge time is 1.25µs. Repeating the
above calculations using the 100% load resistance of 25Ω
(0.2A per output), the results are shown below:
τ = 25µs
TDIS = 1.25µs.
V
DIS = 244mV
Ripple and Noise
VESR = 20mV
Careful consideration should be given to the layout of the
PCB, in order that the best results can be obtained.
Ripple Voltage = 266mV
This time, it is the capacitor discharging that is contributing
to the largest component of ripple. Changing the output
filter to 10µF, and repeating the calculations:
The DCP01B is a switching power supply and as such can
place high peak current demands on the input supply. In
order to avoid the supply falling momentarily during the
fast switching pulses, ground and power planes should be
used to connect the power to the input of DCP01B. If this
is not possible, then the supplies must be connected in a
star formation with the traces made as wide as possible.
Ripple Voltage = 45mV.
This value is composed of almost equal components.
The above calculations are given only as a guide.
Capacitor parameters usually have large tolerances and
can be susceptible to environmental conditions.
If the SYNCIN pin is being used, then the trace connection
between device SYNCIN pins should be short to avoid
stray capacitance. If the SYNCIN pin is not being used, it
is advisable to place a guard ring (connected to input
ground) around this pin to avoid any noise pick up.
PCB LAYOUT
Figure 5 and Figure 6 illustrate a printed circuit board
(PCB) layout for the two conventional (DCP01/02,
DCV01), and two SO-28 surface-mount packages
(DCP02U). Figure 7 shows the schematic.
The output should be taken from the device using ground
and power planes; this ensures minimum losses.
A good quality low-ESR ceramic capacitor placed as close
as practical across the input will reduce reflected ripple
and ensure a smooth startup.
Input power and ground planes have been used, providing
a low-impedance path for the input power. For the output,
the common or 0V has been connected via a ground plane,
while the connections for the positive and negative voltage
outputs are conducted via wide traces in order to minimize
losses.
A good quality low-ESR capacitor (ceramic preferred)
placed as close as practical across the rectifier output
terminal and output ground gives the best ripple and noise
performance. See SBVA012 for more information on noise
rejection.
The location of the decoupling capacitors in close
proximity to their respective pins ensures low losses due
to the effects of stray inductance; thus, improving the ripple
performance. This is of particular importance to the input
decoupling capacitor as this supplies the transient current
associated with the fast switching waveforms of the power
drive circuits.
THERMAL MANAGEMENT
Due to the high power density of this device, it is advisable
to provide ground planes on the input and output.
13
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
Figure 5. Example of PCB Layout, Component-Side View
Figure 6. Example of PCB Layout, Non-component-Side View
14
DCP01B SERIES
www.ti.com
SBVS012B − DECEMBER 2000 − REVISED OCTOBER 2004
CON3
1
CON1
1
2
VS1
VS3
0S3
28
14
C1
SYNC
JP1
SYNC
C11
JP1
2
3
27
26
0V1
+V1
NC
6
5
7
13
12
14
+V3
C3
C2−1
C2
DCP02xU
R1
DCP02xP
C12
C13
R5
COM1
COM3
R2
C5
C4−1
C4
R6
C14
C15
−
V1
−
V3
CON2
SYNC
CON4
SYNC
1
1
2
VS4
0S4
VS2
0V2
28
27
26
14
JP2
C16
JP2
C6
2
3
NC
13
12
14
6
5
7
+V4
+V2
DCP02xU
DCP02xP
C17
R7
C18
C7
R3
C8
C7−1
COM4
COM2
R8
C20
C19
R4
C10
C9−1
C9
−
V4
−
V2
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
Capacitors C2−1, C4−1, C7−1, and C9−1 are through-hole plated components connected in parallel with C2, C4, C7 and C9 (1206 SMD), respectively.
For optimum low-noise performance, use low-ESR capacitors.
Do not connect the SYNC pin jumper (JP1−JP4) if the SYNC function is not being used.
Connections to the power input should be made with a minimum wire of 16/0.2 twisted pair, with the length kept short.
VSx and 0Vx are input supply and ground respecively (x represents the channel).
+Vx and −Vx are the positive and negative outputs, referenced to a common ground COMx.
JPx are the links used for self-synchronization; if this facility is not being used, the links should be unconnected.
R1−R8 are the power output loads; do not fit these if an external load is connected.
CON1 and CON2 are DIL-14; CON3 and CON4 are SO-28 packages.
NC = not connected.
Figure 7. Example of PCB Layout, Schematic Diagram
15
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
PDIP
SOP
SOP
Drawing
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
NVA
DUA
DUA
DCP010505BP
DCP010505BP-U
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
25
25
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Level-NA-NA-NA
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
DCP010505BP-U/700
DCP010505DBP
700
25
DCP010505DBP-U
DCP010505DBP-U/700
DCP010512BP
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
700
25
DCP010512BP-U
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
DCP010512BP-U/700
DCP010512DBP
700
25
DCP010512DBP-U
DCP010512DBP-U/700
DCP010515BP
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
700
25
DCP010515BP-U
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
DCP010515BP-U/700
DCP010515DBP
700
25
DCP010515DBP-U
DCP010515DBP-U/700
DCP011512DBP
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
700
25
DCP011512DBP-U
DCP011512DBP-U/700
DCP011515DBP
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
700
25
DCP011515DBP-U
DCP011515DBP-U/700
DCP012415DBP
25
Level-3-240C-168 HR
Level-3-240C-168 HR
Level-NA-NA-NA
700
25
DCP012415DBP-U
DCP012415DBP-U/700
25
Level-3-240C-168 HR
Level-3-240C-168 HR
700
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDI058 – APRIL 2001
NVA (R-PDIP-T7/14)
PLASTIC DUAL-IN-LINE
D
0.775 (19,69)
0.735 (18,67)
14
8
0.280 (7,11)
0.240 (6,10)
D
1
Index
7
Area
E
H
0.070 (1,78)
0.045 (1,14)
0.195 (4,95)
0.325 (8,26)
Base Plane
0.115 (2,92)
0.300 (7,62)
0.015 (0,38)
0.210 (5,33)
MAX
MIN
C
– C –
C
0.150 (3,81)
0.115 (2,92)
0.300 (7,63)
E
0.005 (0,13)
0.100 (2,54)
0.022 (0,56)
0.014 (0,36)
0.008 (0,20)
D
MIN
Seating Plane
Full Lead
4 PL
C
0.060 (1,52)
0.000 (0,00)
0.014 (0,36)
0.010 (0,25)
0.430 (10,92)
M
C
MAX
F
F
4202489/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
I. Distance between leads including dambar protrusions
to be 0.005 (0,13) minumum.
J. A visual index feature must be located within the
cross–hatched area.
K. For automatic insertion, any raised irregularity on the
top surface (step, mesa, etc.) shall be symmetrical
about the lateral and longitudinal package centerlines.
L. Falls within JEDEC MS-001-AA.
C. Dimensions are measured with the package
seated in JEDEC seating plane gauge GS-3.
D. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
E. Dimensions measured with the leads constrained to be
perpendicular to Datum C.
F. Dimensions are measured at the lead tips with the
leads unconstrained.
G. Pointed or rounded lead tips are preferred to ease
insertion.
H. Lead shoulder maximum dimension does not include
dambar protrusions. Dambar protrusions shall not exceed
0.010 (0,25).
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS097 – APRIL 2001
DUA (R-PDSO-G7/14)
PLASTIC SMALL-OUTLINE
C
0.775 (19,69)
0.735 (18,67)
14
8
0.280 (7,11)
0.240 (6,10)
C
1
7
Index
Area
0.022 (0,56)
0.014 (0,36)
0.420 (10,70)
0.405 (10,30)
0.070 (1,78)
0.045 (1,14)
0.325 (8,26)
0.300 (7,62)
0.210 (5,33)
MAX
D
Base
Plane
0.014 (0,36)
0.008 (0,20)
Seating
Plane
0.043 (1,10)
0 " 5
°
0.100 (2,54)
0.015 (0,38)
MIN
0.025 (0,65)
0.057 (1,45)
0.045 (1,15)
0.005 (0,13) MIN
Full Lead
4 PL
C
4202490/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 (0,25).
D. Lead shoulder maximum dimension does not include
dambar protrusions. Dambar protrusions shall not exceed
0.010 (0,25).
E. Distance between leads including dambar protrusions
to be 0.005 (0,13) minimum.
F. A visual index feature must be located within the
cross–hatched area.
G. For automatic insertion, any raised irregularity on the top
surface (step, mesa, etc.) shall be symmetrical about
the lateral and longitudinal package centerlines.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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