DIR1701E [BB]
DIGITAL AUDIO INTERFACE RECEIVER; 数字音频接口接收器
| 型号： | DIR1701E |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | DIGITAL AUDIO INTERFACE RECEIVER |
| 文件： | 总19页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DIR1701
SLAS331 – APRIL 2001
DIGITAL AUDIO INTERFACE RECEIVER
FEATURES
DESCRIPTION
D
Standard Digital Audio Interface Receiver
(EIAJ1201)
The DIR1701 is a digital audio interface receiver
(DIR) which receives and decodes audio data up
to 96 kHz according to the AES/EBU, IEC958,
S/PDIF, and EIAJCP340/1201 consumer and
professional format interface standards. The
DIR1701 demultiplexes the channel status bit and
user bit directly to serial output pins, and has
dedicated output pins for the most important
channel status bits.
D
D
D
D
Sampling Rate: 32/44.1/48/88.2/96 kHz
Recover 128 / 256 / 384 / 512 f System Clock
s
Very Low Jitter System Clock Output (80ps
Typically)
On-Chip Master Clock Oscillator, Only an
External 12.000 MHz or 16.000 MHz Crystal Is
Required
D
D
Selectable Output PCM Audio Data Format
The significant advantages of the DIR1701 are
96 kHz sampling rate capability and Low-jitter
clock recovery by the Sampling Period Adaptive
ControlledTracking(SpAct )system. Inputsignal
is reclocked with the patented Sampling period
Adaptive controlled tracking system for maximum
quality. These two features are required for recent
consumer and professional audio instruments, in
which the DIR has an interface to any kind of
delta-sigma type ADC/DAC with 96 kHz sampling
rate.
Output User Bit Data, Flag Signals, and
Channel Status Data With Block Start Signal
D
Single + 3.3-V Power Supply
Package: 28 SSOP
D
APPLICATIONS
D
D
D
AV Receiver
MD Player
DAC Unit
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SpAct and Burr-Brown are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
1
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DIR1701
SLAS331 – APRIL 2001
DIR1701
(TOP VIEW)
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADFLG
BRATE0
BRATE1
SCKO
TEST
UNLOCK
FMT1
2
3
4
FMT0
5
V
V
DD
CC
6
DGND
XTO
AGND
FILT
RST
7
8
XTI
9
CKTRNS
LRCKO
BCKO
DOUT
SCF0
DIN
10
11
12
13
14
BRSEL
BFRAME
EMFLG
URBIT
CSBIT
SCF1
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
OPERATION
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
}
DIR1701E
Rails
†
324
DIR1701E
SSOP–28
–25°C to +85°C
DIR1701E
DIR1701E/2K
Tape and Reel
†
‡
TI equivalent no. 4040065.
Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of DIR1701E/2K will get a single 2000-piece tape and reel.
block diagram
SCF
BRSEL
FMT
V
DD
V
CC
XTI
SCKO
OSC
XTO
BCKO
OSC
Selector
LRCKO
DOUT
PLL1
Audio Clock
and Data
Generator
BFRAME
100 MHz
URBIT
CSBIT
EMFLG
ADFLG
DIN
PLL2
SpAct
wrclk
S/PDIF
DECODER
rdclk
FIFO
BRATE
2
DGND AGND
UNLOCK CKTRNS
FILT
RST
2
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DIR1701
SLAS331 – APRIL 2001
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
PIN
1
ADFLG
BRATE0
BRATE1
SCKO
O
O
O
O
–
–
O
I
Audio data or digital data flag
f rate flag 0 (32k, 44.1k, 48k, and 88k / 96k)
2
s
3
f rate flag 1 (32k, 44.1k, 48k, and 88k / 96k)
s
4
System clock output
V
5
Digital power supply, +3.3 V
Digital ground
DD
DGND
XTO
6
7
Crystal oscillator output
XTI
8
Crystal oscillator input, external clock input
Clock transition status output
CKTRNS
LRCKO
BCKO
DOUT
SCF0
SCF1
CSBIT
URBIT
EMFLG
BFRAME
BRSEL
DIN
9
O
O
O
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Audio latch enable (LRCK, f ) output
s
Audio bit clock output
Audio serial data output
System clock frequency select (128/256/384/512 f ) (see Note 1)
s
I
System clock frequency select (128/256/384/512 f ) (see Note 1)
s
O
O
O
O
I
Channel status bit output (see Note 2)
User bit output (see Note 2)
Emphasis flag
Block start clock (B-frame)
Default bit rate select (32 / 44.1 / 48 / 88.2 / 96k) (see Note 1)
S/PDIF data digital input (see Note 4)
Reset input, active LOW (see Note 3)
External filter
I
RST
I
FILT
–
–
–
I
AGND
Analog ground
V
Analog power supply, +3.3V
CC
FMT0
Audio data format select (see Note 1)
Audio data format select (see Note 1)
PLL unlock or parity error flag
Should be connected to DGND (see Note 1)
FMT1
I
UNLOCK
TEST
O
I
NOTES: 1. Schmitt trigger input with internal pulldown (TYP 51 kΩ), 5 V tolerant.
2. Serial outputs are utilized for both consumer and professional application.
3. Schmitt trigger input with internal pullup (TYP 51 kΩ), 5 V tolerant.
4. CMOS level input with internal pulldown (TYP 51 kΩ), 5 V tolerant.
3
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DIR1701
SLAS331 – APRIL 2001
†
absolute maximum ratings
Supply voltage, V , V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
CC DD
Supply voltage differences, V , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
CC DD
Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage: Digital input pins except XTI . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (6.5 V + 0.3 V)
XTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V + 0.3 V)
DD
Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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DIR1701
SLAS331 – APRIL 2001
electricalcharacteristics, allspecificationsatT =25°C,V =V =3.3V(unlessotherwisenoted)
A
CC
DD
PARAMETER
DIGITAL INPUT/OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(5)
(5)
V
V
V
V
V
V
V
V
V
V
2
5.5
0.8
IH
IL
(6)
(6)
(7)
(7)
(8)
(8)
(9)
(9)
70%V
IH2
IL2
IH3
IL3
OH
OL
OH
OL
DD
Input logic level
VDC
30%V
DD
5.5
70%V
DD
30%V
DD
I
I
I
I
= 1 mA
V
DD
–0.4
–0.4
O
O
O
O
= –2 mA
= 2 mA
0.5
Output logic level
Input leakage current
VDC
V
DD
= –4 mA
0.5
(10)
I
I
I
I
I
I
f
V
V
V
V
V
V
= V
65
100
10
IH
IN
IN
IN
IN
IN
IN
DD
= 0 V
= V
(10)
–10
–10
IL
(11)
10
IH
DD
= 0 V
= V
µA
(11)
–100
–10
–10
32
–65
IL
(6)
10
10
96
IH
DD
(6)
IL
(12)
= 0 V
Input sampling frequency
System clock frequency
kHz
MHz
s
128/256/
384/512 f
SCKO
4.096
49.152
s
t
j
SCKO clock jitter
SCKO duty cycle
80
ps RMS
50%
See
Table 3
XTI clock accuracy
–500
500
ppm
S/PDIF INPUT
Duty cycle
V
IN
V
IN
= 1.5 V,
= 1.5 V
f
= 96 kHz
s
15%
85%
20
Jitter
ns p-p
POWER SUPPLY REQUIREMENTS
V
, V
Voltage range
3
3.3
3.4
26
3.6
4.7
36
VDC
mA
DD CC
I (V
CC CC
)
)
Supply current (see Note 13)
Power dissipation
I (V
DD DD
P
D
100
mW
POWER SUPPLY REQUIREMENTS
Operation temperature
–25
85
°C
θ
Thermal resistance
28-pin SSOP
100
°C/W
JA
NOTES: 5. TTL compatible, except pins 8, 20: XTI, DIN.
6. Pin 8: XTI (CMOS logic level).
7. Pin 20: DIN (CMOS logic level).
8. Pins 1–3, 9, 17–18, 27: ADFLG, BRATE0, BRATE1, CKTRNS, EMFLG, BFRAME, UNLOCK.
9. Pins 4, 10–12, 15–16: SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT.
10. Pins 13–14, 19–20, 25–26, 28: SCF0, SCF1, BRSEL, DIN, FMT0, FMT1, CKSEL.
11. Pin 21: RST
12. f is defined as the incoming audio sampling frequency per channel.
s
13. No load connected to SCKO, LRCKO, BCKO, DOUT, CSBIT, URBIT. Power supply current varies according to the system clock
frequency.
5
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DIR1701
SLAS331 – APRIL 2001
basic operation theory
The DIR1701 has two PLLs, PLL1 and PLL2. The SpAct (Sampling Period Adaptive Controlled Tracking)
system is a newly developed clock recovery architecture, giving very low jitter clock from S/PDIF data input. The
DIR1701 requires a system clock input for operation of SpAct; internal PLL1 provides a 100 MHz execution
clock. The system clock can be obtained by either connecting a suitable crystal resonator at the XTI/XTO pins
or applying an external clock input at the XTI pin as shown in Figure 1. Internal PLL2 generates the system clock
SCKO by using the output signal of the SpAct frequency estimator.
When the S/PDIF input signal ceases, SCKO holds the latest tracked frequency. Also, the DIR1701 indicates
the unlocked state by a HIGH level output at the UNLOCK pin. When the S/PDIF signal restarts, the PLL will
lock in around 1ms with very low jitter, using the SpAct estimator. Then the DIR1701 indicates the locked status
by a LOW level output at the UNLOCK pin. In this status, the BRATE pins indicate the actual bit rate of the
incoming S/PDIF signal.
External Clock
C
Crystal
1
XTI
XTI
XTAL
OSC
CIR
XTAL
OSC
CIR
R
1
Open
XTO
XTO
C
R
2
1
= 1 MΩ,
C , C = 10 TO 33 pF
DIR1701
DIR1701
1
2
Crystal Resonator Connection
External Clock Input
Figure 1. System Clock Connections
system clock output
The primary function of the DIR1701 is to recover audio data and a low jitter clock from a digital audio
transmission line. The clocks that can be generated are SCKO (128/256/384/512 f , shown in Table 1), BCKO
S
(64 f ), and LRCKO (1 f ). SCKO is the output of the voltage controlled oscillator (VCO) in an analog PLL. The
S
S
PLL function consists of a VCO, phase and frequency detector, and a external second-order loop filter. The
closed-loop transfer function, which specifies the PLL jitter attenuation characteristics, is shown in Figure 2.
The crystal frequency should be defined for internal PLL by connecting the BRSEL pin to one of the output pins
BFRAME or CSBIT as shown in Table 2. A 12 MHz crystal resonator can be used for 128f (CSBIT), 256f
S
S
(OPEN) and 384f (BFRAME). And a 16 MHz crystal resonator is used for 512f (BFRAME). The system clock
S
S
frequency can be set by control data at SCF0, SCF1 pin (shown in Table 3); this data must be stable before reset
is applied.
Table 4 shows the state of the system and the condition of audio clocks and flags. Required accuracy of system
clock by either crystal resonator or external clock input is ±500 ppm.
Table 1. Generated System Clock (SCKO) Frequencies
SAMPLING
128 f
256 f
384 f
512 f
S
S
S
S
RATE
32 kHz
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
22.5792 MHz
24.576 MHz
12.288 MHz
16.9344 MHz
18.432 MHz
33.8688 MHz
36.864 MHz
16.384 MHz
22.5792 MHz
24.576 MHz
45.1584 MHz
49.152 MHz
44.1 kHz
48 kHz
88.2kHz
96 kHz
11.2896 MHz
12.288 MHz
6
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DIR1701
SLAS331 – APRIL 2001
system clock output (continued)
5
0
–5
–10
–15
–20
–25
–30
1 k
10 k
100 k
100
f – Frequency – Hz
Figure 2. Jitter Attenuator Characteristics With Specified Loop Filter
Table 2. Selectable Crystal Oscillators
SYSTEM CLOCK f
CRYSTAL
12 MHz
12 MHz
12 MHz
16 MHz
BRSEL CONNECTED TO
CSBIT
S
128
256
384
512
OPEN or DGND
BFRAME
BFRAME
Table 3. System Clock Selection
SCF1
SCF0
LOW
HIGH
LOW
HIGH
SYSTEM CLOCK
LOW
LOW
HIGH
HIGH
128 f
256 f
384 f
512 f
S
S
S
S
Table 4. System Clock and Data Output Operation
CONDITIONS
S/PDIF DATA
CLOCK AND DATA OUTPUTS
SCKO
BCKO
LRCKO
DOUT
BRATE
UNLOCK CS. UR BIT AD. EMFLG
Unknown
(128, 256, 384, 512 f )
S
Unknown
(64 f )
S
Unknown
(1 f )
S
After RESET
YES
MUTE
LOW
HIGH
LOW
HIGH
LOW
LOW
PLL
PLL
PLL
(1 f )
S
†
HOLD
(1 f )
S
DATA
DETECT
DATA
DATA
(128, 256, 384, 512 f )
(64 f )
S
S
†
†
HOLD
(128, 256, 384, 512 f )
HOLD
(64 f )
†
†
†
HOLD
NO
MUTE
HOLD
HOLD
S
S
†
Holds the latest tracked frequency.
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DIR1701
SLAS331 – APRIL 2001
SCKO timing
t
SCKH
H
L
2 V
SCKO
0.8 V
t
SCKL
System Clock Pulse
†
Cycle Time
SCKO Clock Pulse Width High
SCKO Clock Pulse Width Low
t
t
7 ns (min)
7 ns (min)
SCKH
SCKL
†
1/128 f , 1/256 f , 1/384 f or 1/512 f .
S
S
S
S
bit rate detection
By using the SpAct frequency estimator (not the S/PDIF channel status bit), the DIR1701 detects automatically
the sample rate of an incoming S/PDIF signal and indicates the frequency at the BRATE pins.
Table 5 lists the frequency ranges reported. Except for 88.2 and 96 kHz, these sample rates are the same as
the channel status bit defined in the S/PDIF specifications. When the bit-rate is 88.2 or 96 kHz the indicator
shows the same HL value. This state is not defined in the S/PDIF specifications.
Table 5. Incoming Sample Frequency Bits
SAMPLING RATE
32 kHz
BRATE1
HIGH
LOW
BRATE0
HIGH
LOW
44.1 kHz
48 kHz
LOW
HIGH
LOW
88.2 kHz
96 kHz
HIGH
HIGH
LOW
timing specification for PLL operation
lock-up time
Unlock
PLL
Lock
Condition
DIN Start
PLL Status
Indicator Pin
Site UNLOCK
H
L
t
< 1 ms
INT
Figure 3. PLL Lock Up Timing
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DIR1701
SLAS331 – APRIL 2001
relation between audio-data-output timing and PLL condition indicator timing
When the analog PLL is still unlocked and the S/PDIF signal starts, after at least ten rising edges, the S/PDIF
decoder can detect the incoming S/PDIF signal. The DOUT pin becomes LOW (MUTE) until the analog PLL
locks. This MUTE period t
is less than 1 ms (the analog PLL lockup time is less than 0.5 ms). When the
INT
decoder detects that incoming S/PDIF signal has stopped, UNLOCK goes HIGH at the next LRCKO transition.
SCKO keeps its frequency at the latest tracked bit rate.
When S/PDIF signal is not present after removal of reset, the frequency of the DIR1701 audio clocks (SCKO,
BCKO, LRCKO) is not known.
Unlock
Lock
PLL
Condition
H
L
UNLOCK
LRCKO
BCKO
DOUT
Mute
Mute
31
32
1
2
Figure 4. Relation Between Audio Data Output Timing and UNLOCK Flag Timing
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DIR1701
SLAS331 – APRIL 2001
unlock flag minimum pulse width time
CASE-A when PLL is unlocked
When the PLL is unlocked, the UNLOCK flag pin is HIGH and the audio data output DOUT becomes LOW
(MUTE). The MUTE period, t
the latest tracked frequency.
, is at least 200 ms. In this period, SCKO, BCKO, and LRCKO frequency hold
UNL
If an S/PDIF signal is connected again in this unlock period, the bit rate is changed to the incoming signal
frequency, afteratleast1ms(beforetheUNLOCKflaggoesLOW). TheCKTRNSpinindicatesvalidityofSCKO.
When CKTRNS is HIGH, the frequency of SCKO, BCKO, and LRCKO is in transition between states.
t
>200 ms
UNL
UNLOCK
LRCKO
H
L
CKTRANS
S/PDIF Signal Bit Rate
S/PDIF Signal Starts Again
New Bit Rate
BCKO
DOUT
t
< 1 ms
TRNS
1
2
Mute
Figure 5. UNLOCK Flag Minimum Pulse Width Time for PLL Unlocked
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DIR1701
SLAS331 – APRIL 2001
unlock flag minimum pulse width time (continued)
CASE-B when parity error occurs
When a parity error occurs in one subframe interval, UNLOCK becomes HIGH during this sub-frame then
returns LOW at the next arriving subframe.
During this subframe with parity error, the data output will hold the previous data of each channel.
CASE-B When Parity Error Occurs
H
L
UNLOCK
LRCKO
BCKO
DOUT
24
1
24
1
2
Same as The Previous Data
Figure 6. UNLOCK Timing for Parity Error
PCM audio interface
The DIR1701 can produce 16-bit or 24-bit output data in standard format and 24-bit output data in IIS format.
The PCM audio interface format of the DIR1701 is selected using the format pins FMT1, FMT0. Table 6 shows
the FMT pin configuration.
Table 6. Audio Output Data Format Select
FMT1
LOW
LOW
HIGH
HIGH
FMT0
LOW
HIGH
LOW
HIGH
AUDIO DATA FORMAT
16 bit MSB first, Right justified
24 bit MSB first, Right justified
24 bit MSB first, Left justified
24 bit IIS
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DIR1701
SLAS331 – APRIL 2001
PCM audio interface (continued)
Standard Data Format; L–Channel = HIGH, R–Channel = LOW
1/f
S
LRCKO
R–Channel
L–Channel
BCKO
Right Justified
Audio Data Word = 16–Bit
1
2
1 2
DOUT 14 15 16
15 16
LSB
15 16
LSB
MSB
MSB
Right Justified
Audio Data Word = 24–Bit
DOUT
22 23 24
1
2
23 24
LSB
1
2
23 24
LSB
MSB
MSB
Left Justified
Audio Data Word = 24–Bit
DOUT
1
2
23 24
LSB
1
2
23 24
LSB
MSB
MSB
IIS Data Format; L–Channel = LOW, R–Channel = HIGH
1/f
S
LRCKO
BCKO
L–Channel
R–Channel
Audio Data Word = 24–Bit
DOUT
1
2
23 24
LSB
1
2
23 24
LSB
1
MSB
MSB
Figure 7. Audio Data Output Format
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DIR1701
SLAS331 – APRIL 2001
PCM audio interface (continued)
50% of V
DD
SCHO
t
t
LS
SL
50% of V
LRCHO
DD
t
t
t
LB
BCH
BCL
50% of V
50% of V
BCHO
DOUT
DD
DD
t
t
BCY
BL
t
t
DS
DH
PARAMETERS
MIN
11
MAX UNITS
t
t
t
t
t
t
t
t
t
SCKO rising edge to LRCKO edge
LRCKO edge to SCKO rising edge
BCKO pulse cycle time
ns
ns
SL
5
LS
64 f
BCY
BCL
BCH
BL
S
BCKO pulse width low
78
78
78
78
78
78
ns
ns
ns
ns
ns
ns
BCKO pulse width high
BCKO rising edge to LRCKO edge
LRCKO edge to BCKO rising edge
DOUT setup time
LB
DS
DOUT hold time
DH
Figure 8. Audio Data Output Timing
dedicated output pins for both professional and consumer applications
The DIR1701 has parallel output pins for both professional and consumer applications. In professional mode
de-emphasis flag EMFLG indicates a 50/15-µs time constant pre-emphasis. Professional mode is set when Bit
0 of CSBIT Byte 0 is HIGH. When Bits 2 to 4 of CSBIT Byte 0 is 110, the EMFLG becomes HIGH. In other cases,
EMFLG is LOW. Audio/non-audio flag ADFLG indicates S/PDIF data mode, i.e., Bit 1 of CSBIT Byte 0. When
ADFLG is LOW, S/PDIF data includes PCM audio signal. In other cases, ADFLG is HIGH.
In consumer mode EMFLG indicates 2-channel audio with a 50/15-µs time constant pre-emphasis. Consumer
mode is set when Bit 0 of CSBIT Byte 0 is LOW. When Bits 3 to 5 of CSBIT Byte 0 is 100, EMFLG becomes
HIGH. In other cases, EMFLG is LOW. The ADFLG signal indicates whether S/PDIF includes digital data, such
as AC-3 or not. When Bit 1 of CSBIT Byte 0 is HIGH, the incoming S/PDIF includes non-audio signal. In other
cases, ADFLG is LOW.
These dedicated output pins are checked for only L-ch CS information. The DIR1701 does not support CRC
check function in professional mode. As for other flags, CS bit and user-bit for professional and consumer
applications, are directly supplied by serial mode at CSBIT (pin 15) and URBIT (pin 16). These pins indicate
L-ch and R-ch information sequentially.
13
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DIR1701
SLAS331 – APRIL 2001
dedicated output pins for both professional and consumer applications (continued)
Audio data and clock timing are described below. The serial output data starts after 16±8 BCKO clocks from
when the corresponding subframe arrives. When B subframe arrives, BFRAME pin becomes HIGH during
1/f x 32 (s), then BFRAME returns to LOW after 32 frames.
s
1/f (S)
S
Frame 0
Frame 1
Frame 191
W
Frame 0
R191
S/PDIF
B
W
M
W
M
B
16 ± 8 BCKO Delay
64 BCKO
L1 R1
URBIT/CSBIT/UNLOCK etc.
LRCKO
L0
R0
L191
BFRAME
1/f x 32 (S)
S
1/f x 192 (S)
S
LRCKO
BCKO
DOUT
64 1
2 3
Figure 9. Timing Chart for Audio Data and Channel Status
14
www.ti.com
DIR1701
SLAS331 – APRIL 2001
reset sequence
The DIR1701 requires external reset operation after power on. Figure 10 shows the reset sequence after power
on. The DIR1701 is ready for receiving S/PDIF signal when the internal reset sequence has finished and
CKTRNS goes to LOW. BFRAME, EMFLG, URBIT and CSBIT pins are used for configuration during the period
from the rising edge of RST to the falling edge of CKTRNS. S/PDIF signal is accepted after CKTRNS goes to
LOW.TheminimumpulsewidthofRST,t
be at least 10 ms. All of the output pins except CKTRNS and UNLOCK are LOW during RST LOW.
is100ns.TheRSTdelayafterthepowersupplyreaches3Vshould
RST
3 V
V , V
DD CC
XTI
Stable
Unstable
XTO
RST
DIR1701 Ready
Internal PLL ON
t
> 10 ms
STT
LOW
LOW
HIGH
HIGH
t
> 100 ns
RST
BFRAME,
EMFLG,
VRBIT,
12.5XTI Clock
Chip Status Information
LOW
Unknown
Valid
CSBIT
1160XTI Clock
CKTRNS
DIN
< 5 f
s
S/PDIF Acceptable
< 1 ms
HIGH
UNLOCK
NOTE: SCF0 and SCF1 should be settled during RST assertion. The change of SCF0 and SCF1 is not permitted during normal operation. When
the change is needed, the reset sequence must be started by asserting RST again.
Figure 10. After Power ON
15
www.ti.com
DIR1701
SLAS331 – APRIL 2001
typical circuit connection
1
2
28
27
26
25
24
23
22
21
20
19
18
ADFLG
TEST
UNLOCK
FMT1
BRATE0
BRATE1
SCKO
Bit Rate Indicator
3
4
Data Format Select
FMT0
5
3.3 V V
V
DD
V
CC
3.3 V V
CC
DD
+
+
C
C
C
4
C
3
7
C
2
1
6
DGND
XTO
AGND
FILT
RST
DIN
R
C
8
2
7
R
1
8
Reset (Active LOW)
Receiver Circuit
XTI
9
C
5
C
CKTRNS
LRCKO
6
10
11
12
BRSEL
BFRAME
EMFLG
URBIT
BCKO
17
16
15
DOUT
SCF0
SCF1
13
14
System Clock
Frequency Select
(128,256,348, 512 f )
CSBIT
s
BRSEL Connection Depends Upon
Crystal Resonator Frequency.
Audio Data
Processor
C
C
C
C :
C :
, C : Bypass Capacitor, 1 µF to 10 µF
2
1
3
5
7
8
, C : Bypass Capacitor, 0.01 µF to 0.1 µF
4
, C : OSC Capacitor, 10 to 33 pF
6
Loop Filter Capacitor, 0.022 µF
Ripple Capacitor, 0.0022 µF
OSC Resistor, 1 MΩ
R :
R :
1
2
Loop Filter Resistor, 6.8 kΩ
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
16
www.ti.com
®
PACKAGE DRAWING
MPDS072
DIR1701
SLAS331 – APRIL 2001
(This page has been left blank intentionally.)
18
www.ti.com
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its products to the specifications applicable at the time of sale in accordance with
TI’sstandardwarranty. TestingandotherqualitycontroltechniquesareutilizedtotheextentTIdeemsnecessary
to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except
those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
products or services might be or are used. TI’s publication of information regarding any third party’s products
or services does not constitute TI’s approval, license, warranty or endorsement thereof.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation
or reproduction of this information with alteration voids all warranties provided for an associated TI product or
service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Resale of TI’s products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service,
is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use.
Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
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