DSD1700 [BB]
Direct Stream Digital⑩ DSD⑩ TM Audio DIGITAL-TO-ANALOG CONVERTER; 直接流Digital⑩ DSD⑩ TM音频数位类比转换器
| 型号： | DSD1700 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Direct Stream Digital⑩ DSD⑩ TM Audio DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总8页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
DSD1700
DSD1700
For most current data sheet and other product
information, visit www.burr-brown.com
Direct Stream Digital™ (DSD™)
TM
Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
● SUPER AUDIO CD (SACD™) PLAYERS
● DIRECT TRANSFER OF DSD DATA
STREAM TO ANALOG OUTPUT SIGNAL
● PROFESSIONAL DSD PROCESSORS
● PROFESSIONAL DSD CONSOLES
● DUAL DIFFERENTIAL ANALOG FIR FILTER
● DIRECT, CMOS LOGIC INTERFACE TO
DSDTM DECODER IC
Data Clock: 2.8224 MHz (64 • 44.1kHz)
System Clock: 11.2896 MHz (256 • 44.1kHz)
DESCRIPTION
The DSD1700 is a unique digital-to-analog converter
designed for DSD audio applications. The DSD1700
consists of a single-channel, 8-tap analog FIR filter
constructed using a double differential circuit architec-
ture, ensuring excellent dynamic performance and
high power- supply noise rejection. The DSD1700
also includes the necessary logic required to interface
directly to a DSD decoder IC.
● EXCELLENT DYNAMIC PERFORMANCE
THD+N: 0.001% (typ)
Dynamic Range: 110dB (typ)
SNR: 110dB (typ)
Frequency Response (–3dB): 100kHz
● SINGLE +5V SUPPLY OPERATION
● SMALL 28-LEAD SSOP PACKAGE
The overall features and performance of the DSD1700
make it an ideal choice for high-performance Super
Audio CD players and DSD studio applications.
All trademarks are property of their respective owners.
VDD
Analog FIR
IOUTHP
(HOT/P)
Duty
Generator
Shift Register
(HOT)
PHASE
DATA
DSD I/F
VDD
Analog FIR
(HOT/N)
IOUTHN
RST
DCK
SCK
Timing
Generator
Analog FIR
(COLD/P)
I
OUTCP
Duty
Generator
Shift Register
(COLD)
VDD
Power
Supply
DGND
VCC
Analog FIR
(COLD/N)
IOUTCN
AGND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1999 Burr-Brown Corporation
PDS-1555A
Printed in U.S.A. December, 1999
SPECIFICATIONS
All specifications TA = +25°C, VDD = VCC = 5.0V, fS = 44.1kHz, data clock = 64fS, system clock = 256fS, unless otherwise specified. (Although the sampling frequency
of Direct Stream Digital is 2.8224MHz, for convenience, in this specification sheet, it is described that the sampling frequency (fS) is 44.1kHz and the 2.8224MHz
clock is 64fS).
DSD1700E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CLOCK
Data Clock Frequency (DCK)
System Clock Frequency (SCK)
64fS
256fS
2.8224
11.2896
MHz
MHz
SCK AC REQUIREMENT(1)
Input Clock Duty Cycle
50
%
DIGITAL INPUT
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VIH
VIL
IIH
0.7VDD
V
V
µA
µA
µA
0.3VDD
±10
±10
(2)
IIL
IIL
(3)
–120
ANALOG OUTPUT(5)
Full-Scale Voltage
Gain Error
Offset Error
Output Impedance(4)
4.1VCC
±4
±0.1
2
Vp-p
% of FSR
% of FSR
kΩ
±10
±1
DYNAMIC PERFORMANCE(5)
THD+N, VOUT = 0dB
Dynamic Range
Signal-to-Noise Ratio
Frequency Response, –3dB
with 30kHz GIC Filter
with 30kHz GIC Filter
with 30kHz GIC Filter
0.001
110
110
%
dB
dB
100
kHz
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current
Power Dissipation
VCC, VDD
VCC = VDD = 5.0V
VCC = VDD = 5.0V
4.5
5
5.5
27.5
5.5
8.0
40
VDC
mA
mW
ICC+IDD
TEMPERATURE RANGE
Operating
Storage
–25
–55
+85
+125
°C
°C
Thermal Resistance
θJA
28-Pin SSOP
100
°C/W
NOTES: (1) See description of system clock in the Functional Description section of this data sheet. (2) Pins 26, 27, 28: DATA. DCK. SCK. (3) Pins 3, 4: RST, PHASE
(with internal pull-up). (4) Pins 13, 14, 15, 16: IOUTHN, IOUTCP, IOUTCN, IOUTHP. (5) Measure DSD signal modulated fSIG = 1kHz with 50% scaling factor through
standard differential to single-ended converter (see Figure 10) using Audio Precision System II in rms mode with 20kHz LPF and 400Hz HPF.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
2
DSD1700
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN
NAME
I/O
DESCRIPTION
Top View
SSOP
1
2
3
4
DGND
VDD
—
—
IN
IN
Digital Ground
Digital Power Supply: +5V
Reset Control Input, Active LOW(1)
RST
PHASE
Select data phase
(LOW = Normal; HIGH = Invert)
DGND
VDD
1
2
3
4
5
6
7
8
9
28 SCK
27 DCK
26 DATA
25 AGND
24 VCC
5
AGND
VCC
—
—
Analog Ground
6
Analog Power Supply: +5V
Analog Ground
7
AGND
VCC
—
RST
8
—
Analog Power Supply: +5V
Analog Power Supply: +5V
Analog Ground
PHASE
AGND
VCC
9
VCC
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
AGND
VCC
—
—
Analog Power Supply: +5V
Analog Ground
23 AGND
22 VCC
AGND
—
AGND
VCC
I
OUTHN
OUTCP
OUTCN
OUTHP
OUT
OUT
OUT
OUT
—
Analog Output from DAC (Hot Negative)
Analog Output from DAC (Cold Positive)
Analog Output from DAC (Cold Negative)
Analog Output from DAC (Hot Positive)
Analog Ground
DSD1700
I
21 VCC
I
VCC
20 AGND
19 VCC
I
AGND
AGND
VCC
AGND 10
VCC 11
—
Analog Ground
18 AGND
17 AGND
—
Analog Power Supply: +5V
Analog Ground
AGND
VCC
—
AGND 12
OUTHN 13
—
Analog Power Supply: +5V
Analog Power Supply: +5V
Analog Ground
I
16
15
I
I
OUTHP
OUTCN
VCC
—
AGND
VCC
—
I
OUTCP 14
—
Analog Power Supply: +5V
Analog Ground
AGND
DATA
DCK
—
IN
Direct Stream Digital Data Input
Data Clock Input
IN
SCK
IN
System Clock Input
NOTE: (1) With internal pull-up resistor
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
Supply Voltage(2) .............................................................................. +6.5V
Supply Voltage Differences(3) ........................................................... ±0.1V
Ground Voltage Differences(4) .......................................................... ±0.1V
Digital Input Voltage ................................................... –0.3V to VDD +0.3V
Input Current (any pins except supplies) ....................................... ±10mA
Operating Temperature ....................................................–25°C to +85°C
Storage Temperature .....................................................–55°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, peak, 10s) ............................... +235°C
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. (2) VCC, VDD. (3) Among VCC, VDD. (4) Among AGND, DGND.
PACKAGE/ORDERING INFORMATION
PACKAGE
SPECIFIED
DRAWING
NUMBER
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
DSD1700E
28-Lead SSOP
324
0°C to +70°C
DSD1700E
DSD1700E
Rails
"
"
"
"
"
DSD1700E/2K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “DSD1700E/2K” will get a single 2000-piece Tape and Reel.
®
3
DSD1700
DECODER INTERFACE
GENERAL INFORMATION
The decoder interface consists of several CMOS logic in-
puts. The system clock input, SCK (pin 28), operates at
11.2896MHz (256 • 44.1kHz). The data bit clock, DCK
(pin 27), operates at 2.8244 MHz (64 • 44.1kHz) and is the
64x oversampled data clock. The 1-bit, 64x oversampled
data stream is input at DATA (pin 26). DATA and DCK are
synchronized to the SCK falling edge.
The DSD1700 is designed solely for use in DSD and SACD
applications. It is not compatible with standard CD audio
transports, or DVD/MPEG-2 decoders. Burr-Brown manu-
facturers a wide array of products for these applications.
Please refer to our audio brochure and product data sheets,
available from our web site (www.burr-brown.com) and
local sales offices.
The DSD1700 generates HOT and COLD data internally for
use with the double differential analog FIR filter. The
PHASE input (pin 4) is used to determine the polarity of the
HOT and COLD data (normal or inverted). The PHASE
input is synchronized to the rising edge of SCK.
FUNCTIONAL DESCRIPTION
The concept of Direct Stream Digital (DSD) conversion is
simple. An analog audio input is digitized by a 1-bit, 64x
oversampled delta-sigma modulator. The 1-bit data stream is
then stored and may be transferred to a SACD disc at a later
time. For playback, the 1-bit, 64x oversampled data is then
presented to the DSD1700 directly by a DSD decoder IC.
The DSD1700 then low-pass filters the oversampled data to
reconstruct the original analog audio waveform. The record-
ing and playback functions are illustrated in Figures 1 and 2
respectively.
The RST input (pin 3) is used for system reset purposes.
RST should be High for normal operation, and Low for reset
operation. When RST is held Low, the current outputs of the
analog FIR filter are set to the bipolar zero (BPZ) level. The
RST signal is synchronized to the rising edge of SCK.
TIMING
Figures 3 though 6 show the timing diagrams for the
DSD1700 interface signals. Figure 3 shows the system clock
(SCK) timing requirements. Figure 4 shows the general
timing for the data input. Figures 5 and 6 show the detailed
timing for the DSD data and control data inputs.
To perform the digital-to-analog conversion, the DSD1700
includes both the decoder interface logic and an analog FIR
filter. The following paragraphs provide a summary of these
functions.
Loop Filter
Interface
Logic
Low-Pass
Filter
(Noise Shaping
and Integration)
1-Bit
Quantizer
DSD
Input
(64fS, 1-Bit)
DSD
Output
(64fS, 1-Bit)
+
Analog
Output
Analog
Input
LOGIC
Q
∫
–
FIGURE 2. DSD Playback.
FIGURE 1. DSD Recording.
tSCKH
VIH
VIL
High
VIH = 0.7VDD
VIL = 0.3VDD
System Clock
Low
tSCKL
1/256 fS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tSCKH
tSCKL
System Clock Pulse Width High
System Clock Pulse Width Low
10
10
ns
ns
FIGURE 3. System Clock Timing.
RST
SCK (256fS)
DATA
DCK (64fS)
FIGURE 4. Input Signal Timing.
®
4
DSD1700
SCK
tSCWL
tSCWH
tSCY
DCK
tDCH
tDCS
DATA
tDAH
tDAS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tSCWH
tSCWL
tSCY
tDCS
tDCH
tDAS
SCK Pulse Width High
SCK Pulse Width Low
SCK Pulse Cycle Time
DCK Setup Time
DCK Hold Time
DATA Setup Time
DATA Hold Time
10
10
ns
ns
sec
ns
ns
ns
1/(256fS)
15
5
15
5
tDAH
ns
FIGURE 5. DSD Data Input Timing.
SCK
tSCWH
tSCWL
tSCY
PHASE
RST
tPH
tPS
tRH
tRS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tSCWH
tSCWL
tSCY
tPS
tPH
tRS
SCK Pulse Width High
SCK Pulse Width Low
SCK Pulse Cycle Time
PHASE Setup Time
PHASE Hold Time
RST Setup Time
10
10
ns
ns
sec
ns
ns
ns
1/(256fS)
15
5
15
5
tRH
RST Hold Time
ns
FIGURE 6. Control Data Input Timing.
®
5
DSD1700
ANALOG FIR FILTER
Figure 7. Prior to the analog FIR filters, the duty cycle of the
DSD input signal is set to 75% by the DSD1700’s duty
generators.
The low-pass filter function for the DSD1700 is constructed
by using four 8-tap, analog FIR filters with current outputs.
The four filters include one each for HOT and COLD
positive, and one each for HOT and COLD negative. This is
referred to as a double differential architecture. These filters
use resistors to set the filter coefficients, as shown in
Plots of the analog FIR filter response is shown in Figure 8.
The stop-band attenuation of the filters dictates that addi-
tional low-pass filtering is required at the output of the
external current-to-voltage converter circuit (see Figure 10).
D0
D1
D2
D3
D4
D5
D6
D7
R0
R1
R2
R3
R4
R5
R6
R7
IOUT
FIGURE 7. Analog FIR Filter Structure.
FREQUENCY RESPONSE
(DC – 11.2896MHz)
FREQUENCY RESPONSE
(DC – 1.4112MHz)
0
0
–50
–50
–100
–100
0
5,644,800
11,289,600
0
705,600
1,411,200
Frequency (Hz)
Frequency (Hz)
FIGURE 8. Analog FIR Filter Frequency Response.
®
6
DSD1700
CURRENT-TO-VOLTAGE (I/V)
CONVERTER CIRCUIT
APPLICATIONS INFORMATION
TYPICAL CONNECTIONS
The DSD1700 is a current output device, and requires an
I/V conversion circuit to transform the double-differential
outputs into a usable voltage output. The circuit in Figure 10
is recommended for this purpose. Op amps are OPA134 or
equivalent.
Figure 9 shows the basic connection diagram for the
DSD1700. A significant number of power supply bypass
capacitors are required, and Burr-Brown recommends the
indicated values for optimal performance.
+5V
DSD1700
1
2
3
4
5
6
7
8
9
DGND
VDD
SCK 28
DCK 27
DATA 26
AGND 25
VCC 24
System Clock
C1
Direct
Stream
Digital™
Data
System Reset
Phase Control
RST
PHASE
AGND
VCC
C6
C7
C8
C9
C1
C3
C4
C5
AGND 23
VCC 22
AGND
VCC
VCC 21
VCC
AGND 20
VCC 19
10 AGND
11 VCC
AGND 18
AGND 17
IOUTHP 16
12 AGND
13
14
I
I
OUTHN
OUTCP
Analog
Ground
=
I
OUTCN 15
NOTE: C1 = 0.1µF ceramic and 1-100µF. C2 - C9 = 0.1µF ceramic each and 1-100µF chemical.
FIGURE 9. Basic Connection Diagram.
+18V
0.1µF
+18V
0.1µF
100pF
1kΩ
1kΩ
IOUTCN
8.2 kΩ
220pF
I
OUTHP
7
2
3
4.7kΩ
4.7kΩ
6
OPA134
+5V
1
4
7
2
3
4.7kΩ
4.7kΩ
470pF
–18V
+18V
Analog
Out
6
OPA134
470pF
1
4
0.1µF
7
2
3
4.7kΩ
6
OPA134
1
4
–18V
1kΩ
1kΩ
8.2 kΩ
4.7kΩ
220pF
IOUTCP
100pF
I
OUTHN
Analog
Ground
=
0.1µF
–18V
FIGURE 10. Recommended I/V Conversion Circuit.
®
7
DSD1700
PRINTED CIRCUIT BOARD LAYOUT
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic perfor-
mance of the DSD1700.
A typical PCB floor plan for the DSD1700 is shown in
Figure 11. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a
split in the plane. The DSD1700 should be oriented with the
digital I/O pins facing the ground plane split/cut, allowing
for direct connection to the DSD decoder and control signals
originating from the digital section of the board.
Digital Power
Analog Power
+VD
DGND
AGND +5VA
+VS –VS
VCC
VDD
DSD™ Decoder
and
Output
DGND
Circuits
Control Logic
DSD1700
Digital
Ground
AGND
Analog
Ground
DIGITAL SECTION
ANALOG SECTION
Return Path for Digital Signals
FIGURE 11. Recommended PCB Layout Technique.
®
8
DSD1700
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