DSD1702E/2K [BB]
ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER; 增强的多格式， DELTA- SIGMA ，音频数位类比转换器
| 型号： | DSD1702E/2K |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | ENHANCED MULTIFORMAT, DELTA-SIGMA, AUDIO DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总28页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
ENHANCED MULTIFORMAT, DELTA-SIGMA,
AUDIO DIGITAL-TO-ANALOG CONVERTER
D
Dual Supply Operation:
5-V Analog, 3.3-V Digital
FEATURES
D
Supports DSD and PCM Format
D
5-V Tolerant Digital Inputs
D
Accepts 16-, 18-, 20- and 24-Bit Audio Data for
PCM Format
D
Small 20-Lead QSOP Package
D
D
Accepts Direct Stream Digital (1 bit)
APPLICATIONS
Analog Performance (V
– Dynamic Range: 106 dB Typ
– SNR: 106 dB Typ
= 5 V):
CC
D
D
D
D
Universal A/V Players
SACD Players
– THD+N: 0.0015% Typ
– Full–Scale Output: 3.1 V(pp) Typ
Car Audio Systems
Other Applications Requiring 24-Bit Audio
D
Includes 8x Oversampling Digital Filter for
PCM Format:
– Stopband Attenuation: –60 dB
– Passband Ripple: ±0.02 dB
DESCRIPTION
The DSD1702 is
a CMOS, monolithic, stereo
digital-to-analog converter that supports both PCM
audio data format and direct stream digital (DSD) audio
data format.
D
D
Including Digital DSD Filter For DSD Format:
– Passband Choices: 50 kHz, 70 kHz or
60 kHz at –3 dB
The device includes an 8x digital interpolation filter for
PCMsignals. A digital DSD filter provides three different
selectable frequency response options, followed by
Burr-Brown’s enhanced multilevel delta-sigma
modulator employing 4th-order noise shaping and
8-level amplitude quantization. This design achieves
excellent dynamic performance and improved
tolerance to clock jitter.
Sampling Frequency:
– PCM Mode: 10 kHz to 200 kHz
– DSD Mode: 64 × 44.1 kHz
D
D
System Clock:
– 128f 192f , 256f , 384f 512f , 768f
s
s
s
s
s
s
Data Formats:
– Standard, I S, and Left-Justified for PCM
Direct Stream Digital
2
DSD1702 sampling rates of up to 192 kHz for PCM
mode and 44.1 kHz × 64 for DSD mode are supported.
A full set of user-programmable functions is accessible
through a 3-wire serial control port, supporting register
write functions.
D
User-Programmable Mode Controls:
– Digital Attenuation
– Digital De-Emphasis
– Digital Filter Roll-Off: Sharp or Slow Soft
Mute
– Zero Detect Mute
The DSD1702 is available in a 20-lead QSOP package.
– Zero Flags for Each Output
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
1
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
DSD1702
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DSDL
DSDR
PBCK
PDATA
PLRCK
DGND
DBCK
DSCK
PSCK
MS
MC
MD
V
V
ZEROL/NA
ZEROR/ZEROA
DD
CC
V
L
V
OUT
COM
V
R
AGND
OUT
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING NUMBER
OPERATION
TEMPERATURE RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA
PRODUCT
PACKAGE
†
DSD1702E
Rails
DSD1702E
QSOP–20
4073301
–25°C to 85°C
DSD1702E
DSD1702E/2K
Tape and Reel
†
Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of DSD1702E/2K will get a single 2000-piece tape and reel.
block diagram
PLRCK
ZEROL
PCM
Filter
(×8 DF)
PCM
I/F
PBCK
ZEROR/ZEROA
PDATA
V
L
OUT
Multilevel
Delta-Sigma
Modulator
PSCK
M
U
X
M
U
X
Analog
LPF
Multilevel
DAC
V
V
R
OUT
DSCK
DBCK
COM
DSD
DSD
Filter
DSDL
DSDR
I/F
MS
MC
MD
Mode
Control
Power Control
V
CC
DGND AGND V
DD
2
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
Terminal Functions
TERMINAL
I/O
DESCRIPTIONS
NAME
DSDL
PIN
1
I
I
Audio data digital input (DSD L–channel) (see Note 1)
Audio data digital input (DSD R–channel) (see Note 1)
Audio data bit clock input. (PCM) (see Note 1)
Audio data digital input. (PCM) (see Note 1)
Audio data latch enable input. (PCM) (see Note 1)
Digital ground
DSDR
PBCK
PDATA
PLRCK
DGND
2
3
I
4
I
5
I
6
–
–
–
O
O
–
–
O
O
I
V
V
V
V
7
Digital power supply, 3.3 V
DD
8
Analog power supply, 5 V
CC
L
9
Analog output for L–channel
OUT
R
10
11
12
13
14
15
16
17
18
19
20
Analog output for R–channel
OUT
AGND
Analog ground
V
COM
Common voltage decoupling
ZEROR/ZEROA
ZEROL/NA
MD
Zero flag output for R–channel/zero flag output for L/R–channel. (see Note 3)
Zero flag output for L–channel/no assignment (see Note 3)
Mode control data Input. (see Note 2)
MC
I
Mode control clock input. (see Note 2)
MS
I
Chip Select for Mode control. (see Note 2)
PSCK
I
System clock input. (PCM) (see Note 1)
DSCK
I
System clock input. (DSD) (see Note 1)
DBCK
I
Audio data bit clock input. (DSD) (see Note 1)
NOTES: 1. Schmitt trigger input, 5-V tolerant.
2. Schmitt trigger input with internal pulldown, 5-V tolerant.
3. Usage depending on AZRO register setting.
†
absolute maximum ratings
Supply voltage, V
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
DD
CC
Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (6.5 V + 0.3 V)
Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
electrical characteristics, T = 25°C, V
= 3.3 V, V
= 5 V (unless otherwise noted)
CC
A
DD
In PCM mode, f = 44.1 kHz, system clock = 256 f , 24-bit data
S
S
In DSD mode, f = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data
S
DSD1702E
PARAMETERS
TEST CONDITIONS
UNITS
MIN
TYP
MAX
Resolution
24
Bits
DATA FORMAT
PCM MODE
2
Audio data interface format
Standard, I S, left justified
16-, 18-, 20-, 24-bits
selectable
Audio data bit length
Audio data format
MSB First, 2s Complement
kHz
f
s
Sampling frequency
10
200
128f , 192f , 256f , 384f ,
s
s
s
s
System clock frequency
512f , 768f
s
s
DSD MODE
Audio data interface format
Audio data bit length
Direct stream digital (DSD)
1-Bit
f
s
Sampling frequency
f = 44.1 kHz
s
64f
s
Hz
System clock frequency
f = 44.1 kHz
s
256f , 384f , 512f , 768f
kHz
s
s
s
s
Digital Input/OUTPUT
Logic Family
TTL Compatible
V
V
2.0
IH
Input logic level
Input logic current
Output logic level
VDC
µA
0.8
10
IL
(4)
I
I
I
I
V
V
V
V
= V
IH
IN
DD
= 0 V
= V
(4)
–10
100
–10
IL
IN
(5)
65
IH
IN
DD
(5)
= 0 V
IL
IN
(6)
(6)
V
V
I
I
= –2 mA
= 2 mA
2.4
OH
OH
VDC
1.0
OL
OL
NOTES: 4. Pins 1, 2, 3, 4, 5, 18, 19, 20: DSDL, DSDR, PBCK, PDATA, PLRCK, PSCK, DSCK, DBCK.
5. Pins 15, 16, 17: MD, MC, MS.
6. Pins 13, 14: ZEROR, ZEROL.
4
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
electrical characteristics, T = 25°C, V
= 3.3 V, V = 5 V (unless otherwise noted) (continued)
CC
A
DD
In PCM mode, f = 44.1 kHz, system clock = 256f , 24-bit data
s
s
In DSD mode, f = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data
s
DSD1702E
PARAMETERS
TEST CONDITIONS
UNITS
MIN
TYP
MAX
(7)
Dynamic Performance
PCM MODE
f = 44.1 kHz
s
0.0015% 0.002%
f = 96 kHz
s
0.0020%
0.0025%
106
THD+N at V
OUT
= 0 dB
f = 192 kHz
s
EIAJ, A-Weighted,
A-Weighted,
f = 44.1 kHz
s
103
103
100
f = 96 kHz
s
106
Dynamic range
dB
dB
f = 192 kHz
s
105
EIAJ, A-Weighted,
A-Weighted,
f = 44.1 kHz
s
106
(8)
f = 96 kHz
s
106
Signal-to-noise ratio
f = 192 kHz
s
105
f = 44.1 kHz
s
103
f = 96 kHz
s
103
Channel separation
Level linearity error
dB
dB
f = 192 kHz
s
102
V
OUT
= –90 dB
±0.5
DSD MODE (at f = 64 × 44.1 kHz)
s
THD+N
Dynamic range
V
= 0 dB, EIAJ
0.0015%
106
OUT
EIAJ, A-Weighted
EIAJ, A-Weighted
dB
dB
dB
dB
Signal–to–noise ratio
Channel separation
Level linearity error
DC Accuracy
106
103
V
OUT
= –90 dB
±0.5
Gain error
±1.0
±1.0
±30
±6.0 %/FSR
±3.0 %/FSR
Gain mismatch, channel-to-channel
Bipolar zero error
Analog Output
V
OUT
= 0.5 V
at BPZ
±60
mV
CC
Output voltage
Center voltage
Full scale (–0dB)
62%/V
V
(PP)
VDC
CC
50%/V
CC
Load impedance
Digital Filter Performance
8x Interpolation Filter
Sharp roll off Filter
Passband
AC load
5
kΩ
±0.02 dB
–3 dB
0.454f
s
Passband
0.487f
s
Stopband
0.546f
s
Passband ripple
± 0.02
dB
dB
Stopband Attenuation
Stopband = 0.546f
– 60
s
NOTES: 7. Analog performance specs are measured by audio precision system 2 under averaging mode.
8. SNR is tested at infinite zero detection OFF.
5
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
electrical characteristics, T = 25°C, V
= 3.3 V, V
= 5 V (unless otherwise noted) (continued)
A
DD
CC
In PCM mode, f = 44.1 kHz, system clock = 256f , 24-bit data
s
s
In DSD mode, f = 2.8224 MHz (= 64 × 44.1 kHz), system clock = 256 × 44.1 kHz, 1-bit data
s
DSD1702E
PARAMETERS
TEST CONDITIONS
UNITS
MIN
TYP
MAX
Digital Filter Performance
Slow Rolloff Filter
–0.5 dB
0.308f
0.432f
s
Passband
–3 dB
s
Stopband
0.832f
s
Passband ripple
Stopband attenuation
Delay time
0.308 f
0.832 f
±0.5
dB
dB
s
s
s
–58
23/f
s
De-Emphasis Filter
PCM mode only
De-Emphasis error
At f = 32, 44.1 or 48 kHz
s
±0.1
dB
DSD Filter
Filter–1
Passband
At –3 dB
50
kHz
dB
Stopband attenuation
At 100 kHz
–18
Filter–2
Filter–3
Passband
At –3 dB
70
kHz
dB
Stopband attenuation
At 100 kHz
–9.8
Passband
At –3 dB
60
kHz
dB
Stopband attenuation
At 100 kHz
–17
Internal Analog Filter Performance
At 20 kHz
At 44 kHz
At 50 kHz
At 100 kHz
–0.02
–0.1
Frequency response
dB
–0.12
–0.5
Power Supply Requirements
V
3.0
4.5
3.3
5
3.6
5.5
14
DD
CC
Voltage range
VDC
mA
V
f = 44.1 kHz
s
10
23
17
8.5
9
f = 192 kHz
s
I
DD
DSD mode
Supply current
f = 44.1 kHz
s
13
I
CC
f = 192 kHz
s
f = 44.1 kHz
76
120
111
s
Power dissipation
mW
f = 192 kHz
s
Temperature Range
Operation temperature
Thermal resistance
–25
85
°C
θ
20-pin QSOP
98
°C/W
JA
6
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
system clock and reset functions
system clock input
The DSD1702 requires a system clock for operating the digital interpolation filter, digital DSD filter and multilevel
delta-sigma modulator. The system clock is applied to PSCK (pin 18) in PCM mode and to DSCK (pin 19) in
DSD mode. When CKCE (control register 20, B7) is not set to 1, the system clock is also applied to PSCK in
DSD mode. The DSD1702 has a system clock detection circuit. Table I shows examples of system clock
frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Burr-Brown’s PLL1700 multiclock generator is an excellent
choice for providing the DSD1702 system clock.
In PCM mode, the over sampling rate of digital filter is 4 times when a 128f and 192f system clock is applied
S
s
to DSD1702. When a 256f , 384f , 512f and 768f is applied, the over sampling rate is eight times.
s
s
s
s
power-on reset functions
The DSD1702 includes a power-on reset function. Figure 1 shows the operation of this function. With
> 2 V, the power-on reset function will be enabled. The initialization sequence requires 1024 system clocks
V
DD
from the time V
> 2 V as shown in Figure 2. After the initialization period, the DSD1702 will be set to its reset
DD
default state, as described in the mode control register section of this data sheet.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
SCLK
) (MH )
Z
SAMPLING
FREQUENCY
MODE
128f
192f
256f
384f
512f
768f
s
s
s
s
s
s
16kHz
32kHz
2.048
4.096
5.6488
6.144
11.2896
12.288
24.576
—
3.072
6.144
8.4672
9.216
16.9344
16.84
36.864
—
4.096
8.192
6.144
8.192
16.384
12.288
24.576
12.288
16.9344
18.432
44.1kHz
48kHz
11.2896
12.288
22.5792
24.576
33.8688
36.864
PCM
DSD
88.2kHz
96kHz
22.5792
24.576
33.8688
36.864
45.1584
49.152
67.7376
73.728
192kHz
64x44.1kHz
See Note 9
11.2896
See Note 9
16.9344
See Note 9
22.5792
See Note 9
33.8688
NOTE 9: This system clock is not supported for the given sampling frequency.
t
SCKH
H
L
2 V
System Clock
0.8 V
t
SCKL
System Clock Pulse
Cycle Time
System Clock Pulse Width High
System Clock Pulse Width Low
t
t
5 ns (min)
5 ns (min)
SCKH
SCKL
Figure 1. System Clock Input Timing
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
system clock and reset functions (continued)
2.4 V
V
DD
2 V
1.6 V
Reset
Reset Remove
Internal Reset
1024 System Clocks
System Clock
Figure 2. Power-On Reset Timing
audio serial interface
The DSD1702 has two audio serial interface ports: PCM audio interface port and DSD audio interface port.
In PCM mode, the audio interface is a 3-wire serial port. It includes PLRCK (pin 5), PBCK (pin 3), and PDATA
(pin 4). PBCK is the serial audio bit clock, and it is used to clock the serial data present on PDATA into the serial
shift register of the audio interface. Serial data is clocked into the DSD1702 on the rising edge of PBCK. PLRCK
is the serial audio left/right word clock. It is used to latch serial data into the internal registers of the serial audio
interface.
DSD1702 requires the synchronization of PLRCK and system clock, but does not need a specific phase relation
between PLRCK and system clock.
If the relationship between PLRCK and system clock changes more than ±6 PBCK, internal operation is
initialized within 1/f and analog outputs are forced into 0.5 V
system clock is completed.
until re-synchronization between PLRCK and
s
CC
In DSD mode, the audio interface port is also a 3-wire serial connection. DBCK (pin 20) is the serial audio bit
clock, and it is used to clock the individual direct stream digital (= DSD) audio data on DSDL (pin 1) and DSDR
(pin 2). DSD data is clocked into the DSD1702 on the rising edge of DBCK. DBCK must be synchronous with
the system clock, but does not require a specific phase relation to it. DBCK is operated at the DSD sampling
frequency, nominally 64 × 44.1kHz.
audio data formats and timing
2
In PCM mode, the DSD1702 supports industry-standard audio data formats, including standard, I S, and
left-justified. The data formats are shown in Figures 3 and 4. Data formats are selected using the format bits,
FMT[2:0], in control register 20. The default data format is 24-bit standard format. All formats require binary 2s
complement, MSB-first audio data. Figure 5 shows a detailed timing diagram for the serial audio interface.
In DSD mode, the DSD1702 supports a DSD audio data format. The data formats are shown in FIGURE 5. The
data formats are selected automatically when DSD bit in control register 22 is set. Figure 6 shows a detailed
timing diagram for the DSD audio data interface.
serial control interface
The serial control interface is a 3-wire serial port which operates completely asynchronously to the serial audio
interface. The serial control interface is utilized to program the on-chip mode registers. The control interface
includes MD (pin 15), MC (pin 16), and MS (pin 17). MD is the serial data input, used to program the mode
registers. MC is the serial bit clock, used to shift data into the control port. MS is the chip select for control port.
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
system clock and reset functions (continued)
(1) STD Format: L-ch = H, R-ch = L
T = 1/f
s
PLRCK
L – ch
R – ch
PBCK
(a) Data Word = 16 Bit
PDATA 14 15 16
PDATA 16 17 18
PDATA 18 19 20
PDATA 22 23 24
1
2
15 16
LSB
1
2
15 16
17 18
19 20
23 24
(b) Data Word = 18 Bit
MSB
1
2
17 18
19 20
23 24
1 2
(c) Data Word = 20 Bit
(d) Data Word = 24 Bit
1
2
1 2
1
2
1 2
(2) IIS Format: L-ch = L, R-ch = H; Data Word = 24 Bit
L – ch
R – ch
PLRCK
PBCK
1
2
23 24
1
2
23 24
1
PDATA
(3) Left Justified Format: L-ch = H, R-ch = L; Data Word = 24 Bit
PLRCK
PBCK
L – ch
R – ch
PDATA
1
2
24
1
2
24
1
24
Figure 3. PCM Data Format
T = 1/(64 × 44.1 kHz)
DBCK
DSDL
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
DSDR
Figure 4. Normal Data Output Form From DSD Decoder
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
system clock and reset functions (continued)
PARAMETERS
MIN
70
30
30
10
10
10
10
MAX
UNIT
ns
t
t
t
t
t
t
t
BCK pulse cycle time
BCK high level time
BCY
BCH
BCL
BL
ns
BCK low level time
ns
BCK rising edge to LRCK edge
LRCK falling edge to BCK
Rising edge DIN set up time
DIN hold time
ns
ns
LB
ns
DS
ns
DH
50% of V
PLRCK
DD
t
t
t
LB
BCH
BCL
50% of V
PBCK
DD
t
BL
t
BCY
50% of V
PDATA
DD
t
DS
t
DH
Figure 5. Timing for PCM Audio Interface
PARAMETERS
MIN
MAX
UNIT
MHz
ns
†
2.8224
t
t
t
t
t
BCK pulse cycle time
BCY
BCH
BCL
DS
BCK high level time
BCK low level time
DIN set up time
DIN hold time
30
30
10
10
ns
ns
ns
DH
†
2.8224 MHz = 64 x 44.1 kHz, This value is specified as a sampling rate of DSD.
t
t
BCL
BCH
50% of V
50% of V
DBCK
DD
t
t
BL
BCY
DSDL
DSDR
DD
t
DS
t
DH
Figure 6. Timing for DSD Audio Interface
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
register write operation
All write operations for the serial control port use 16-bit data words. Figure 7 shows the control data word format.
The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (or
address). The least significant eight bits, D[7:0], contain the data to be written to the register specified by
IDX[6:0].
Figure8showsthefunctionaltimingdiagramfortheserialcontrolport. MSisheldatalogic1stateuntilaregister
needs to be written. To start the register write cycle, MS is set to logic 0. Sixteen clocks are then provided on
MC, corresponding to the 16 bits of the control data word on MD. After the sixteenth clock cycle has completed,
the data is latched into the indexed mode control register. To write the next data, MS must be set to 1 once.
control interface timing requirements
Figure 9 shows a detailed timing diagram for the serial control interface. These timing parameters are critical
for proper control port operation.
MSB
0
LSB
D0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7
Register Index (or Address)
D6
D5
D4
D3
D2
D1
Register Data
Figure 7. Control Data Word Format MD
MS
MC
X
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7
D6
D5
D4
D3
D2
D1
D0
X
X
0
IDX6
MD
Figure 8. Register Write Operation
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
control interface timing requirements (continued)
t
MHH
50% of V
DD
ML
t
MLS
t
t
t
MLH
MCH
MCL
50% of V
50% of V
MC
MD
DD
DD
t
MCY
LSB
t
t
MDH
MDS
PARAMETERS
MIN
100
40
MAX
UNIT
ns
t
t
t
t
t
t
t
t
MC pulse cycle time
MCY
MCL
MCH
MHH
MSS
MSH
MDH
MDS
MC low level time
MC high level time
MS high level time
ns
40
ns
80
ns
MS fall edge to MC rise edge
15
ns
†
MS hold time
15
ns
MD hold time
15
ns
MD set-up time
15
ns
†
MC rise edge for LSB to MS rise edge
Figure 9. Control Interface Timing
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
mode control registers
user-programmable mode controls
The DSD1702 includes a number of user programmable functions that are accessed via control registers. The
registers are programmed using the serial control Interface as previously discussed in this data sheet. Table
2 lists the available mode control functions, along with their reset default conditions and associated register
index.
Table 2. User-Programmable Mode Controls
FUNCTION
Digital attenuation control, 0dB to –infinity in 0.5dB steps
Soft mute control
RESET DEFAULT
0 dB, no attenuation
Mute disabled
REGISTER
BIT(S)
AT1[7:0], AT2[7:0]
MUT[2:0]
INZD
PCM DSD
16 and 17
18
√
√
√
√
√
√
√
√
√
√
√
√
√
Infinite zero detect mute
Disabled
18
Oversampling rate control (64f or 128f )
64f oversampling
s
18
OVER
s
s
DAC operation control
DAC1 and DAC2 enabled
De-emphasis disabled
44.1 kHz
19
DAC[2:1]
DEM
√
De-emphasis function control
19
De-emphasis sample rate select
Audio data format control
Roll-off control for 8x digital filter
Clock select control
19
DMF[1:0]
FMT[2:0]
FLT
24-Bit standard format
Sharp roll-off
20
20
Disabled
20
CKCE
√
√
√
√
System reset
Not operated
PCM mode
22
SRST
DSD mode control
22
DSD
DSD filter select
Filter-1
22
DFLT[1:0]
AZRO
Zero flag output pin select
Output phase select
L/R flags separately
Normal phase
High
22
√
√
√
22
DREV
√
Zero flag polarity select
22
ZREV
register map
The mode control register map is shown in Table 3. Each register includes an index (or address) indicated by
the IDX[6:0] bits.
Table 3. Mode Control Register Map
REGISTER D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register 16
Register 17
Register 18
Register 19
Register 20
Register 21
Register 22
0
0
0
0
0
0
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
AT17
AT27
RSV
RSV
AT16
AT26
OVER
AT15
AT25
RSV
AT14
AT24
INZD
DEM
RSV
RSV
AT13
AT23
RSV
RSV
RSV
RSV
AT12
AT22
RSV
RSV
AT11
AT21
AT10
AT20
MUT2 MUT1
DAC2 DAC1
DMF1 DMF0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 CKCE
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
FLT
RSV
RSV
REV
RSV
DSD
FMT2 FMT1 FMT0
RSV RSV RSV
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST
DFLT1 DFLT0 AZRO ZREV DREV
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
mode control registers (continued)
register definitions
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
Register 17
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20
ATx[7:0] Digital Attenuation Level Setting
:PCM/DSD Mode
Where x = 1 or 2, corresponding to the DAC output V
L (x = 1) and V
R (x = 2).
OUT
OUT
In PCM mode, default value : 1111 1111 , 0 dB.
B
Each DAC channel (V
L and V
R) includes a digital attenuation function. The attenuation level may be
OUT
OUT
set from 0 dB to –119.5 dB and –infinity in 0.5 dB steps in PCM mode and 6 dB to –113.5 dB and –infinity in DSD
mode. Alternatively, the attenuation level may be set to infinite attenuation (or mute). A 6dB gain difference is
applied between PCM mode and DSD mode to compensate for the 0.5 maximum modulation index of DSD
signals.
The following table shows attenuation levels for various settings:
ATx[7:0]
DECIMAL VALUE
ATTENUATION LEVEL SETTING
PCM Mode
DSD Mode
1111 1111B
1111 1110B
1111 1101B
:
255
254
253
:
0 dB, No Attenuation. (default)
6 dB
5.5 dB
5 dB
–0.5 dB
–1 dB
:
:
1111 0011B
1111 0010B
:
243
242
:
–6 dB
–6.5 dB
:
0 dB
–0.5 dB
:
1000 0011B
1000 0010B
1000 0001B
1000 0000B
:
131
130
129
128
:
–62 dB
–62.5 dB
–63 dB
–63.5 dB
:
–56 dB
–56.5 dB
–57 dB
–57.5 dB
:
0111 0101B
:
117
:
–69 dB
:
–63 dB
:
0001 0000B
0000 1111B
:
16
15
:
–119.5 dB
–infinity
:
–113.5 dB
–infinity
:
0000 0000B
0
–infinity
–infinity
IDX[6:0] Register Index
Register 16: 10000
Register 17: 10001
B
B
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
register definitions (continued)
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 18
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV OVER RSV INZD RSV RSV MUT2 MUT1
MUTx Soft Mute Control
:PCM/DSD Mode
Where, x = 1 or 2, corresponding to the DAC output V
Default value: 0
L (x = 1) and V
R (x = 2).
OUT
OUT
MUTx = 0
MUTx = 1
Mute disabled (default)
Mute enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the soft mute function for the corresponding DAC
outputs, V L and V R. The soft mute function is incorporated into the digital attenuators. When mute is
OUT
OUT
disabled (MUTx = 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx = 1,
the digital attenuator for the corresponding output will be decreased from the current setting to infinite
attenuation, one attenuator step (0.5 dB) at a time. This provides pop-free muting of the DAC output.
By setting MUTx = 0, the attenuator will be incremented one step at a time to the previously programmed
attenuation level.
INZD Infinite Zero Detect Mute Control
:PCM Mode
Default value: 0
INZD = 0
INZD = 1
Infinite zero detect mute disabled (default)
Infinite zero detect mute disabled (default)
The INZD bit is used to enable or disable the zero detect mute function described in the zero flag and infinite
zero detect mute section in this data sheet. The zero detect mute function is independent of the zero flag output
operation, so enabling or disabling the INZD bit has no effect on the zero flag outputs (ZEROL and ZEROR).
OVER Oversampling Rate Control
:PCM Mode
Default value: 0
OVER = 0
OVER = 1
64x Oversampling for system clock ≥ 256f , and 32x Oversampling for system clock < 256 f . (default)
s s
128x Oversampling for system clock ≥ 256f , and 64x Oversampling for system clock < 256 f .
s
s
Sets the oversampling rate of the delta-sigma D/A converters. The OVER = 1 setting is recommended when
the system clock is 128 f or 192 f .
s
s
RSV Reserved Bit
The RSV should be set to 0.
IDX[6:0] Register Index
Register 18: 10010
B
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
register definitions (continued)
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 19 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV DMF1 DMF0 DEM RSV RSV DAC2 DAC1
DACx DAC Operation Control
Where x = 1 or 2, corresponding to the DAC output V
Default value: 0
:PCM/DSD Mode
L (x = 1) or V
R (x = 2).
OUT
OUT
DACx = 0
DACx = 0
DAC operation enabled (default)
DAC operation disabled
The DAC operation controls are used to enable and disable the DAC outputs, V
DACx = 0, the corresponding output will generate the audio waveform dictated by the data present on the DATA
L and V
R. When
OUT
OUT
pin. When DACx = 1, the corresponding output will be set to the bipolar zero level, or V /2.
CC
DME De-emphasis Function Control
:PCM Mode
Default value: 0
DME = 0
DME = 1
De-emphasis disabled (default)
De-emphasis enabled
The DME bit is used to enable or disable the digital de-emphasis function. Refer to the plots shown in the Typical
Characteristics section of this data sheet.
DMF[1:0] Sampling Frequency Select for the De-emphasis Function
:PCM Mode
Default value: 00
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when
it is enabled.
DMF[1:0]
De-emphasis Sample Rate Select
00
01
10
11
44.1 kHz (default)
48 kHz
32 kHz
Reserved
RSV Reserved Bit
The RSV should be set to 0.
IDX[6:0] Register Index
Register 19: 10011
B
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
register definitions (continued)
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 20
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 CKCE FLT RSV RSV RSV FMT2 FMT1 FMT0
FMT[2:0] Audio Interface Data Format
:PCM Mode
Default value: 00
The FMT[2:0] bits are used to select the data format for the serial audio interface. The table below shows the
available format options.
FMT[2:0]
000
Audio Data Format Select
24-Bit standard format, right-justified data (default)
20-Bit standard format, right-justified data
18-Bit standard format, right-justified data
16-Bit standard format, right-justified data
001
010
011
2
100
I S format, 24 bits
101
Left-justified format, 24 bits
Reserved
110
111
Reserved
FLT Digital Filter Roll-Off Control
:PCM Mode
Default value: 0
FLT = 0
FLT = 1
Sharp rolloff (default)
Slow rolloff
The FLT bit allows the user to select the digital filter rolloff that is best suited to their application. Sharp and slow
filter rolloffs are available. The response curves for filter selections are shown in the Typical Characteristics
section of this data sheet.
CKCE Clock Select Control
:DSD Mode
Default value: 0
CKCE = 0
CKCE = 1
System clock is applied to PSCK in DSD mode(default)
System clock is applied to DSCK in DSD mode
The CKCE bit selects system clock source in DSD mode. (PSCK or DSCK)
The CKCE bit must be set before to set DSD to 1.
RSV Reserved Bit
The RSV should be set to 0.
IDX[6:0] Register Index
Register 20: 10100
B
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
register definitions (continued)
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 21
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV
RSV
RSV RSV RSV RSV
RSV
RSV
User cannot write register 21. All RSV bits [B7:B0] must be set to 0.
IDX[6:0] Register Index
Register 21: 10101
B
B15
0
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 22
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 SRST RSV DSD DFLT1 DFLT0 AZRO ZREV DREV
DREV Output Phase Select
:PCM/DSD Mode
Default value: 0
DREV = 0
DREV = 1
Normal output (default)
Inverted output
The DREV bit is output analog signal phase control.
ZREV Zero Flag Polarity Select
Default value: 0
:PCM Mode
ZREV = 0
ZREV = 1
Zero flag pins HIGH at a zero detect (default)
Zero flag pins LOW at a zero detect
The ZREV bit allows the user to select the polarity of zero flag pins.
AZRO Zero Flag Output Pin Select
Default value: 0
:PCM Mode
AZRO = 0
WhenZREV=0, ZEROLandZERORpinofeachchannelgoestoHIGHwheneachchanneliscontinuously
zero data. (default)
When ZREV=1, ZEROL and ZEROR pin of each channel goes to LOW when each channel is continuously
zero data.
AZRO = 1
When ZREV=0, ZEROR pin goes to HIGH when both L and R channels are continuously zero at the same
time. ZEROL pin stays in LOW state.
When ZREV=1, ZEROR pin goes to LOW when both L and R channels are continuously zero at the same
time. ZEROL pin stays in LOW state.
The AZRO bit allows the user to select output form of zero flag pins.
DFLT[1:0] DSD Filter Select
:DSD Mode
Default value: 0
DFLT[1:0]
DSD Filter Select
Filter-1 (default
Filter-2
00
01
10
11
Filter-3
Reserved
The DFLT[1:0] bits allow the user to select the DSD filter from three kind of filters.
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
:PCM/DSD Mode
register definitions (continued)
DSD DSD Mode Control
Default value: 0
DSD = 0
DSD = 1
PCM mode (default)
DSD mode
The DSD bit allows the user to control the operation mode, PCM mode and DSD mode.
SRST System Reset
:PCM/DSD Mode
Default value: 0
SRST = 0
SRST = 1
Not operated (default)
DAC system is reset once
The SRST bit allows the user to reset DAC system. This function is same as the power on reset.
RSV Reserved Bit
The RSV should be set to 0.
IDX[6:0] Register Index
Register 22: 10110
B
analog outputs
The DSD1702 includes two independent output channels, V
L and V
R. These are unbalanced outputs,
OUT
OUT
each capable of driving 3.1 V
typical into a 10-kΩ ac-coupled load. The internal output amplifiers for V
L
(pp)
OUT
and V
R are biased to the dc common-mode (or bipolar zero) voltage, equal to V
/ 2.
OUT
CC
The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy
present at the DAC outputs due to the noise shaping characteristics of the delta-sigma D/A converters. The
frequency response of this filter is shown in Figure 10. By itself, this filter may not be enough to attenuate the
out-of-band noise to an acceptable level for many applications. An external low-pass filter is recommended to
provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the
Applications Information section of this data sheet.
ANALOG FILTER PERFORMANCE (100 Hz – 10 MHz)
10
0
–10
–20
–30
–40
–50
–60
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
Figure 10. Output Filter Frequency Response
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
zero flags and zero detect mute functions
The DSD1702 includes circuitry for detecting an all 0 data condition for the PCM audio data input pin. This
includes two independent functions: zero output flags and zero detect mute. Although the flag and mute
functions are independent of one another, the zero detection mechanism is common to both functions.
zero detect condition
Zero detection for each output channel is independent from the other.
In PCM mode, if the data for a given channel remains at a 0 level for 1024 sample periods (or PLRCK clock
periods), a zero detect condition exists for that channel.
In DSD mode, the zero detection is not available.
zero output flags
Given that a zero detect condition exists for one or more channels, the zero flag pins for those channels will be
set to a logic 1 state. There are zero flag pins for each channel, ZEROL (pin 14) and ZEROR (pin 13). These
pins can be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal
processor, or other digitally-controlled circuit.
The active polarity of zero flag outputs can be inverted by setting the ZREV bit of control register 22 to 1. The
reset default is active high output, or ZREV = 0.
infinite zero detect mute
Infinitezerodetectmuteisaninternallogicfunction. ThisfunctionisavailableinPCMmodeonly. Thezerodetect
mute can be enabled or disabled using the INZD bit of control register 18. The reset default is zero detect mute
disabled, INZD = 0. If the input data on L- and R-channels is countinuously and simultaneously zero for 1024
clocks of LRCK, the zero mute circuitry will immediately force the corresponding DAC output(s) to the bipolar
zero level, or 0.5V
.
CC
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
SCKO
BCK
DSD
Decoder
1
2
3
4
20
SDOL
DSDL
DBCK
19
SDOR
SCKO
DSCK
PSCK
DSDR
PBCK
PDATA
18
17
BCKO
SDO
PCM
Decoder
MS
WCK
5
6
16
15
From SIO Portion MCU
PLRCK
DGND
MC
MD
10 µF 0.1 µF
14
13
7
8
V
3.3 V
5 V
ZEROL
ZEROR
DD
Mute Control
V
V
V
CC
9
12
11
L
V
COM
OUT
10 µF
10
0.1 µF
10 µF
AGND
R
OUT
L-Channel Out
R-Channel Out
Post LPF
Post LPF
Figure 11. Basic Connection Diagram
connection diagrams
A basic connection diagram is shown in Figure 11, with the necessary power supply bypassing and decoupling
components.
The use of series terminating resistors (22 Ω to 100 Ω) fitted close to the signal source is recommended for the
xSCK, PLRCK, xBCK, DATA, DSDx inputs. The series resistor combines with the stray PCB and device input
capacitance to form a low-pass filter which reduces high frequency noise emissions and helps to dampen
glitches and ringing present on clock and data lines.
power supplies and grounding
The DSD1702 requires a 5-V analog supply and a 3.3-V digital supply. The 5-V supply is used to power the DAC
analog and output filter circuitry, while the 3.3-V supply is used to power the digital filter and serial interface
circuitry. For best performance, the 3.3-V digital supply should be derived from the 5-V supply by using a linear
regulator. Burr-Brown’s REG1117-3.3 is an ideal choice for this application.
Proper power supply bypassing is shown in Figure 12. The 10-µF capacitors should be tantalum or aluminum
electrolytic, while the 0.1-µF capacitors are ceramic (X7R type is recommended for surface-mount
applications).
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
APPLICATION INFORMATION
D/A output filter circuits: post low-pass filter
The DSD1702 requires a third or second-order analog low-pass filter to achieve the frequency response
recommended by SACD standard and reduce the out-of-band noise both produced by the DSD1702
delta-sigma modulator and inherent in the DSD modulated input signal.
Figure 12 shows the recommended external low-pass filter circuit. This circuit is a 3rd order Butterworth filter
using the Sallen-Key circuit arrangement. The filter response and corner frequency are determined by the
frequency response recommended by SACD standard. The table in Figure 12 lists the standard resistor and
capacitor values corresponding with the DSD digital filter on DSD1702. This filter can be used in PCM and DSD
modes.
C2
DSD Filter
R1
R2
R3
R4
R5
C1
C2
C3
2.7 kΩ
6.8 kΩ
15 kΩ
10 kΩ
10 kΩ
1500 pF
680 pF
100 pF
R1
R2
R3
C3
+
_
C1
R5
R4
Figure 12. Post Low-Pass Filter Circuit
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
digital filter—PCM mode
x8 interpolation filter (de-emphasis off)
AMPLITUDE
AMPLITUDE
vs
vs
FREQUENCY RESPONSE (SHARP ROLL-OFF)
FREQUENCY RESPONSE (SLOW ROLL-OFF)
0
0
–20
–20
–40
–60
–80
–40
–60
–80
–100
–120
–100
–120
0
1
2
3
4
0
1
2
3
4
f – Frequency – Hz
f – Frequency – Hz
Figure 14
Figure 13
AMPLITUDE
vs
FREQUENCY RESPONSE (SLOW ROLL-OFF)
AMPLITUDE
vs
PASSBAND RIPPLE FREQUENCY (SHARP ROLL-OFF)
0.05
2
1
0.04
0.03
0.02
0.01
0
–1
0
–2
–0.01
–0.02
–0.03
–0.04
–0.05
–3
–4
–5
0
0.1
0.2
0.3
0.4
0.5
0
0.1
0.2
0.3
0.4
0.5
f – Frequency – Hz
f – Frequency – Hz
Figure 15
Figure 16
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
digital filter—PCM mode (continued)
de-emphasis curves
LEVEL
vs
ERROR
vs
FREQUENCY DE-EMPHASIS (f = 32 kHz)
s
FREQUENCY DE-EMPHASIS (f = 32 kHz)
s
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–10
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
f – Frequency – kHz
f – Frequency – kHz
Figure 17
Figure 18
LEVEL
vs
ERROR
vs
FREQUENCY DE-EMPHASIS (f = 44.1 kHz)
s
FREQUENCY DE-EMPHASIS (f = 44.1 kHz)
s
0
–1
–2
–3
–4
–5
–6
–7
–8
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–9
–10
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f – Frequency – kHz
f – Frequency – kHz
Figure 19
Figure 20
24
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
digital filter—PCM mode (continued)
de-emphasis curves
LEVEL
vs
ERROR
vs
FREQUENCY DE-EMPHASIS (f = 48 kHz)
FREQUENCY DE-EMPHASIS (f = 48 kHz)
s
s
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
f – Frequency – kHz
f – Frequency – kHz
Figure 21
Figure 22
digital filter—DSD mode
DSD MODE AMPLITUDE
vs
INTERNAL DIGITAL FILTER FREQUENCY
5
Filter 3
0
Filter 1
–5
Filter 2
–10
–15
–20
–25
–30
–35
1
10
100
1000
f – Frequency – kHz
Figure 23
25
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
analog dynamic performance
supply voltage characteristics
TOTAL HARMONIC DISTORTION PLUS NOISE
DYNAMIC RANGE
vs
SUPPLY VOLTAGE
vs
SUPPLY VOLTAGE
0.01
110
108
4.4 kHz
106
104
102
100
98
96 kHz
192 kHz
96 kHz
192 kHz
44 kHz
0.001
4
4.5
5
5.5
6
4
4.5
5
5.5
6
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
Figure 24
Figure 25
SIGNAL TO NOISE RATIO
vs
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
110
108
106
104
102
100
98
110
108
106
104
102
100
98
44.1 kHz
192 kHz
96 kHz
44.1 kHz
96 kHz
192 kHz
4.5
V
5.5
– Supply Voltage – V
4
5
6
4
4.5
V
5
5.5
6
– Supply Voltage – V
CC
CC
Figure 26
Figure 27
26
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
analog dynamic performance (continued)
temperature characteristics
TOTAL HARMONIC DISTORTION PLUS NOISE
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
vs
FREE-AIR TEMPERATURE
0.01
110
108
106
104
102
100
98
44.1 kHz
96 kHz
192 kHz
96 kHz
192 kHz
44.1 kHz
50 75
0.001
–50
–25
0
25
100
–50
–25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 28
Figure 29
SIGNAL TO NOISE NOISE
vs
FREE-AIR TEMPERATURE
110
108
106
104
102
100
44.1 kHz
96 kHz
192 kHz
98
–50
–25
0
25
50
75
100
T
A
– Free-Air Temperature – °C
Figure 30
27
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