INA116UA-TR [BB]
Instrumentation Amplifier, 1 Func, 10000uV Offset-Max, 0.8MHz Band Width, PDSO16,;
| 型号： | INA116UA-TR |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Instrumentation Amplifier, 1 Func, 10000uV Offset-Max, 0.8MHz Band Width, PDSO16, 仪表放大器 |
| 文件： | 总9页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
INA116
INA116
INA116
Ultra Low Input Bias Current
INSTRUMENTATION AMPLIFIER
DESCRIPTION
FEATURES
The INA116 is a complete monolithic FET-input instru-
mentation amplifier with extremely low input bias
current. Difet® inputs and special guarding techniques
yield input bias currents of 3fA at 25°C, and only 25fA
at 85°C. Its 3-op amp topology allows gains to be set
from 1 to 1000 by connecting a single external resistor.
● LOW INPUT BIAS CURRENT: 3fA typ
● BUFFERED GUARD DRIVE PINS
● LOW OFFSET VOLTAGE: 2mV max
● HIGH COMMON-MODE REJECTION:
84dB (G = 10)
● LOW QUIESCENT CURRENT: 1mA
Guard pins adjacent to both input connections can be
used to drive circuit board and input cable guards to
maintain extremely low input bias current.
● INPUT OVER-VOLTAGE PROTECTION: ±40V
The INA116 is available in 16-pin plastic DIP and SOL-16
surface-mount packages, specified for the –40°C to +85°C
temperature range.
APPLICATIONS
● LABORATORY INSTRUMENTATION
● pH MEASUREMENT
● ION–SPECIFIC PROBES
● LEAKAGE CURRENT MEASUREMENT
V+
13
2
Guard
INA116
–
VIN
3
Over-Voltage
Protection
+1
A1
50kΩ
RG
4
1
G = 1 +
Guard
60kΩ
60kΩ
25kΩ
25kΩ
A3
VO
RG
11
9
16
5
Guard
A2
Ref
+
VIN
6
7
Over-Voltage
Protection
60kΩ
60kΩ
+1
Guard
8
V–
Difet®; Burr-Brown Corporation
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
©1994 Burr-Brown Corporation
PDS-1242B
Printed in U.S.A. May, 1995
SPECIFICATIONS
AT TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
INA116P, U
TYP
INA116PA, UA
TYP
PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
UNITS
INPUT
Offset Voltage, RTI
Initial
vs Temperature
vs Power Supply
Long-Term Stability
Bias Current
vs Temperature
Offset Current
vs Temperature
Impedance, Differential
Common-Mode
Common-Mode Voltage Range
T
A = +25°C
±0.5 ±0.5/G
See Typical Curve
±10 ±15/G
±1 ±5/G
±2 ±2/G
±50 ±100/G
±25
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
±5 ±5/G
±100 ±200/G
±100
mV
TA = TMIN to TMAX
VS = ±4.5V to ±18V
µV/V
µV/mo
fA
±3
See Typical Curve
±1
See Typical Curve
>1015/0.2
±25
±100
fA
Ω/pF
Ω/pF
V
V
V
>1015/7
(V+)–2
(V–)+2.4
(V+)–4
(V–)+4
±40
✻
✻
✻
Safe Input Voltage
Common-Mode Rejection
VCM = ±11V, ∆RS = 1kΩ
G = 1
G = 10
G = 100
CM = ±5V, G = 1000
80
84
86
86
89
92
94
94
73
78
80
80
✻
✻
✻
✻
dB
dB
dB
dB
V
NOISE
Voltage Noise, RTI
f = 1kHz
G = 1000, RS = 0Ω
28
2
✻
✻
nV/√Hz
µVp-p
fB = 0.1Hz to 10Hz
Current Noise
f = 1kHz
0.1
✻
✻
fA/√Hz
GAIN
Gain Equation
Range of Gain
Gain Error
1+(50kΩ/RG)
V/V
V/V
%
%
%
1
1000
±0.05
±0.4
✻
✻
0.1
±0.5
±0.7
G = 1
G = 10
G = 100
G = 1000
G = 1
±0.01
±0.25
±0.35
±1.25
±5
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
±0.5
%
Gain vs Temperature(1)
50kΩ Resistance(1)(2)
Nonlinearity
±10
±100
±0.005
±0.005
±0.005
±20
ppm/°C
ppm/°C
% of FSR
% of FSR
% of FSR
% of FSR
±25
±100
±0.01
±0.01
±0.01
G = 1
G = 10
G = 100
G = 1000
±0.0005
±0.001
±0.001
±0.005
GUARD OUTPUTS
Offset Voltage
Output Impedance
Current Drive
±15
650
+2/–0.05
±50
✻
✻
✻
✻
mV
Ω
mA
OUTPUT
Voltage Positive
Negative
Load Capacitance Stability
Short-Circuit Current
RL = 10kΩ
RL = 10kΩ
(V+) –1
(V–) +0.35
(V+) –0.7
(V–) +0.2
1000
✻
✻
✻
✻
✻
✻
V
V
pF
mA
+5/–12
FREQUENCY RESPONSE
Bandwidth, –3dB
G = 1
G = 10
G = 100
800
500
70
7
0.8
22
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
kHz
kHz
kHz
kHz
V/µs
µs
µs
µs
µs
µs
G = 1000
Slew Rate
Settling Time, 0.01%
G = 10 to 200
10V Step, G = 1
G = 10
G = 100
G = 1000
50% Overdrive
25
145
400
20
Output Overload Recovery
POWER SUPPLY
Voltage Range
Current
±4.5
±15
±1
±18
±1.4
✻
✻
✻
✻
✻
V
mA
VIN = 0V
TEMPERATURE RANGE
Specification
Operating
–40
–40
85
125
✻
✻
✻
✻
°C
°C
θJA
80
✻
°C/W
✻ Specification same as INA116P
NOTE: (1) Guaranteed by wafer test. (2) Temperature coefficient of the “50kΩ” term in the gain equation.
®
2
INA116
PIN CONFIGURATION
ELECTROSTATIC
DISCHARGE SENSITIVITY
Top View
DIP
SOL-16
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
RG
Guard –
VI–N
1
2
3
4
5
6
7
8
16 RG
15 NC
14 NC
13 V+
12 NC
11 VO
10 NC
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
Guard –
Guard +
VI+N
Guard +
V–
PACKAGE INFORMATION
9
Ref
PACKAGE DRAWING
PRODUCT
PACKAGE
NUMBER(1)
NC: No Internal Connection.
INA116PA
INA116P
INA116UA
INA116U
16-Pin Plastic DIP
16-Pin Plastic DIP
SOL-16 Surface-Mount
SOL-16 Surface-Mount
180
180
211
211
ABSOLUTE MAXIMUM RATINGS
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Supply Voltage .................................................................................. ±18V
Input Voltage Range .......................................................................... ±40V
Output Short-Circuit (to ground) .............................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –40°C to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
INA116
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
COMMON-MODE REJECTION vs FREQUENCY
G = 1000V/V
GAIN vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
60
G = 1000
50
G = 100V/V
40
G = 100
30
G = 10V/V
G = 1V/V
20
G = 10
10
0
G = 1
–10
–20
10
100
1k
10k
100k
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
NEGATIVE POWER SUPPLY REJECTION
vs FREQUENCY
POSITIVE POWER SUPPLY REJECTION
vs FREQUENCY
120
100
80
60
40
20
0
120
100
80
60
40
20
0
G = 1k
G = 1000V/V
G = 100V/V
G = 10 < 100
G = 1
G = 10V/V
G = 1V/V
1k
1
10
100
1k
10k
100k
1
10
100
Frequency (Hz)
10k
100k
Frequency (Hz)
INPUT BIAS CURRENT vs INPUT VOLTAGE
INPUT BIAS CURRENT vs TEMPERATURE
15
10
5
1000
100
10
0
IOS
IB
–5
–10
–15
Measurement Limit
75 100
1
–15
–10
–5
0
5
10
15
–75
–50
–25
0
25
50
125
Input Voltage (V)
®
4
INA116
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
INPUT COMMON-MODE RANGE
vs OUTPUT VOLTAGE
INPUT REFERRED NOISE vs FREQUENCY
15
10
5
10k
1k
G ≥ 10
G ≥ 10
G = 1
VD/2
G = 1
G = 1V/V
+15V
–
VO
+
–
INA116
0
VD/2
Ref
+
G = 1
VCM
–5
–10
–15
100
10
–15V
G = 1
G = 1000V/V
G = 10V/V
Bandwidth Limit
1k
–15
–10
–5
0
5
10
15
1
10
100
Frequency (Hz)
10k
Output Voltage (V)
INPUT OVER-VOLTAGE V/I CHARACTERISTICS
OFFSET VOLTAGE WARM-UP
4
3
15
10
5
G ≥ 10
2
G = 1
G = 1000V/V
G = 1V/V
1
0
0
–1
–2
–3
–4
G = 1V/V
–5
–10
–15
G = 1000V/V
G = 1
G ≥ 10
–40
–30
–20
–10
0
10
20
30
40
0
5
10
15
20
25
Input Voltage (V)
Time After Power Supply Turn-On (s)
INPUT OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
QUIESCENT CURRENT AND SLEW RATE
vs TEMPERATURE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
40
26
G = 100
19
1.4
0.5
7
9
6
5
IQ
0.5
1.2
1.0
0.8
0.6
0.4
38
24
15
20
18
G = 10
G = 1
2
9
1
4
1
SR
17
0
14
20
12
0.5
4
3
2
0.5
–80 –60 –40 –20
40
60
80
–75
–50
–25
0
25
50
75
100
125
Offset Voltage Drift (µV/°C)
Temperature (°C)
®
5
INA116
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
VOLTAGE NOISE, 0.1 TO 10Hz
INPUT-REFERRED, G ≥ 100
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
32
G = 10, 100
28
G = 1
24
20
16
G = 1000
12
8
4
0
100
1k
10k
100k
1M
1s/div
Frequency (Hz)
SMALL SIGNAL RESPONSE
SMALL SIGNAL RESPONSE
G=1
G=100
20mV/div
20mV/div
G=10
G=1000
10µs/div
100µs/div
LARGE SIGNAL RESPONSE
LARGE SIGNAL RESPONSE
G=1
G=100
5V/div
5V/div
G=10
G=1000
100µs/div
100µs/div
®
6
INA116
The 50kΩ term in equation 1 is the sum of the two feedback
resistors of A1 and A2. These on-chip metal film resistors are
laser trimmed to accurate absolute values. The accuracy and
temperature coefficient of these resistors are included in the
gain accuracy and drift specifications of the INA116.
APPLICATIONS INFORMATION
Figure 1 shows the connections required for basic operation
of the INA116. Applications with noisy or high impedance
power supplies may require decoupling capacitors close to
the supply pins as shown.
The stability and temperature drift of RG also affect gain.
RG’s contribution to gain accuracy and drift can be directly
inferred from the gain equation (1). Low resistor values
required for high gain make wiring resistance important.
Sockets add to the wiring resistance that will contribute
additional gain error in gains of approximately 100 or
greater.
The output is referred to the output reference (Ref) terminal
which is normally grounded. This must be a low impedance
connection to assure good common-mode rejection. A resis-
tance of 30Ω in series with this connection will cause a
typical device to degrade to approximately 72dB CMR at
G = 1.
SETTING THE GAIN
OFFSET TRIMMING
Gain of the INA116 is set by connecting a single external
resistor, RG, as shown. The gain is—
The INA116 is laser trimmed for low offset voltage and
offset voltage drift; most applications require no external
offset adjustment. Figure 2 shows an optional circuit for
trimming the output offset voltage. A voltage applied to the
Ref terminal is summed at the output. Op amp A1 provides
a low source impedance for the Ref terminal, assuring good
common-mode rejection.
50kΩ
G = 1+
(1)
RG
Commonly used gains and resistor values are shown in
Figure 1.
V+
0.1µF
13
4
INA116
3
Over-Voltage
Protection
VI–N
+1
A1
50kΩ
RG
2
1
G = 1 +
R1
60kΩ
R2
60kΩ
RFB
25kΩ
Input Guards
See Text.
A3
VO
RG
11
16
5
RFB
25kΩ
Ref
A2
6
7
Over-Voltage
Protection
9
VI+N
R3
60kΩ
R4
60kΩ
+1
8
0.1µF
DESIRED
GAIN
RG
(Ω)
NEAREST 1% RG
V–
(Ω)
1
2
5
10
20
50
100
200
500
1000
2000
5000
10000
NC
NC
49.9k
12.4k
5.62k
2.61k
1.02k
511
249
100
49.9
24.9
10
50.00k
12.50k
5.556k
2.632k
1.02k
505.1
251.3
100.2
50.05
25.01
10.00
5.001
Also drawn in simplified form:
–
VIN
INA116
Ref
VO
RG
+
VIN
4.99
NC: No Connection.
FIGURE 1. Basic Connections.
®
7
INA116
CIRCUIT BOARD LAYOUT AND ASSEMBLY
Careful circuit board layout and assembly techniques are
required to achieve the exceptionally low input bias current
performance of the INA116. Guard terminals adjacent to
both inputs make it easy to properly guard the critical input
terminal layout. Since traces are not required to run between
device pins, this layout is easily accomplished, even with the
surface mount package. The guards should completely en-
circle their respective input connections—see Figure 4. Both
sides of the circuit board should be guarded, even if only one
side has an input terminal conductor. Route any time-
varying signals away from the input terminals. Solder mask
should not cover the input and guard traces since this can
increase leakage.
–
VIN
V+
VO
INA116
RG
100µA
1/2 REF200
+
Ref
VIN
100Ω(1)
100Ω(1)
OPA131
±10mV
Adjustment Range
10kΩ(1)
100µA
1/2 REF200
NOTE: (1) For wider trim range required
in high gains, scale resistor values larger
V–
FIGURE 2. Optional Trimming of Output Offset Voltage.
INPUT BIAS CURRENT RETURN PATH
Input circuitry must provide an input bias current path for
proper operation. Figure 3 shows resistors R1 and R2 to
provide an input current path. Without these resistors, the
inputs would eventually float to a potential that exceeds the
common-mode range of the INA116 and the input amplifiers
would saturate. Because of its exceedingly low input bias
current, improperly biased inputs may operate normally for
a period of time after power is first applied, or operate
intermittently.
Guard Top and
Bottom of Circuit Board.
FIGURE 4. Circuit Board Guard Layout.
After assembly, the circuit board should be cleaned. Com-
mercial solvents should be chosen according to the soldering
method and flux used. Solvents should be cleaned and
replaced often. Solvent cleaning should be followed by a de-
ionized water rinse and 85°C bake out.
Crystal or
Ceramic
Transducer
INA116
VO
Sockets can be used, but select and evaluate them carefully
for best results. Use caution when installing the INA116 in
a socket. Careless handling can contaminate the plastic near
the input pins, dramatically increasing leakage current.
100MΩ
R1
100MΩ
R2
A proven low leakage current assembly method is to bend
the input pins outward so they do not contact the circuit
board. Input connections are made in air and soldered
directly to the input pin. This technique is often not practical
or production-worthy. It is, however, a useful technique for
evaluation and testing and provides a benchmark with which
to compare other wiring techniques. The circuit board guard-
ing techniques discussed normally reduce leakage to accept-
able levels.
Polarizing
Voltage
100MΩ
Capacitive
Sensor
INA116
A solid mechanical assembly is required for good results.
Nearby plastic parts can be especially troublesome since a
static charge can develop and the slightest motion or vibra-
tion will couple charge to the inputs. Place a Faraday shield
around the whole amplifier and input connection assembly
to eliminate stray fields.
VO
100MΩ
R1
100MΩ
R2
100MΩ
FIGURE 3. Providing An Input Bias Current Path.
®
8
INA116
INPUT CONNECTIONS
potential and ground the outer shield. Two separate guarded
lines are required if both the inverting and non-inverting
inputs are brought to the source.
Some applications must make high impedance input connec-
tions to external sensors or input connectors. To assure low
leakage, the input should be guarded all the way to the signal
source—see Figure 5. Coaxial cable can be used with the
shield driven by the guard. A separate connection is required
to provide a ground reference at the signal source. Triaxial
cable may reduce noise pickup and provides the ground
reference at the source. Drive the inner shield at guard
The guard drive output current is limited to approximately
+2mA/–50µA. For slow input signals the internal guard
output can directly drive a cable shield. With fast input
signals, however, the guard may not provide sufficient
output current to rapidly charge the cable capacitance. An op
amp buffer may be required as shown in Figure 6.
High-Z
Source
Two coaxial cables and ground
VI–N
VI+N
V
1MΩ
High-Z
Source
Two triaxial cables
VI–N
VI+N
V
1MΩ
FIGURE 5. Input Cable Guarding Circuits.
+15
Circuit Board
Guard
Cable
13
3
1
VIN
G = 10
11
150Ω
INA116
VO
5.62kΩ
16
6
9
Op amp buffer helps
OPA131
8
guard cables with
fast input signals—
see text.
–15
FIGURE 6. Buffered Guard Drive.
Solution
Ground
Sample
Electrode
Reference
Electrode
FIGURE 7. pH or Ion Measurement System.
®
9
INA116
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