PCM1702 [BB]

BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER; BiCMOS高级注册幅度20位数字 - 模拟转换器


型号：	PCM1702
厂家：	BURR-BROWN CORPORATION
描述：	BiCMOS Advanced Sign Magnitude 20-Bit DIGITAL-TO-ANALOG CONVERTER BiCMOS高级注册幅度20位数字 - 模拟转换器转换器
文件：	总8页 (文件大小：131K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

49%

FPO

PCM1702P

PCM1702U

BiCMOS Advanced Sign Magnitude 20-Bit

DIGITAL-TO-ANALOG CONVERTER

FEATURES

DESCRIPTION

● ULTRA LOW –96dB max THD+N

The PCM1702 is a precision 20-bit digital-to-analog

converter with ultra-low distortion (–96dB typ with a

full scale output). Incorporated into the PCM1702 is

an advanced sign magnitude architecture that elimi-

nates unwanted glitches and other nonlinearities around

bipolar zero. The PCM1702 also features a very low

noise (120dB typ SNR: A-weighted method) and fast

settling current output (200ns typ, 1.2mA step) which

is capable of 16X oversampling rates.

(No External Adjustment Required)

● NEAR-IDEAL LOW LEVEL OPERATION

● GLITCH-FREE OUTPUT

● 120dB SNR TYP (A-Weight Method)

● INDUSTRY STD SERIAL INPUT FORMAT

● FAST (200ns) CURRENT OUTPUT

(±1.2mA)

Applications include very low distortion frequency

synthesis and high-end consumer and professional

digital audio applications.

● CAPABLE OF 16X OVERSAMPLING

● COMPLETE WITH REFERENCE

● LOW POWER (150mW typ)

Clock

Data

Input Shift Register

and Control Logic

Balanced Current

Segment DAC A

DCOM

ACOM

+V_CC

Balanced Current

I_OUT

Segment DAC B

Reference

and

–V_CC

Servo

Bipolar Offset

BPO DC

RF DC SERV DC

International Airport Industrial Park

•

Mailing Address: PO Box 11400

•

Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd.

• Tucson, AZ 85706

Tel: (520) 746-1111

•

Twx: 910-952-1111

•

Cable: BBRCORP

•

Telex: 066-6491

•

FAX: (520) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1175B

Printed in U.S.A. June, 1995

PCM1702

SPECIFICATIONS

All specifications at 25°C, ±V_CCand +V_DD= ±5V unless otherwise noted.

PCM1702P/U, -J, -K

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

Bits

RESOLUTION

DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight

110

DIGITAL INPUT

Logic Family

Logic Level: V_IH

V_IL

TTL/CMOS Compatible

+2.4

+V_DD

0.8

I_IH

I_IL

V_IH= +V_DD

V_IL= 0V

±10

µA

Data Format

Serial, MSB First, BTC⁽¹⁾

12.5

Input Clock Frequency

20.0

MHz

TOTAL HARMONIC DISTORTION + N⁽²⁾

P/U

V_O= 0dB

f_S= 352.8kHz⁽³⁾, f = 1002Hz⁽⁴⁾

–92

–82

–46

–96

–83

–48

–100

–84

–50

–88

–74

–40

–92

–76

–42

–96

–80

–44

_O= –20dB

_O= –60dB

_O= 0dB

_O= –20dB

_O= –60dB

_O= 0dB

P/U, -J

P/U, -K

_O= –20dB

_O= –60dB

ACCURACY

Level Linearity

Gain Error

At –90dB Signal Level

±0.5

±0.25

±25

±5

±3

Bipolar Zero Error⁽⁵⁾

Gain Drift

0°C to 70°C

ppm of FSR/°C

minute

Bipolar Zero Drift

Warm-up Time

IDLE CHANNEL SNR⁽⁶⁾

Bipolar Zero, A-weighted Filter

110

120

ANALOG OUTPUT

Output Range

Output Impedance

Settling Time

±1.2

1.0

200

kΩ

(±0.003% of FSR, 1.2mA Step)

Glitch Energy

No Glitch Around Zero

POWER SUPPLY REQUIREMENTS

Supply Voltage Range: +V_CC= +V_DD

–V_CC= –V_DD

Combined Supply Current: +I_CC

Combined Supply Current: –I_CC

Power Dissipation

+4.75

–4.75

+5.00

–5.00

+5.00

–25.00

150

+5.25

–5.25

+9.0

–41.0

250

+V_CC= +V_DD= +5V

–V_CC= –V_DD= –5V

±V_CC= ±V_DD= ±5V

TEMPERATURE RANGE

Operating

Storage

–25

–55

+85

+125

°C

NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (Distortion_RMS+ Noise_RMS) / Signal_RMS. (3) D/A converter sample frequency (8 x 44.1kHz; 8x oversampling).

(4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5kΩ feedback and an A-weighted filter.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes

no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change

without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant

any BURR-BROWN product for use in life support devices and/or systems.

PCM1702

ABSOLUTE MAXIMUM RATINGS (DIP Package)

ABSOLUTE MAXIMUM RATINGS (SOP Package)

PowerSupply Voltage .................................................................. ±6.5VDC

Input Logic Voltage ........................................... DGND—0.3V~+V_DD+0.3V

Operating Temperature..................................................... –25°C to +85°C

Storage Temperature ...................................................... –55°C to +125°C

Power Dissipation .......................................................................... 500mW

Lead Temperature (soldering, 10s) .................................................. 260°C

Power Supply Voltage .................................................................. ±6.5VDC

Input Logic Voltage ........................................... DGND—0.3V~+V_DD+0.3V

Operating Temperature..................................................... –25°C to +85°C

Storage Temperature ...................................................... –55°C to +125°C

Power Dissipation .......................................................................... 300mW

Lead Temperature (soldering, 5s) .................................................... 260°C

PIN ASSIGNMENTS (DIP Package)

PIN ASSIGNMENTS (SOP Package)

MNEMONIC

DATA

CLOCK

+V_DD

DCOM

–V_DD

+V_CC

BPO DC

I_OUT

ACOM

SERV DC

REF DC

–V_CC

DATA

CLOCK

+V_DD

DCOM

–V_DD

+V_CC

BPO DC

I_OUT

ACOM

SERV DC

RFE DC

–V_CC

PACKAGE INFORMATION⁽¹⁾

PACKAGE DRAWING

NUMBER

GRADE MARKING (SOP Package)

MODEL

PACKAGE

MODEL

PACKAGE

PCM1702P

PCM1702U

16-Pin Plastic DIP

20-Pin Plastic SOP

180

248

PCM1702U

PCM1702U-J

PCM1702U-K

Marked PCM1702.

Marked with white dot by pin 10.

Marked with red dot by pin 10.

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

CONNECTION DIAGRAM

47µF

–5V V_CC

CLOCK

DATA

16 20

15 19

14 17

11 14

10 12

22µF

100µF

R_NF

+5V V_DD

V_OUT

47µF

+5V V_CC

–5V V_DD

47µF

13 16

12 15

= SOP

= DIP

PCM1702

TYPICAL PERFORMANCE CURVES

All specifications at 25°C, ±V_Aand ±V_D= ±5.0V unless otherwise noted.

16-BIT LEVEL LINEARITY

(Dithered Fade-to-Noise)

THD+N vs FREQUENCY

–40

–60dB

–60

–40dB

–80

–20dB

–2

–4

–6

–8

–100

0dB

–120

100

10k

–120

–110

–100

–90

–80

–70

–60

Output Frequency (Hz)

Output Signal Level (dB)

–90dB SIGNAL SPECTRUM

(100Hz Bandwidth)

16-BIT MONOTONICITY

1.5

–80

–100

–120

–140

–160

0.5

–0.5

–1

–1.5

8.83ms/div

12k

16k

20k

Frequency (Hz)

–90dB SIGNAL

–110dB SIGNAL

(10Hz to 20kHz Bandwidth)

200

100

–100

–200

–20

–40

400

800

1200

1600

2000

400

800

1200

1600

2000

Time (µs)

PCM1702

THEORY OF OPERATION

ADVANCED SIGN MAGNITUDE

DISCUSSION OF

SPECIFICATIONS

Digital audio systems have traditionally used laser-trimmed,

current-source DACs in order to achieve sufficient accuracy.

However, even the best of these suffer from potential low-

level nonlinearity due to errors at the major carry bipolar

zero transition. More recently, DACs employing a different

architecture which utilizes noise shaping techniques and

very high over-sampling frequencies, have been introduced

(“Bitstream”, “MASH”, or 1-bit DAC). These DACs over-

come the low level linearity problem, but only at the expense

of signal-to-noise performance, and often to the detriment of

channel separation and intermodulation distortion if the

succeeding circuitry is not carefully designed.

DYNAMIC SPECIFICATIONS

Total Harmonic Distortion + Noise

The key specifications for the PCM1702 is total harmonic

distortion plus noise (THD+N).

Digital data words are read into the PCM1702 at eight times

the standard compact disk audio sampling frequency of

44.1kHz (352.8kHz) so that a sine wave output of 1002Hz

is realized.

For production testing, the output of the DAC goes to an

I to V converter, then through a 40kHz low pass filter, and

then to a programmable gain amplifier to provide gain at

lower signal output test levels before being fed into an

analog-type distortion analyzer. Figure 1 shows a block

diagram of the production THD+N test setup.

The PCM1702 is a new solution to the problem. It combines

all the advantages of a conventional DAC (excellent full

scale performance, high signal-to-noise ratio and ease of

use) with superior low-level performance. Two DACs are

combined in a complementary arrangement to produce an

extremely linear output. The two DACs share a common

reference, and a common R-2R ladder for bit current sources

by dual balanced current segments to ensure perfect tracking

under all conditions. By interleaving the individual bits of

each DAC and employing precise laser trimming of resis-

tors, the highly accurate match required between DACs is

achieved.

For the audio bandwidth, THD+N of the PCM1702 is

essentially flat for all frequencies. The typical performance

curve, “THD+N vs Frequency”, shows four different output

signal levels: 0dB, –20dB, –40dB, and –60dB. The test

signals are derived from a special compact test disk (the

CBS CD-1). It is interesting to note that the –20dB signal

falls only about 10dB below the full scale signal instead of

the expected 20dB. This is primarily due to the superior low

level signal performance of the advanced sign magnitude

architecture of the PCM1702.

This new, complementary linear or advanced sign magni-

tude approach, which steps away from zero with small steps

in both directions, avoids any glitching or “large” linearity

errors and provides an absolute current output. The low level

performance of the PCM1702 is such that real 20-bit reso-

lution can be realized, especially around the critical bipolar

zero point.

In terms of signal measurement, THD+N is the ratio of

Distortion_RMS+ Noise_RMS/ Signal_RMSexpressed in dB. For the

PCM1702, THD+N is 100% tested at all three specified

output levels using the test setup shown in Figure 1. It is

significant to note that this test setup does not include any

output deglitching circuitry. All specifications are achieved

without the use of external deglitchers.

Table 1 shows the conversion made by the internal logic of

the PCM1702 from binary two’s complement (BTC). Also,

the resulting internal codes to the upper and lower DACs

(see front page block diagram) are listed. Notice that only

the LSB portions of either internal DAC are changing

around bipolar zero. This accounts for the superlative per-

formance of the PCM1702 in this area of operation.

Dynamic Range

Dynamic range in audio converters is specified as the mea-

sure of THD+N at an effective output signal level of –60dB

referred to 0dB. Resolution is commonly used as a theoreti-

cal measure of dynamic range, but it does not take into

account the effects of distortion and noise at low signal

levels. The advanced sign magnitude architecture of the

PCM1702, with its ideal performance around bipolar zero,

provides a more usable dynamic range, even using the strict

audio definition, than any previously available D/A con-

verter.

INPUT CODE

LOWER DAC CODE

UPPER DAC CODE

ANALOG OUTPUT

(20-bit Binary Two's Complement)

(19-bit Straight Binary)

+Full Scale

011...111

011...110

000...010

000...001

000...000

111...111

111...110

100...001

100...000

111...111+1LSB⁽¹⁾

111...111

111...110

000...010

000...001

000...000

+Full Scale –1LSB

Bipolar Zero +2LSB

Bipolar Zero +1LSB

Bipolar Zero

Bipolar Zero –1LSB

Bipolar Zero –2LSB

–Full Scale +LSB

–Full Scale

111...110

000...001

000...000

NOTE: (1) The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero.

TABLE I. Binary Two's Complement to Sign Magnitude Conversion Chart.

PCM1702

Use 400Hz High-Pass

Filter and 30kHz

Low-Pass Filter

Programmable

Gain Amp

0dB to 60dB

Low-Pass Filter

40kHz 3rd Order

GIC Type

Distortion

Analyzer

Meter Settings

(Shiba Soku Model

725 or Equivalent)

I to V

Converter

OPA627

DATA

Binary

Counter

Digital Code

(EPROM)

Parallel-to-Serial

Conversion

DUT

(PCM1702)

CLOCK

LE (Latch Enable)

Sampling Rate = 44.1kHz x 8(352.8kHz)

Output Frequency = 1002Hz

Timing

Logic

FIGURE 1. Production THD+N Test Setup.

Level Linearity

Monotonicity

Deviation from ideal versus actual signal level is sometimes

called “level linearity” in digital audio converter testing. See

the “–90dB Signal Spectrum” plot in the Typical Perfor-

mance Curves section for the power spectrum of a PCM1702

at a –90dB output level. (The “–90dB Signal” plot shows the

actual –90dB output of the DAC). The deviation from ideal

for PCM1702 at this signal level is typically less than

±0.3dB. For the “–110dB Signal” plot in the Typical Perfor-

mance Curves section, true 20-bit digital code is used to

generate a –110dB output signal.

Because of the unique advanced sign magnitude architecture

of the PCM1702, increasing values of digital input will

always result in increasing values of DAC output as the

signal moves away from bipolar zero in one-LSB steps (in

either direction). The “16-bit Monotonicity” plot in the

Typical Performance Curves section was generated using

16-bit digital code from a test compact disk. The test starts

with 10 periods of bipolar zero. Next are 10 periods of

alternating 1LSBs above and below zero, and then 10

periods of alternating 2LSBs above and below zero, and so

on until 10LSBs above and below zero are reached. The

signal pattern then begins again at bipolar zero.

This type of performance is possible only with the low-

noise, near-theoretical performance around bipolar zero of

the PCM1702 advanced sign magnitude.

With PCM1702, the low-noise steps are clearly defined and

increase in near-perfect proportion. This performance is

achieved without any external adjustments. By contrast,

sigma-delta (“Bit-stream”, “MASH”, or 1-bit DAC) archi-

tectures are too noisy to even see the first 3 or 4 bits change

(at 16 bits), other than by a change in the noise level.

A commonly tested digital audio parameter is the amount of

deviation from ideal of a 1kHz signal when its amplitude is

decreased form –60dB to –120dB. A digitally dithered input

signal is applied to reach effective output levels of

–120dB using only the available 16-bit code from a special

compact disk test input. See the “16-bit Level Linearity” plot

in the Typical Performance Curves section for the results of

a PCM1702 tested using this 16-bit dithered fade-to-noise

signal. Note the very small deviation from ideal as the signal

goes from –60dB to –100dB.

Absolute Linearity

Even though absolute integral and differential linearity specs

are not given for the PCM1702, the extremely low THD+N

performance is typically indicative of 17-bit integral linearity

in the DAC. The relationship between THD+N and linearity,

however, is not such that an absolute linearity specification

for every individual output code can be guaranteed.

DC SPECIFICATION

Offset, Gain, and Temperature Drift

Idle Channel SNR

Although the PCM1702 is primarily meant for use in dy-

namic applications, specifications are also given for more

traditional DC parameters such as gain error, bipolar zero

offset error, and temperature gain and offset drift.

Another appropriate specification for a digital audio con-

verter is idle channel signal-to-noise ratio (idle channel

SNR). This is the ratio of noise on the DAC output at bipolar

zero in relation to the full scale range of the DAC. To make

this measurement, the digital input is continuously fed the

code for bipolar zero, while the output of the DAC is band-

limited from 20Hz to 20kHz and an A-weighted filter is

applied. The idle channel SNR for the PCM1702 is typically

greater than 120dB, making it ideal for low-noise applica-

tions.

DIGITAL INPUT

Timing Considerations

The PCM1702 accepts TTL compatible logic input levels.

The data format of the PCM1702 is binary two’s comple-

ment (BTC) with the most significant bit (MSB) being first

PCM1702

in the serial input bit stream. Table II describes the exact

relationship of input data to voltage output coding. Any

number of bits can precede the 20 bits to be loaded, since

only the last 20 will be transferred to the parallel DAC

<PCM1702U>, LE) has gone low.

INSTALLATION

POWER SUPPLIES

Refer to CONNECTION DIAGRAM for proper connection

of the PCM1702. The PCM1702 only requires a ±5V sup-

ply. Both positive supplies should be tied together at a single

point. Similarly, both negative supplies should be connected

together. No real advantage is gained by using separate

analog and digital supplies. It is more important that both

these supplies be as “clean” as possible to reduce coupling

of supply noise to the output. Power supply decoupling

capacitors should be used at each supply pin to maximize

power supply rejection, as shown in CONNECTION DIA-

GRAM regardless of how good the supplies are. Both

commons should be connected to an analog ground plane as

close to the PCM1702 as possible.

All DAC serial input data (Pin1, DATA) bit transfers are

triggered on positive clock (Pin2, CLOCK), edges. The

serial-to-parallel data transfer to the DAC occurs on the

falling edge of Latch Enable. The change in the output of the

DAC occurs at a rising edge of the 4th clock of the CLOCK

after the falling edge of Latch Enable. Refer to Figure 2 for

graphical relationships of these signals.

Maximum Clock Rate

A typical clock rate of 16.9MHz for the PCM1702 is derived

by multiplying the standard audio sample rate of 44.1kHz by

sixteen times (16X over-sampling) the standard audio word

bit length of 24 bits (44.1kHz x 16 x 24 = 16.9MHz). Note

that this clock rate accommodates a 24-bit word length, even

though only 20 bits are actually being used. The setup and

hold timing relationships are shown in Figure 3.

FILTER CAPACITOR REQUIREMENTS

As shown in CONNECTION DIAGRAM, various size

decoupling capacitors can be used, with no special tolerances

being required. The size of the offset decoupling capacitor is

not critical either, with larger values (up to 100µF) giving

slightlybetterSNRreadings.Allcapacitorsshouldbeasclose

to the appropriate pins of the PCM1702 as possible to reduce

noise pickup from surrounding circuitry.

“Stopped Clock” Operation

The PCM1702 is normally operated with a continuous clock

input signal. If the clock is to be stopped between input data

words, the last 20 bits shifted in are not actually shifted from

the serial register to the latched parallel DAC register until

Latch Enable goes low. Latch Enable must remain low until

after the first clock cycle of the next data word to insure

proper DAC operation. In any case, the setup and hold times

for Data and LE must be observed as shown in Figure 3.

> 40ns

Data Input

LSB

MSB

> 15ns > 15ns

Clock

Input

> 20ns

DIGITAL INPUT

ANALOG OUTPUT

CURRENT OUTPUT

1,048,576LSBs

1LSB

7FFFF_HEX

00000_HEX

80000_HEX

Full Scale Range

+Full Scale

Bipolar Zero –1LSB

–Full Scale

2.40000000mA

2.28882054nA

–1.19999771mA

0.00000000mA

+1.20000000mA

> 15ns

Latch

Enable

> 15ns

> One Clock Cycle

TABLE II. Digital Input/Output Relationships.

FIGURE 3. Setup and Hold Timing Diagram.

Clock

DATA "N"

12 13 14 15 16 17 18 19 20

Data

MSB

LSB

Latch

Enable

I_OUT

N-1

NOTES : (1) If clock is stopped between input of 20-bit data words, "Latch" Enable (LE) must remain low until after the first clock cycle of the next 20-bit data

word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable

(LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative. (5)

I_OUTchanges on positive going edge of the 4th clock after negative going edge of Latch Enable (LE).

FIGURE 2. Timing Diagram.

PCM1702

FIGURE 4. Typical Application for Stereo Audio 8X Oversampling system.

PCM1702

PCM1702 [BB]

相关型号：

PCM1702-J

PCM1702-K

PCM1702P

PCM1702P-J

PCM1702P-JG4

PCM1702P-JG4

PCM1702P-K

PCM1702P/PCM1702U

PCM1702PG4

PCM1702P_07

PCM1702U

PCM1702U-J