PCM1728 [BB]
24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER; 24位， 96kHz的采样CMOS Δ-Σ立体声音频数位类比转换器
| 型号： | PCM1728 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | 24-Bit, 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总11页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
PCM1728
PCM1728
TM
24-Bit, 96kHz Sampling
CMOS Delta-Sigma Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
FEATURES
The PCM1728 is designed for mid- to high-grade
digital audio applications which achieve 96kHz sam-
pling rates with 24-bit audio data. PCM1728 uses a
newly developed, enhanced multi-level delta-sigma
modulator architecture that improves audio dynamic
performance and reduces jitter sensitivity in actual
applications. The internal digital filter operates at 8X
oversampling at a 96kHz sampling rate.
● ENHANCED MULTI-LEVEL DELTA-SIGMA DAC
● SAMPLING FREQUENCY (fS): 16kHz - 96kHz
● INPUT AUDIO DATA WORD:
16-, 20-, 24-Bit
● HIGH PERFORMANCE:
THD+N: –96dB
Dynamic Range: 106dB
The PCM1728 has superior audio dynamic perfor-
mance, 24-bit resolution, and 96kHz sampling, mak-
ing it ideal for mid- to high-grade audio applications
such as CD, DVD, and musical instruments.
SNR: 106dB
Analog Output Range: 0.62 x VCC (Vp-p)
● 8x OVERSAMPLING DIGITAL FILTER:
Stop Band Attenuation: –82dB
Passband Ripple: ±0.002dB
● MULTI FUNCTIONS:
Digital De-emphasis
Soft Mute
Zero Flag
● +5V SINGLE SUPPLY OPERATION
● SMALL 28-LEAD SSOP PACKAGE
VOUT
L
BCKIN
Serial
Low-pass
Filter
DAC
DAC
LRCIN
Input
I/F
EXTL
8X Oversampling
Digital Filter with
Function
Enhanced
Multi-level
Delta-Sigma
Modulator
DIN
Controller
VOUTR
Low-pass
Filter
I2S
EXTR
DM1
DM0
ZERO
Mode
Control
I/F
IW0
IW1
SCK
Open Drain
MUTE
RST
Crystal/OSC
XTO
Power Supply
XTI
CLKO
VCC1 AGND1 VDD DGND
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
• Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP
•
Telex: 066-6491
•
FAX: (520) 889-1510
•
Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-1453A
Printed in U.S.A. April, 1998
SPECIFICATIONS
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1728
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
24
Bits
DATA FORMAT
Audio Data Interface Format
Data Bit Length
Standard/I2S
16/20/24 Selectable
Audio Data Format
MSB-First, Two’s Binary Comp
Sampling Frequency (fS)
System Clock Frequency(1)
16
96
kHz
256/384/512/768fS
DIGITAL INPUT/OUTPUT LOGIC LEVEL
Input Logic Level
VIH
VIL
2.0
4.5
V
V
V
V
0.8
0.5
Output Logic Level (CLKO) VOH
VOL
IOH = 2mA
IOL = 4mA
CLKO PERFORMANCE(2)
Output Rise Time
Output Fall Time
20 ~ 80% VDD, 10pF
80 ~ 20% VDD, 10pF
10pF Load
5.5
4
37
ns
ns
%
Output Duty Cycle
DYNAMIC PERFORMANCE(3) (24-Bit Data)
THD+N
VO = 0dB
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
–97
–94
–42
–90
dB
dB
dB
VO = –60dB
Dynamic Range
fS =44.1kHz EIAJ A-weighted
fS = 96kHz A-weighted
fS =44.1kHz EIAJ A-weighted
fS = 96kHz A-weighted
fS = 44.1kHz
98
98
96
106
103
106
103
102
101
dB
dB
dB
dB
dB
dB
Signal-to-Noise Ratio
Channel Separation
fS = 96kHz
DYNAMIC PERFORMANCE(3) (16-Bit Data)
THD+N
VO = 0dB
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz EIAJ A-weighted
fS = 96kHz A-weighted
–94
–92
98
dB
dB
dB
dB
Dynamic Range
97
DC ACCURACY
Gain Error
Gain Mismatch: Channel-to-Channel
Bipolar Zero Error
±1.0
±1.0
±30
±3.0
±3.0
±60
% of FSR
% of FSR
mV
VO = 0.5VCC at Bipolar Zero
ANALOG OUTPUT
Output Voltage
Center Voltage
Full Scale (0dB)
AC Load
0.62 VCC
0.5 VCC
Vp-p
V
kΩ
Load Impedance
5
DIGITAL FILTER PERFORMANCE
Filter Characteristics
Passband
±0.002dB
–3dB
0.454fS
0.490fS
Stopband
0.546fS
Passband Ripple
Stopband Attenuation
±0.002
dB
dB
dB
sec
dB
Stop Band = 0.546fS
Stop Band = 0.567fS
–75
–82
Delay Time
De-emphasis Error
30/fS
±0.1
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
100
–0.16
kHz
dB
f = 20kHz
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current: ICC +IDD
VDD, VCC
fS = 44.1kHz
fS = 96kHz
fS = 44.1kHz
fS = 96kHz
4.5
5
32
45
160
225
5.5
45
VDC
mA
mA
mW
mW
Power Dissipation
225
TEMPERATURE RANGE
Operation
Storage
–25
–55
+85
+100
°C
°C
NOTES: (1) Refer section of system clock. (2) External buffer is recommended. (3) Dynamic performance specs are tested with 20kHz low pass filter and THD+N
specs are tested with 30kHz LPF, 400Hz HPF, Average Mode.
®
2
PCM1728
PIN CONFIGURATION
PIN ASSIGNMENTS
PIN NAME
I/O
DESCRIPTION
1
LRCIN
IN
Left and Right Clock Input. This clock is equal to
the sampling rate - fS.(1)
28 I2S
2
3
4
DIN
IN
IN
Serial Audio Data Input(1)
Bit Clock Input for Serial Audio Data.(1)
LRCIN
DIN
1
2
3
4
5
6
7
8
9
BCKIN
CLKO
27 DM1
26 DM0
25 MUTE
24 IW1
23 IW0
22 RST
21 ZERO
OUT
Buffered Output of Oscillator. Equivalent to
System Clock.
BCKIN
CLKO
XTI
5
6
7
8
9
XTI
XTO
DGND
VDD
IN
OUT
—
Oscillator Input (External Clock Input)
Oscillator Output
Digital Ground
—
Digital Power +5V
XTO
V
CC2R
—
Analog Power +5V
DGND
VDD
10 AGND2R
—
Analog Ground
PCM1728E
11
12
13
14
15
16
17
18
EXTR
NC
OUT
—
Rch, Common Pin of Analog Output Amp
No Connection
VCC2R
20
VCC2L
V
OUTR
AGND1
CC1
OUT
—
Rch, Analog Voltage Output of Audio Signal
Analog Ground
AGND2R 10
EXTR 11
NC 12
19 AGND2L
18 EXTL
17 NC
V
—
Analog Power +5V
VOUT
NC
L
OUT
—
Lch, Analog Voltage Output of Audio Signal
No Connection
EXTL
OUT
—
Lch, Common Pin of Analog Output Amp
Analog Ground
V
OUTR 13
16
15
V
OUTL
CC1
19 AGND2L
20
21
22
V
CC2L
—
Analog Power +5V
AGND1
14
V
ZERO
RST
OUT
IN
Zero Data Flag
Reset. When this pin is LOW, the DF and
modulators are held in reset.(2)
23
24
25
26
27
28
IW0
IW1
IN
IN
IN
IN
IN
IN
Input Format Selection(3)
Input Format Selection(3)
Mute Control
De-emphasis Selection 1(2)
De-emphasis Selection 2(2)
Input Format Selection(2)
PACKAGE INFORMATION
MUTE
DM0
DM1
I2S
PACKAGE DRAWING
NUMBER(1)
PRODUCT
PACKAGE
PCM1728E
28-Pin SSOP
324
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
NOTES: (1) Pins 1, 2, 3; Schmitt Trigger input. (2) Pins 22, 25, 26, 27, 28;
Schmitt Trigger input with pull-up resister. (3) Pins 23, 24; Schmitt Trigger
input with pull-down resister.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ...................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Input Current (except power supply) ............................................... ±10mA
Power Dissipation .......................................................................... 400mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s)................................................. +260°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
PCM1728
TYPICAL PERFORMANCE CURVES
All specifications at +25°C, +VCC = +VDD = +5V, fS = 44.1kHz, and 24-bit input data, SYSCLK = 384fS, unless otherwise noted.
THD+N vs SAMPLING FREQUENCY
(VCC = VDD = 5V, 24-Bit)
THD+N vs LEVEL
(fS = 44.1kHz)
88
91
–20
–30
–40
–50
–60
–70
–80
–90
–100
10
1
94
16-Bit
256fs
0.1
97
0.010
0.001
24-Bit
100
103
384fs
32
44.1
48
96
–60
–50
–40
–30
–20
–10
0
Sampling Frequency fS (kHz)
Amplitude (dB)
DYNAMIC RANGE vs SAMPLING FREQUENCY
(VCC = VDD = 5V, 24-Bit)
SNR vs SAMPLING FREQUENCY
(VCC = VDD = 5V, 24-Bit)
110
108
106
104
102
100
110
108
106
104
102
100
256/384fS
256/384fS
32
44.1
48
96
32
44.1
48
96
Sampling Frequency fS (kHz)
Sampling Frequency fS (kHz)
–60dB OUTPUT SPECTRUM
–60dB OUTPUT SPECTRUM
(f = 1kHz, fS = 44.1kHz, 16-Bit Data)
(f = 1kHz, fS = 44.1kHz, 24-Bit Data)
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
20
2
4
6
8
10
12
14
16
18
20
20
2
4
6
8
10
12
14
16
18
20
Frequency (Hz)
Frequency (Hz)
®
4
PCM1728
TYPICAL PERFORMANCE CURVES (CONT)
PASSBAND RIPPLE CHARACTERISTIC
OVERALL FREQUENCY CHARACTERISTIC
0
–20
0.003
0.002
0.001
0
–40
–60
–80
–100
–120
–140
–160
–0.001
–0.002
–0.003
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.1
0.2
0.3
0.4
0.5
Frequency (x fS)
Frequency (x fS)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
DE-EMPHASIS ERROR (fS = 32kHz)
0
–2
0.5
0.3
–4
0.1
–6
–8
–10
–0.1
–0.3
–0.5
0
0
0
2
4
6
8
10
12
14
0
0
0
2
4
6
8
10
12
14
Frequency (kHz)
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
DE-EMPHASIS ERROR (fS = 44.1kHz)
0
–2
–4
–6
–8
0.5
0.3
0.1
–0.1
–0.3
–0.5
–10
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
16
18
20
Frequency (kHz)
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
DE-EMPHASIS ERR0R (fS = 48kHz)
0
–2
–4
–6
–8
0.5
0.3
0.1
–0.1
–0.3
–0.5
–10
2
4
6
8
10 12 14 16 18 20 22
2
4
6
8
10 12 14 16 18 20 22
Frequency (kHz)
Frequency (kHz)
®
5
PCM1728
SYSTEM CLOCK
Typical input system clock frequencies to the PCM1728 are
shown in Table I, also, external input clock timing require-
ments are shown in Figure 2.
The system clock for PCM1728 must be either 256fS, 384fS,
512fS or 768fS, where fS is the audio sampling frequency
(typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768fS at
96kHz is not accepted.
The system clock can be either a crystal oscillator placed
between XTI (pin 5) and XTO (pin 6), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
tSCKH
“H”
2.0V
XTI
0.8V
“L”
tSCKL
PCM1728 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256fS ~
768fS. The system clock should be synchronized with LRCIN
(pin 1) clock. LRCIN (left-right clock) operates at the sam-
pling frequency fS. In the event these clocks are not synchro-
nized, PCM1728 can compensate for the phase difference
internally. If the phase difference between left-right and
system clocks is greater than 6-bit clocks (BCKIN), the
synchronization is performed internally. While the synchro-
nization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
System Clock Pulse Width High tSCKIH : 7ns MIN
System Clock Pulse Width Low tSCKIL : 7ns MIN
FIGURE 2. XTI Clock Timing.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1728 on pins 1, 2,
and 3, LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1728 can accept both standard, I2S,
and left justified data formats.
Figure 3 illustrates acceptable input data formats. Figure 4
shows required timing specification for digital audio data.
Externl Clock Input
Reset
4
5
6
CLKO
XTI
PCM1728 has both internal power-on reset circuit and the
RST pin (pin 22), which accepts an external forced reset by
RST = LOW. For internal power on reset, initialization is
done automatically at power on VDD >2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to VCC /2. Figure 5 illustrates
the timing of the internal power on reset.
System Clock
(256/384/
512/768fS)
XTO
PCM1728
PCM1728 accepts an external forced reset when RST = LOW.
When RST = LOW, the output of the DAC is invalid and the
analog outputs are forced to VCC/2 after internal initialization
(1024 system clocks count after RST = HIGH.) Figure 6
illustrates the timing of the RST pin.
Crystal Resonator Oscillation
System Clock
Buffer Out
4
5
6
CLKO
XTI
Buffer
C1
Zero Out (pin 21)
XTO
C2
XTAL
If the input data is continuously zero for 65536 cycles of
BCK, an internal FET is switched to “ON”. The drain of the
internal FET is the zero-pin, it will enable “wired-or” with
external circuit.
PCM1728
C1 C2 : 10pF ~ 30pF
FIGURE 1. System Clock Connection.
SYSTEM CLOCK FREQUENCY - MHz
SAMPLING RATE FREQUENCY (fS) - LRCIN
256fS
384fS
512fS
768fS
32kHz
44.1kHz
48kHz
8.1920
11.2896
12.2880
24.5760
12.2880
16.9340
18.4320
36.8640(1)
16.3840
22.5792
24.5760
49.1520(1)
24.5760
33.8688(1)
36.8640(1)
—
96kHz
NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz.
TABLE I. Typical System Clock Frequency.
®
6
PCM1728
1/fS
L_ch
R_ch
LRCIN (pin 1)
BCKIN (pin 3)
(1) 16-Bit Right Justified
DIN (pin 2)
14 15 16
14 15 16
14 15 16
1
3
2
3
1
3
2
3
MSB
LSB
MSB
LSB
(2) 20-Bit Right Justified
DIN (pin 2)
18 19 20
1
1
2
2
18 19 20
1
1
2
2
18 19 20
MSB
3
LSB
MSB
3
LSB
(3) 24-Bit Right Justified
DIN (pin 2)
23 24
22 23 24
22 23 24
MSB
LSB
MSB
LSB
(4) 24-Bit Left Justified
DIN (pin 2)
1
2
3
22 23 24
1
2
3
22 23 24
MSB
LSB
MSB
LSB
1/fS
L_ch
R_ch
LRCIN (pin 1)
BCKIN (pin 3)
(5) 16-Bit I2S
DIN (pin 2)
14 15 16
LSB
14 15 16
LSB
1
1
2
2
1
1
2
2
3
1
1
2
2
3
MSB
3
MSB
3
(6) 24-Bit I2S
DIN (pin 2)
22 23 24
22 23 24
LSB
MSB
LSB
MSB
FIGURE 3. Audio Data Input Formats.
LRCKIN
1.4V
1.4V
tBCH
tBCL
tLB
BCKIN
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
: tBCY
: tBCH
: tBCL
: 100ns (min)
: 50ns (min)
: 50ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
: 30ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
LRCIN Edge to BCKIN Rising Edge : tLB
DIN Set-up Time
DIN Hold Time
: tDS
: tDH
FIGURE 4. Audio Data Input Timing Specification.
®
7
PCM1728
VCC = VDD
Reset
Reset Removal
Internal Reset
XTI Clock
1024 system (= XTI) clocks
FIGURE 5. Internal Power-On Reset Timing.
RST
(1)
tRST
Reset
Reset Removal
Internal Reset
1024 system (XTI) clocks
XTI Clock
NOTE: (1) tRST = 20ns min.
FIGURE 6. External Forced Reset Timing.
SOFT MUTE
FUNCTIONAL DESCRIPTION
Soft Mute function can be controlled by MUTE (pin 25).
PCM1728 has several built-in functions including digital
input data format selection, soft mute, and digital de-empha-
sis. These functions are hardware controlled where static
control signals are used on pin 28 (I2S), pin 27 (DM1), pin 26
(DM0), pin 25 (MUTE), pin 24 (IW1), and pin23 (IW0).
MUTE (Pin 25)
SOFT MUTE
L
Mute ON
H
Mute OFF (Normal Operation)
TABLE III. Soft Mute Control.
DATA FORMAL SELECTION
PCM audio data format can be selected by pin 28 (I2S), pin
24 (IW1), and pin 23 (IW0), as shown in Table II.
DE-EMPHASIS CONTROL
De-emphasis control can be selected by DM1 (pin 27) and
DM0 (pin 26).
IW1
IW0
I2S
AUDIO INTERFACE
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
16-Bit Standard, Right-Justified
20-Bit Standard, Right-Justified
24-Bit Standard, Right-Justified
24-Bit Left-Justified, MSB-First
16-Bit I2S
DM1 (Pin 27)
DM0 (Pin 26)
DE-EMPHASIS
L
L
H
H
L
H
L
OFF
48kHz
44.1kHz
32kHz
H
24-Bit I2S
TABLE IV. De-emphasis Control.
Reserved
Reserved
TABLE II. Data Format Control.
®
8
PCM1728
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2-level) delta-sigma modulator.
THEORY OF OPERATION
The delta-sigma section of PCM1728 is based on an 8-level
amplitude quantizer and a 4th-order noise shaper. This
section converts the oversampled input data to 8-level delta-
sigma format.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8-times interpolation filter is 64fS for
all system clock ratios (256/384/512/768fS).
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 8. This
enhanced multi-level delta-sigma architecture also has ad-
vantages for input clock jitter sensitivity due to the multi-
level quantizer, simulated jitter sensitivity is shown in
Figure 9.
This newly developed, “Enhanced Multi-level Delta-Sigma”
architecture achieves high-grade audio dynamic performance
and sound quality.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 7. This 8-level delta-sigma modulator has
–
+
Z–1
Z–1
Z–1
Z–1
+
+
+
+
+
8-Level Quantizer
FIGURE 7. 8-Level Delta-Sigma Modulator.
CLOCK JITTER
125
120
115
110
105
100
95
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
90
85
80
0
100
200
300
400
500
600
0
1
2
3
4
5
6
7
8
Jitter (ps)
Frequency (fS)
FIGURE 8. Quantization Noise Spectrum.
FIGURE 9. Jitter Sensitivity.
®
9
PCM1728
APPLICATION
CONSIDERATIONS
DELAY TIME
1
0.5
0
There is a finite delay time in delta-sigma converters. In A/D
converters, this is commonly referred to as latency. For a
delta-sigma D/A converter, delay time is determined by the
order number of the FIR filter stage, and the chosen sampling
rate. The following equation expresses the delay time of
PCM1728:
–0.5
–1
TD = 30 x 1/fS
1
10
100
1k
10k
100k
For fS = 44.1kHz, TD = 30/44.1kHz = 680µs
Log Frequency (Hz)
Applications using data from a disc or tape source, such as
CD audio, DVD audio, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some profes-
sional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
FIGURE 10. Low Pass Filter Response.
20
0
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1728 using a 20kHz low pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
–20
–40
–60
–80
–100
1
10
100
1k
10k
100k
1M
10M
The performance of the internal low pass filter from DC to
40kHz is shown in Figure 10. The higher frequency roll-off
of the filter is shown in Figure 11. If the user’s application
has the PCM1728 driving a wideband amplifier, it is recom-
mended to use an external low pass filter.
Log Frequency (Hz)
FIGURE 11. Low Pass Filter Response.
BYPASSING POWER SUPPLIES
POWER SUPPLY
CONNECTIONS
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 12 for optimal values of bypass
capacitors.
PCM1728 has four power supply pin for digital (VDD), and
analog (VCC). Each connection also has a separate ground. If
the power supplies turn on at different times, there is a
possibility of a latch-up condition. To avoid this condition,
it is recommended to have a common connection between
the digital and analog power supplies. If separate supplies
are used without a common connection, the delta between
the two supplies during ramp-up time must be less than
0.1V.
®
10
PCM1728
PCM1728E
1
2
3
4
5
6
7
8
9
LRCIN
DIN
IIS 28
DM1 27
DM0 26
MUTE 25
IW1 24
PCM
Audio Data
Input
BCKIN
CLKO
XTI
Mode
Control
XTI Buffer Out
System Clock
(256/384/512/768fS)
XTO
IW0 23
To DGND of Digital Source
DGND
VDD
RST 22
ZERO 21
External Reset
C2
C4
10kΩ
VCC2R
VCC2L 20
C3
10 AGND2R
11 EXTR
12 NC
AGND2L 19
EXTL 18
NC 17
+
C6
10µF
C5
10µF
+
13
VOUTR
VOUTL 16
14 AGND1
VCC1 15
C1
+5V VCC
C1, C2 : 10µF + 0.1µF Ceramic
C3, C4 : 1µF ~ 10µF
Post
Low-Pass
Filter
Post
Low-Pass
Filter
Analog
Mute
Analog
Mute
External
Mute Control
Rch Audio Out
Lch Audio Out
FIGURE 12. Typical Circuit Connection Diagram.
®
11
PCM1728
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