PCM1730E/2K [TI]
24-BIT, 192-kHz SAMPLING ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER; 24 - BIT ， 192 - kHz的采样高级分段，音频立体声数字模拟转换器
| 型号： | PCM1730E/2K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24-BIT, 192-kHz SAMPLING ADVANCED SEGMENT, AUDIO STEREO DIGITAL-TO-ANALOG CONVERTER |
| 文件： | 总24页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCM1730
SLES021 – NOVEMBER 2001
24-BIT, 192-kHz SAMPLING ADVANCED SEGMENT, AUDIO
STEREO DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
D
24-Bit Resolution
D
D
D
D
D
D
D
A/V Receivers
D
Analog Performance (V
– Dynamic Range: 117 dB (Typically)
– SNR: 117 dB (Typically)
– THD+N: 0.0004% (Typically)
– Full-Scale Output (At Post Amp): 2.2-Vrms
= 5 V):
DVD Movie Players
SACD Player
CC
HDTV Receivers
Car Audio Systems
Digital Multi-Track Recorders
D
D
Differential Current Output: ±2.48 mA
Other Applications Requiring 24-Bit Audio
8× Oversampling Digital Filter:
– Stop-Band Attenuation: –82 dB
– Pass-Band Ripple: ±0.002 dB
DESCRIPTION
D
D
Sampling Frequency of 10 kHz to 200 kHz
The PCM1730 is a CMOS, monolithic integrated circuit
that includes stereo digital-to-analog converters and
support circuitry in a small 28-lead SSOP package. The
data converters utilize Texas Instruments’ advanced
segment DAC architecture to achieve excellent
dynamic performance and improved tolerance to clock
jitter. The PCM1730 provides balanced current outputs,
allowing the user to optimize analog performance
externally. Sampling rates up to 200 kHz are supported.
System Clock: 128, 192, 256, 384, 512, or
768 f With Auto Detect
S
Accepts 16-, 20-, and 24-Bit Audio Data
D
2
D
Data Formats: Standard, I S, and
Left-Justified
D
D
D
D
Digital De-Emphasis
Soft Mute
Zero Flags for Each Output
Dual Supply Operation:
– 5 V for Analog
– 3.3 V for Digital
D
D
5-V Tolerant Digital Inputs
Small 28-Lead SSOP Package
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER
OPERATING
TEMPERATURE RANGE
PACKAGE
MARKING
†
PRODUCT
PACKAGE
ORDERING NUMBER
PCM1730E
PCM1730E
28-Lead SSOP
28DB
–25°C to 85°C
PCM1730E
PCM1730E/2K
†
Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000
devices per reel). Ordering 2000 pieces of PCM1730E/2K will get a single 2000-piece tape and reel.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2001, Texas Instruments Incorporated
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PCM1730
SLES021 – NOVEMBER 2001
pin assignments
SSOP PACKAGE
(TOP VIEW)
1
28
RST
ZEROL
ZEROR
LRCK
DATA
BCK
SCKI
DGND
V
3
CC
2
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND2
3
I
I
L–
L+
OUT
4
OUT
5
V
V
V
2
1
CC
CC
6
7
3
COM
8
I
REF
9
V
V
V
2
1
DD
COM
10
11
12
13
14
DEMP0
DEMP1
FMT0
FMT1
FMT2
COM
AGND1
I
I
R+
R–
OUT
OUT
MUTE
functional block diagram
I
I
L+
OUT
LRCK
Current
Segment
DAC
Serial
Input
DATA
L–
OUT
BCK
I/F
V
COM
2
I/V and Filter
I
REF
Advanced
Segment
DAC
Bias
and
Vref
RST
Digital
Filter
V
1
3
COM
MUTE
FMT0
Modulator
V
COM
Function
Control
FMT1
FMT2
I/F
I
I
R–
OUT
DEMP0
DEMP1
Current
Segment
DAC
R+
OUT
System Clock
I/V and Filter
System Clock
Manager
SCKI
Zero Detect
Power Supply
2
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PCM1730
SLES021 – NOVEMBER 2001
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND1
AGND2
BCK
PIN
18
27
6
–
–
I
Analog ground
Analog ground
†
Bit clock input
†
DATA
5
I
Serial audio data input
‡
DEMP0
DEMP1
DGND
FMT0
10
11
8
I
De-emphasis control
De-emphasis control
Digital ground
‡
I
–
I
†
†
†
12
13
14
26
25
16
17
21
4
Audio data format select
Audio data format select
Audio data format select
FMT1
I
FMT2
I
I
I
I
I
I
L–
O
O
O
O
–
I
L-channel analog current output –
L-channel analog current output +
R-channel analog current output –
R-channel analog current output +
OUT
OUT
OUT
OUT
REF
L+
R–
R+
Output current reference bias pin. Connect a 16-kΩ resistor to GND.
†
Left and right clock (f )
S
LRCK
MUTE
RST
†
15
1
I
Analog output mute control
†
Reset
I
†
SCKI
7
I
System clock input
Analog supply, 5 V
Analog supply, 5 V
V
V
V
V
V
V
V
1
2
3
23
24
28
19
20
22
9
–
–
–
–
–
–
–
O
O
CC
CC
CC
Analog power supply, 5 V
1
2
3
Internal bias decoupling pin
Common voltage for I/V
Internal bias decoupling pin
Digital supply, 3.3 V
COM
COM
COM
DD
ZEROL
ZEROR
2
Zero flag for L-channel
Zero flag for R-channel
3
†
‡
Schmitt-trigger input, 5-V tolerant
Schmitt-trigger input with internal pulldown, 5-V tolerant
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PCM1730
SLES021 – NOVEMBER 2001
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: V 1, V 2, V 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
DD
CC
CC
Supply voltage: V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Supply voltage differences: V 1, V 2, and V 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
CC
CC
CC
Ground voltage differences: AGND1, AGND2, and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage: LRCK, DATA, BCK, SCKI, DEMP0, DEMP1, FMT0, FMT1,
FMT2, RST, and MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
Digital input voltage: ZEROL, ZEROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
Analog input voltage: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (V
Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
+ 0.3 V)
+ 0.3 V)
DD
CC
Ambient temperature under bias, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
A
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 s
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 s
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
electricalcharacteristics, allspecificationsatT =25°C, V =5V, V =3.3V, f =44.1kHz, system
A
CC
DD
S
clock = 256 f and 24-bit data (unless otherwise noted)
S
PCM1730E
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
RESOLUTION
DATA FORMAT
Audio data interface format
24
Bits
2
Standard, I S, left justified
16, 20, 24-bits selectable
MSB first, 2’s complement
Audio data bit length
Audio data format
f
S
Sampling frequency
System clock frequency
10
200
kHz
128, 192, 256, 384, 512, 768 f
S
DIGITAL INPUT/OUTPUT
Logic family
TTL compatible
2
V
V
High-level input logic level
Low-level input logic level
VDC
VDC
IH
0.8
10
IL
I
I
I
I
V
V
V
V
= V
IH
IN
DD
= 0 V
= V
Input logic current (see Note 1)
Input logic current (see Note 2)
µA
µA
–10
100
–10
IL
IH
IL
IN
65
IN
DD
= 0 V
IN
V
V
High-level output logic level
Low-level output logic level
I
I
= –2 mA
= 2 mA
2.4
VDC
VDC
OH
OH
1
OL
OL
NOTES: 1. Pins 1, 4, 5, 6, 7, 12, 13, 14, and 15: RST, LRCK, DATA, BCK, SCKI, FMT0, FMT1, FMT2, and MUTE
2. Pins 10 and 11: DEMP0, DEMP1
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PCM1730
SLES021 – NOVEMBER 2001
electricalcharacteristics, allspecificationsatT =25°C, V =5V, V =3.3V, f =44.1kHz, system
A
CC
DD
S
clock = 256 f and 24-bit data (unless otherwise noted) (continued)
S
PCM1730E
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
DYNAMIC PERFORMANCE (see Note 3)
f
= 44.1 kHz
= 96 kHz
0.0004% 0.008%
0.0006%
S
S
S
Total harmonic distortion plus
f
f
THD+N
noise
V
OUT
= 0 dB
= 192 kHz
0.0012%
EIAJ, A-weighted, f = 44.1 kHz
S
114
114
110
117
EIAJ, A-weighted, f = 96 kHz
S
Dynamic range
dB
dB
117
117
EIAJ, A-weighted, f = 192 kHz
S
EIAJ, A-weighted, f = 44.1 kHz
S
EIAJ, A-weighted, f = 96 kHz
S
Signal-to-noise ratio
Channel separation
117
EIAJ, A-weighted, f = 192 kHz
S
f
S
f
S
f
S
= 44.1 kHz
= 96 kHz
115
113
111
±1
dB
dB
= 192 kHz
Level linearity error
V
OUT
= –110 dB
DC ACCURACY
V
V
2 voltage
2.45
100
±2
V
COM
2 output current
COM
Delta V 2 < 5%
COM
µA
Gain error
%/FSR
Gain mismatch, channel-to-
channel
±0.5
±0.5
%/FSR
%/FSR
Bipolar zero error
At BPZ
ANALOG OUTPUT
Output current
Center current
Full scale (–0 dB)
±2.48
mA
mA
p-p
BPZ input
0
p-p
DIGITAL FILTER PERFORMANCE—FILTER CHARACTERISTICS
±0.002 dB
0.454 f
0.49 f
S
S
Pass band
–3 dB
Stop band
0.546 f
S
Pass-band ripple
–75
±0.002
dB
Stop band = 0.546 f
Stop band = 0.567 f
dB
dB
s
S
S
Stop-band attenuation
–82
Delay time
29/f
S
De-emphasis error
±0.1
dB
NOTE 3: Analog performance specifications are measured by audio precision II under averaging mode. At 44.1-kHz operation, measurement
bandwidth is limited to 20 kHz. At 96-kHz and 192-kHz operation, measurement bandwidth is limited to 40 kHz.
5
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PCM1730
SLES021 – NOVEMBER 2001
electricalcharacteristics, allspecificationsatT =25°C, V =5V, V =3.3V, f =44.1kHz, system
A
CC
DD
S
clock = 256 f and 24-bit data (unless otherwise noted)(continued)
S
PCM1730E
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
POWER SUPPLY REQUIREMENTS
V
V
3
3.3
5
3.6
5.25
9.8
DD
Voltage range
Supply current
VDC
4.75
CC
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
f
S
= 44.1 kHz
7
= 96 kHz
15
I
DD
= 192 kHz
= 44.1 kHz
= 96 kHz
30
mA
33
46.2
263
34.5
36.5
188
222
282
I
CC
= 192 kHz
= 44.1 kHz
= 96 kHz
P
D
Power dissipation
mW
= 192 kHz
TEMPERATURE RANGE
Operation temperature
Thermal resistance
–25
85
°C
θ
28-pin SSOP
100
°C/W
JA
functional description
system clock and reset functions
The PCM1730 requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCKI input (pin 7). The PCM1730 has a system clock detection
circuit, which automatically senses if the system clock is operating at 128 f to 768 f . Table 1 shows examples
S
S
of system clock frequencies for common audio sampling rates.
Figure 1 shows the timing requirements for the system clock input. For optimal performance, it is important to
use a clock source with low phase jitter and noise. Texas Instruments’ PLL1700 multi-clock generator is an
excellent choice for providing the PCM1730 system clock.
t
w(SCKH)
2 V
System Clock
0.8 V
System Clock
Pulse Cycle Time
t
w(SCKL)
PARAMETER
MIN
UNIT
ns
System clock pulse width high, t
System clock pulse width high, t
5
w(SCKH)
5
ns
w(SCKL)
Figure 1. System Clock Input Timing
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PCM1730
SLES021 – NOVEMBER 2001
system clock and reset functions (continued)
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (f
) (MHz)
SCLK
SAMPLING FREQUENCY
128 f
192 f
256 f
384 f
512 f
768 f
S
S
S
S
S
S
32 kHz
44.1 kHz
48 kHz
4.096
5.6488
6.144
6.144
8.4672
9.216
8.192
11.2896
12.288
24.576
49.152
12.288
16.9344
18.432
36.864
73.728
16.384
22.5792
24.576
24.576
33.8688
36.864
96 kHz
12.288
24.576
18.432
36.864
49.152
73.728
192 kHz
See Note 4
See Note 4
NOTE 4: This system clock rate is not supported for the given sampling frequency.
power-on and external reset functions
The PCM1730 includes a power-on reset function. Figure 2 shows the operation of this function. The system
clock input at SCKI should be active for at least one clock period prior to V = 2 V. With the system clock active
DD
and V
clocks from the time V
> 2 V, the power-on reset function will be enabled. The initialization sequence requires 1024 system
DD
> 2 V. The PCM1730 also includes an external reset capability using the RST input
DD
(pin 1). This allows an external controller or master reset circuit to force the PCM1730 to initialize to its reset
state. Figure 3 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of
20 ns. The RST pin is then set to a logic 1 state, which starts the initialization sequence, which requires 1024
system clock periods. The external reset is especially useful in applications where there is a delay between
PCM1730 power up and system clock activation. In this case, the RST pin should be held at a logic 0 level until
the system clock has been activated. The RST pin may then be set to logic 1 state to start the initialization
sequence.
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PCM1730
SLES021 – NOVEMBER 2001
functional description (continued)
V
DD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 2. Power-On Reset Timing
RST (Pin 36)
50% of V
DD
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
PARAMETER
MIN
UNIT
Reset pulse width low, t
20
ns
(RST)
Figure 3. External Reset Timing
audio data interface
audio serial interface
The audio serial interface for the PCM1730 is comprised of a 3-wire synchronous serial port. It includes LRCK
(pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data
present on DATA into the audio interface’s serial shift register. Serial data is clocked into the PCM1730 on the
rising edge of BCK. LRCK is the serial audio left/right word clock. It is used to latch serial data into the serial
audio interface’s internal registers.
LRCK should be synchronous with the system clock. In the event these clocks are not synchronized, the
PCM1730 can compensate for the phase difference internally. If the phase difference between LRCK and SCKI
is greater than 6-bit clocks (BCK), the synchronization is performed internally. While the synchronization is
processing, the analog output is forced to bipolar zero level. The synchronization typically occurs in less than
one cycle of LRCK.
Ideally, it is recommended that LRCK and BCK be derived from the system clock input or output, SCKI or SCKO.
The left/right clock, LRCK, is operated at the sampling frequency, f .
S
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PCM1730
SLES021 – NOVEMBER 2001
audio data formats and timing
2
The PCM1730 supports industry-standard audio data formats, including standard right-justified, I S, and
left-justified. The data formats are shown in Figure 4. Data formats are selected by using the FMT2 (pin 14),
FMT1 (pin 13) and FMT0 (pin 12) as shown in Table 2. All formats require binary 2’s complement, MSB-first
audio data. Figure 5 shows a detailed timing diagram for the serial audio interface.
Table 2. Audio Data Format Select
FMT2
FMT1
FMT0
FORMAT
16-bit standard format, right-justified
(PIN 14)
(PIN 13)
(PIN 12)
Low
Low
Low
Low
High
High
High
High
Low
Low
High
High
Low
Low
High
High
Low
High
Low
High
Low
High
Low
High
20-bit standard format, right-justified
24-bit standard format, right-justified
24-bit MSB-first, left-justified format
2
16-bit I S format
2
24-bit I S format
Reserved
Reserved
zero detect
When the PCM1730 detects that the audio input data in L-channel or R-channel is continuously zero for 1024
f , the PCM1730 sets ZEROL (pin 2) or ZEROR (pin 3) to high.
S
soft mute
The PCM1730 supports mute operation. When MUTE (pin 15) is set to HIGH, both analog outputs are turned
to bipolar zero levels by –0.5-dB steps with transition speed of 1/f per step. This system provides pop-free
S
muting of DAC output.
de-emphasis
The PCM1730 supports de-emphasis filter performance for sampling frequency 32 kHz, 44.1 kHz, 48 kHz.
Sampling frequency is selectable by using DEMP1 (pin 11) DEMP0 (pin 10) as shown in Table 3.
Table 3. De-Emphasis Control
DEMP1 (PIN 11)
DEMP0(PIN 10)
DE-EMPHASIS FUNCTION
Low
Low
High
High
Low
High
Low
High
Disabled
48 kHz
44.1 kHz
32 kHz
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PCM1730
SLES021 – NOVEMBER 2001
functional description (continued)
(1) Standard Data Format (Right Justified); L-channel = High, R-channel = Low
1/f
S
LRCK
R-Channel
L-Channel
BCK
Audio Data Word = 16 Bit
14 15 16
1
2
15 16
LSB
1
2
15 16
DATA
MSB
Audio Data Word = 20 Bit
18 19 20
1
2
19 20
LSB
1
2
19 20
23 24
DATA
MSB
Audio Data Word = 24 Bit
22 23 24
1
2
23 24
LSB
1
2
DATA
MSB
(2) Left Justified Data Format: L-channel = High, R-channel = Low
1/f
S
LRCK
BCK
R-Channel
L-Channel
Audio Data Word = 24 Bit
DATA
1
2
23 24
LSB
1
2
23 24
1
2
MSB
2
(3) I S Data Format: L-channel = Low, R-channel = High
1/f
S
LRCK
L-Channel
R-Channel
BCK
Audio Data Word = 16 Bit
1
1
2
15 16
LSB
1
2
15 16
1
1
2
2
DATA
MSB
Audio Data Word = 24 Bit
DATA
2
23 24
LSB
1
2
23 24
MSB
Figure 4. Audio Data Input Formats
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PCM1730
SLES021 – NOVEMBER 2001
functional description (continued)
50% of V
DD
LRCK
t
t
t
(LB)
(BCH)
(BCL)
50% of V
DD
BCK
t
t
(BL)
(BCY)
50% of V
DD
DATA
t
t
h
su
PARAMETER
MIN
UNIT
ns
BCK pulse cycle time, t
70
30
30
10
10
10
10
(BCY)
BCK pulse width low, t
ns
w(BCL)
BCK pulse width high, t
ns
w(BCH)
BCK rising edge to LRCK edge, t
LRCK edge to BCK rising edge, t
ns
(BL)
ns
(LB)
DATA set up time, t
su
ns
DATA hold time, t
ns
h
LRCK clock duty
50% ±2 bit clock
Figure 5. Audio Interface Timing
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PCM1730
SLES021 – NOVEMBER 2001
typical connection diagram
5 V
15 V
–15 V
Controller
RST
V
3
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
CC
ZEROL
ZEROR
LRCK
DATA
BCK
AGND2
–
I
I
L–
L+
2
3
OUT
–
V
OUT
+
L/R Clock (f
S)
4
OUT
V
L-Channel
+
Audio DATA
Bit Clock
5
CC
+
V
CC
1
6
–
+
System Clock
SCKI
V
3
7
COM
PCM1730E
DGND
I
8
REF
2
+
V
DD
V
V
9
3.3 V
COM
+
DEMP0
DEMP1
FMT0
1
10
11
12
13
14
COM
AGND1
I
R+
OUT
–
FMT1
I
R–
OUT
–
V
OUT
R-Channel
+
FMT2
MUTE
+
+
–
Analog Output Stage
NOTE: Regarding R/C values for analog output stage, see Figure 9.
Figure 6. Typical Application Circuit for Standard PCM Audio Operation
12
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PCM1730
SLES021 – NOVEMBER 2001
analog outputs
5 V
C
R
13
0.1 µF
R
R
15
16
V
3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CC
+
11
C
17
10 µF
AGND2
R
R
–
I
I
L–
L+
2
13
14
OUT
–
C
C
V
11
OUT
+
C
15
OUT
V
L-Channel
+
CC
R
17
+
V
CC
1
–
+
10 µF
1
C
12
R
16
18
V
3
R
16 kΩ
10 µF
COM
+
R
12
PCM1730E
I
REF
2
C
C
14
23
V
V
COM
10 µF
+
1
COM
R
R
25
26
AGND1
R
21
C
27
I
R+
OUT
R
R
–
I
R–
23
24
OUT
–
C
C
V
21
22
OUT
+
C
MUTE
25
R-Channel
+
R
+
27
–
C
R
26
28
R
22
24
C
NOTE: Example R/C values for f 45 kHz
C
R
C
–R , R –R : 620 Ω, C , C , C , C : not populated, C , C , C , C : 5600 pF, C , C : 8200 pF, C , C , C ,
: 1800 pF
27
11 18 21 28 11 12 21 22 13 14 23 24 15 25 16 17 26
Figure 7. Typical Application for Analog Output Stage
analog output level and I/V converter
ThesignallevelofDACcurrentoutputpins(I
The voltage output of the I/V converter is given by following equation:
L+,I
L–,I
R+,I
R–)is±2.48mAp-pat0dB(fullscale).
OUT
OUT
OUT
OUT
V
= ±2.48 mAp–p × R
OUT
f
Here, R is the feedback resistor in the I/V conversion circuit, R , R , R , R on typical application circuit.
f
11 12 21 22
The common level of the I/V conversion circuit must be same as common level of DAC I
which is given by
OUT
V
2 reference voltage, which is 2.48 V dc typically. The noninverting inputs of the op amps shown in the I/V
circuits are connected to V
COM
2 to provide the common bias voltage.
COM
13
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
op amp for I/V converter circuit
OPA627BP/BM or NE5534 type op amp is recommended for I/V conversion circuit to obtain specified audio
performance. Dynamic performance such as gain bandwidth, settling time and slew rate of op amp gives audio
dynamic performance at I/V section. Input noise specification of op amp should be considered to obtain 120 dB
S/N ratio.
analog gain by balanced amp
The I/V converters are followed by balanced amplifier stages, which sum the differential signals for each
channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a second-order
low pass filter function, which band limits the audio output signal. The cutoff frequency and gain are given by
the external R and C component values. In this case, the cutoff frequency is 45 kHz with a gain of 1. The output
voltage for each channel is 6.2 Vp-p, or 2.2 Vrms.
reference current resistor
As shown in the analog output application circuit, there is a resistor connected from I
(pin 21) to analog
REF
ground, designated as R . This resistor sets the current for the internal reference circuit. The value of R must
1
1
be 16 kΩ ±1% in order to match the specified gain error shown in the specifications table.
theory of operation
Upper
6 Bit
0–62
Level
ICOB
Decoder
0–66
Current
Segment
DAC
Advanced
DWA
Analog Output
Digital Input
24 Bit
8 f
rd
3 -Order
S
5-Level
Sigma-Delta
0–4
Level
MSB
and
Lower 18 Bit
Figure 8. Advanced Segments DAC
The PCM1730 utilizes Texas Instruments’ newly developed advanced segment DAC architecture to achieve
excellent dynamic performance and improved tolerance to clock jitter. The PCM1730 provides balanced current
outputs, allowing the user to optimize analog performance externally.
Digital input data via digital filter separates into the upper 6 bits and lower the 18 bits. The upper 6 bits are
converted to ICOB (inverted complementary offset binary) code. The lower 18 bits associated with the MSB are
processed by five level third order delta-sigma modulator operated at 64 f . The one level of the modulator is
S
equivalent to the 1 LSB of the above code converter. The data groups processed in the ICOB converter and
third order delta-sigma modulator are summed together to be created over the 64 level digital code, and then
processed in DWA (data weighted averaging) to reduce noise produced by element mismatch. The data of over
64 level via DWA is converted to analog output in the differential current segment portion.
This architecture has overcome the various drawbacks of conventional multi-bit and also achieves excellent
dynamic performance.
considerations for application circuit
PCB layout guidelines
A typical PCB floor plan for the PCM1730 is shown in Figure 9. A ground plane is recommended, with the analog
and digital sections being isolated from one another using a split or cut in the circuit board. The PCM1730 should
be oriented with the digital I/O pins facing the ground plane split/cut to allow for short, direct connections to the
digital audio interface and control signals originating from the digital section of the board.
14
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
PCB layout guidelines (continued)
Separate power supplies are recommended for the digital and analog sections of the board. This prevents the
switching noise present on the digital supply from contaminating the analog power supply and degrading the
dynamic performance of the D/A converters. In cases where a common 5-V supply must be used for the analog
and digital sections, an inductance (RF choke, ferrite bead) should be placed between the analog and digital
5-V supply connections to avoid coupling of the digital switching noise into the analog circuitry. Figure 10 shows
the recommended approach for single-supply applications.
bypass and decoupling capacitor requirements
Various-sized decoupling capacitors can be used, with no special tolerances being required. All capacitors
should be located as close to the appropriate pins of the PCM1730 as possible to reduce noise pickup from
surrounding circuitry. Aluminum electrolytic capacitors that are designed for hi-fi audio applications are
recommended for larger values, while metal-film or monolithic ceramic capacitors are used for smaller values.
I/V section
I/V conversion circuit by op amp IC and feedback resistor should achieve excellent performance of the
PCM1730. Toobtain0.0004%THD+N, 117-dBsignal-to-noiseratioaudioperformance, THD+Nandinput noise
performance by the op amp IC should be considered, especially if the input noise of the op amp directly gives
outputnoiseleveloftheapplication. TheI
be connected as short distance.
– pinonthePCM1730andtheinvertedinputontheI/Vampshould
OUT
post LPF design
Out-bandnoiselevelandattenuatedsamplingspectrumlevelaremuchlowerthantypicaldelta-sigmatypeDAC
due to the combination of a high-performance digital filter and advanced segment DAC architecture. Second-
order or third-order post LPF is recommended as post LPF of the PCM1730. Cutoff frequency of post LPF is
depends on applications to that there are many sampling rate operation such as f = 44.1 kHz on CDDA,
S
f = 96 kHz on DVD–M, f = 192 kHz on DVD–A.
S
S
Digital Power
+V DGND
Analog Power
AGND +5VA
+V
S S
–V
D
REG
V
CC
Digital
Logic
and
V
DD
DGND
Output
Circuits
Audio
Processor
PCM1730
AGND
Digital
Ground
Analog
Ground
Digital Section
Analog Section
Return Path for Digital Signals
Figure 9. Recommended PCB Layout
15
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
Power Supplies
5 V AGND +V
RF Choke or Ferrite Bead
–V
S
S
REG
V
CC
V
DD
V
DD
DGND
Output
Circuits
PCM1730
AGND
Digital
Ground
Common
Ground
Digital Section
Analog Section
Figure 10. Single-Supply PCB Layout
16
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
digital filter
de-emphasis off
AMPLITUDE
vs
AMPLITUDE
vs
FREQUENCY
FREQUENCY
0
–20
0.003
V
V
T
= 5 V
= 3.3 V
= 25°C
CC
DD
A
V
V
T
A
= 5 V
= 3.3 V
= 25°C
CC
DD
0.002
–40
0.001
–60
–80
0
–100
–120
–140
–0.001
–0.002
–160
–0.003
0.0
0
1
2
3
4
0.1
0.2
0.3
0.4
0.5
Frequency [x f ]
s
Frequency [x f ]
s
Figure 11
Figure 12
†
All specifications at T = 25°C, V
DD
= 3.3 V, V
= 5 V, SCKI = 256 f (f = 44.1 kHz), and 24-bit input data (unless otherwise noted)
CC S S
A
17
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
de-emphasis error
DE-EMPHASIS LEVEL
DE-EMPHASIS ERROR
vs
vs
FREQUENCY
FREQUENCY
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.5
0.4
V
V
= 5 V
= 3.3 V
= 32 kHz
= 25°C
V
V
= 5 V
= 3.3 V
= 32 kHz
= 25°C
CC
DD
CC
DD
f
T
f
T
S
S
0.3
A
A
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10
12
14
0
2
4
6
8
10
12
14
f – Frequency – kHz
f – Frequency – kHz
Figure 13
Figure 14
DE-EMPHASIS LEVEL
vs
DE-EMPHASIS ERROR
vs
FREQUENCY
FREQUENCY
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
0.5
0.4
V
V
= 5 V
= 3.3 V
= 44.1 kHz
= 25°C
V
V
= 5 V
= 3.3 V
= 44.1 kHz
= 25°C
CC
DD
CC
DD
f
T
f
T
S
A
S
0.3
A
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
f – Frequency – kHz
f – Frequency – kHz
Figure 15
Figure 16
†
All specifications at T = 25°C, V
DD
= 3.3 V, V
= 5 V, SCKI = 256 f (f = 44.1 kHz), and 24-bit input data (unless otherwise noted)
CC S S
A
18
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
de-emphasis error (continued)
DE-EMPHASIS ERROR
DE-EMPHASIS LEVEL
vs
vs
FREQUENCY
FREQUENCY
0.5
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
V
V
= 5 V
= 3.3 V
= 48 kHz
= 25°C
CC
DD
V
V
= 5 V
= 3.3 V
= 48 kHz
= 25°C
CC
DD
0.4
0.3
f
T
S
A
f
T
s
A
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
f – Frequency – kHz
f – Frequency – kHz
Figure 17
Figure 18
analog dynamic performance
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
0.0020
0.0020
V
T
A
= 3.3 V
V
CC
V
DD
= 5 V
= 3.3 V
DD
= 25°C
0.0015
0.0015
0.0010
0.0010
f
= 96 kHz
f
= 96 kHz
S
S
f
0.0005
0.0005
f
= 44.1 kHz
= 44.1 kHz
S
S
0.0000
0.0000
4.50
4.75
5.00
5.25
5.50
–50
–25
0
25
50
75
100
V
CC
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 19
Figure 20
†
All specifications at T = 25°C, V
DD
= 3.3 V, V
= 5 V, SCKI = 256 f (f = 44.1 kHz), and 24-bit input data (unless otherwise noted)
CC S S
A
19
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
analog dynamic performance (continued)
DYNAMIC RANGE
DYNAMIC RANGE
vs
FREE-AIR TEMPERATURE
vs
SUPPLY VOLTAGE
120
120
119
118
117
116
V
T
A
= 3.3 V
= 25°C
DD
V
CC
V
DD
= 5 V
= 3.3 V
119
118
117
116
f
= 44.1 kHz
S
f
f
= 96 kHz
S
S
f
= 96 kHz
S
= 44.1 kHz
4.50
4.75
5.00
5.25
5.50
–50
–25
0
25
50
75
100
V
CC
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 21
Figure 22
SNR
vs
SNR
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
120
120
119
118
117
116
V
V
T
A
= 5 V
= 3.3 V
= 25°C
V
CC
V
DD
= 5 V
= 3.3 V
CC
DD
119
118
117
116
f
= 44.1 kHz
f
= 44.1 kHz
S
S
f
= 96 kHz
f
= 96 kHz
S
S
4.50
4.75
V
5.00
5.25
5.50
–50
–25
0
25
50
75
100
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
CC
Figure 23
Figure 24
†
All specifications at T = 25°C, V
DD
= 3.3 V, V
= 5 V, SCKI = 256 f (f = 44.1 kHz), and 24-bit input data (unless otherwise noted)
CC S S
A
20
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
analog dynamic performance (continued)
CHANNEL SEPARATION
vs
CHANNEL SEPARATION
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
118
117
116
115
114
113
112
111
110
118
117
116
115
114
113
112
111
110
V
T
A
= 3.3 V
DD
= 25°C
V
CC
V
DD
= 5 V
= 3.3 V
f
= 44.1 kHz
= 96 kHz
S
f
= 44.1 kHz
= 96 kHz
S
f
S
f
S
4.50
4.75
5.00
5.25
5.50
–50
–25
0
25
50
75
100
V
CC
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 25
Figure 26
†
All specifications at T = 25°C, V
DD
= 3.3 V, V
= 5 V, SCKI = 256 f (f = 44.1 kHz), and 24-bit input data (unless otherwise noted)
CC S S
A
21
www.ti.com
PCM1730
SLES021 – NOVEMBER 2001
TYPICAL CHARACTERISTICS
–60-dB OUTPUT SPECTRUM
–60-dB OUTPUT SPECTRUM
0
–20
0
V
V
f
= 5 V
= 3.3 V
= 44.1 kHz
= 25°C
V
V
f
= 5 V
= 3.3 V
= 44.1 kHz
= 25°C
CC
DD
S
CC
DD
S
–20
–40
T
T
A
A
–40
BW = 20 kHz
BW = 100 kHz
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
0
5
10
15
20
0
20
40
60
80
100
f – Frequency – kHz
f – Frequency – kHz
Figure 27
Figure 28
TOTAL HARMONIC DISTORTION + NOISE
vs
INPUT LEVEL
100
10
1
V
V
T
A
= 5 V
= 3.3 V
= 25°C
CC
DD
f
= 96 kHz
S
0.1
f
= 44.1 kHz
0.010
0.001
S
0.0001
–100
–80
–60
–40
–20
0
Input Level – dBFS
Figure 29
†
All specifications at T = 25°C, V
DD
= 3.3 V, V
= 5 V, SCKI = 256 f (f = 44.1 kHz), and 24-bit input data (unless otherwise noted)
CC S S
A
22
www.ti.com
MECHANICAL DATA
MSSO002D – JANUARY 1995 – REVISED SEPTEMBER 2000
PLASTIC SMALL-OUTLINE
MECHANICAL DATA
DB (R-PDSO-G**)
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /D 09/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15 mm.
D. Falls within JEDEC MO-150
23
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
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Mailing Address:
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Post Office Box 655303
Dallas, Texas 75265
Copyright 2001, Texas Instruments Incorporated
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