PCM4201 [BB]
Low Power, 24-Bit, Single Channel Audio Analog-to-Digital Converter; 低功耗，24位，单声道音频模拟数字转换器
| 型号： | PCM4201 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | Low Power, 24-Bit, Single Channel Audio Analog-to-Digital Converter |
| 文件： | 总21页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
Low Power, 24-Bit, Single Channel Audio
Analog-to-Digital Converter
FEATURES
APPLICATIONS
D
High-Performance Delta-Sigma
Analog-to-Digital Converter
Differential Voltage Inputs
Dynamic Performance:
− Dynamic Range (A-Weighted): Up to
112dB
D
Digital Wireless Microphones
Battery-Powered Audio Recording and
Processing Equipment
D
D
D
DESCRIPTION
The PCM4201 is designed for digital audio applications
that require a combination of high dynamic range, low
distortion, and low power consumption. The primary
applications for the PCM4201 include digital wireless
microphones and battery-operated audio recording or
processing equipment. The PCM4201 outputs 24-bit
linear PCM audio data at sampling rates up to 108kHz.
Three sampling modes allow the user to trade off power for
performance, dependent upon the intended system
requirements. An on-chip voltage reference reduces the
number of external components needed for operation.
− THD+N: As low as −105dB
Three Sampling Modes:
− Supports Output Sampling Rates Up to
108kHz
D
D
− Choose from Low Power, High-
Performance, or Double Speed Modes
Audio Serial Port Interface:
− Master or Slave Mode Operation
− 24-Bit Linear PCM Output Data
− Left-Justified/DSP-Compatible Data
Format
Digital High-Pass Filter for DC Removal:
− Includes a High-Pass Filter Disable Pin
Power Supplies:
The PCM4201 includes dedicated control pins for
configuration of all programmable functions. The device
requires a +5.0V analog power supply, in addition to a
digital supply operating from +1.8V to +3.3V. The
PCM4201 is available in a small TSSOP-16 package.
D
D
− Requires a +5V Analog Power Supply
− Supports a +1.8V to +3.3V Digital Power
Supply Range
D
Low Power Dissipation
− 49mW Typical (Low Power Mode with
V
= +3.3V)
DD
− 39mW Typical (Low Power Mode with
= +1.8V)
V
DD
D
D
Power Down Mode
− Less than 50µW total power dissipation
Available in a small TSSOP-16 Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
I S is a registered trademark of Royal Philips Electronics B.V., The Netherlands. All other trademarks are the property of their respective owners.
ꢀꢇ ꢈ ꢉꢊ ꢁ ꢋꢌ ꢈꢍ ꢉ ꢎꢋꢎ ꢏꢐ ꢑꢒ ꢓ ꢔꢕ ꢖꢏꢒꢐ ꢏꢗ ꢘꢙ ꢓ ꢓ ꢚꢐꢖ ꢕꢗ ꢒꢑ ꢛꢙꢜ ꢝꢏꢘ ꢕꢖꢏ ꢒꢐ ꢞꢕ ꢖꢚꢟ ꢀꢓ ꢒꢞꢙ ꢘꢖꢗ
ꢘ ꢒꢐ ꢑꢒꢓ ꢔ ꢖꢒ ꢗ ꢛꢚ ꢘ ꢏ ꢑꢏ ꢘ ꢕ ꢖꢏ ꢒꢐꢗ ꢛ ꢚꢓ ꢖꢠꢚ ꢖꢚ ꢓ ꢔꢗ ꢒꢑ ꢋꢚꢡ ꢕꢗ ꢌꢐꢗ ꢖꢓ ꢙꢔ ꢚꢐꢖ ꢗ ꢗꢖ ꢕꢐꢞ ꢕꢓ ꢞ ꢢ ꢕꢓ ꢓ ꢕ ꢐꢖꢣꢟ
ꢀꢓ ꢒ ꢞꢙꢘ ꢖ ꢏꢒ ꢐ ꢛꢓ ꢒ ꢘ ꢚ ꢗ ꢗ ꢏꢐ ꢤ ꢞꢒ ꢚ ꢗ ꢐꢒꢖ ꢐꢚ ꢘꢚ ꢗꢗ ꢕꢓ ꢏꢝ ꢣ ꢏꢐꢘ ꢝꢙꢞ ꢚ ꢖꢚ ꢗꢖꢏ ꢐꢤ ꢒꢑ ꢕꢝ ꢝ ꢛꢕ ꢓ ꢕꢔ ꢚꢖꢚ ꢓ ꢗꢟ
Copyright 2004−2005, Texas Instruments Incorporated
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
PCM4201
+6.0
UNIT
V
V
V
CC
Supply voltage
+3.6
V
DD
Ground voltage differences
Digital input voltage
AGND to DGND
RATE, S/M, RST, HPFD SCKI, BCK, FSYNC
+, V
0.1
V
−0.3 to (V
+ 0.3)
V
DD
Analog input voltage
V
−
−0.3 to (V
+ 0.3)
V
IN IN
CC
Input current (any pin except supplies)
Operating temperature range
10mA
mA
°C
°C
−10 to +70
Storage temperature range, T
STG
−65 to +150
(1)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those specified is not implied.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum located at the end of this
datasheet, or see the TI website at www.ti.com.
2
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all characteristics are measured with T = +25°C, V
= +5V, and V
CC DD
= +3.3V. System clock frequency is set to
A
24.576 MHz. Device is operated in Slave mode.
PCM4201
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
24
Bits
AUDIO DATA FORMAT
Format
Two’s complement, MSB first data
Left Justified/DSP Compatible
24
Word length
Bits
DIGITAL I/O
V
0.7 x V
0
V
DD
V
V
IH
DD
Input logic level
Output logic level
Input current
V
0.3 x V
IL
DD
V
I
= −2mA
= +2mA
OL
0.8 x V
V
OH
OH
DD
V
I
0.2 x V
+10
V
OL
DD
I
V
= V
µA
µA
µA
µA
IH
IN
DD
I
V
= 0V
−10
IL
IN
I
V
= V
+25
IH
IN
DD
(1)
Input current
I
V
= 0V
−25
IL
IN
DIGITAL SWITCHING
Normal speed, low power
Normal speed, high performance
Double speed
8
8
54
54
kHz
kHz
kHz
%
Output sampling frequency
f
S
54
45
108
55
System clock duty cycle
System clock frequency
AUDIO SERIAL-PORT TIMING
Delay from FSYNC rising to BCK rising
Delay from BCK rising to FSYNC rising
BCK high pulse width
BCK low pulse width
50
2.048
27.65
MHz
t
5
ns
ns
ns
ns
ns
ns
DBK
t
5
DLK
t
72
72
10
10
BCKH
t
BCKL
Data setup time
t
S
Data hold time
t
H
ANALOG INPUTS
Input voltage, full-scale range (FSR)
Input impedance
Differential input
5.0
15
V
PP
Per analog input pin
kΩ
Common-mode rejection
DC PERFORMANCE
Output offset error
100
dB
High-pass filter disabled
4
4
% of FSR
% of FSR
Gain error
(1)
(2)
Applies to RATE (pin 5) and S/M (pin 6) inputs.
All typical dynamic performance specifications were measured using an Audio Precision System Two Cascade or Cascade Plus test system and a PCM4201EVM
evaluation module. For Normal Speed operation, the measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter and 20kHz low-pass filter.
For Double Speed mode, the measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter and a user-defined 40kHz low-pass filter (the
f /2 low pass filter may be utilized with similar results). All A-weighted measurements are made using the Audio Precision A-weighting filter in combination with
S
the filters previously noted here. Minimum and maximum dynamic performance limits are based upon the capability of the production test solution.
3
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, all characteristics are measured with T = +25°C, V
= +5V, and V
CC DD
= +3.3V. System clock frequency is set to
A
24.576 MHz. Device is operated in Slave mode.
PCM4201
PARAMETER
(2)
CONDITIONS
MIN
104
105
105
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
with V
CC
= +5V and V = +1.8V
DD
Normal Speed, Low Power, f = 48kHz, BW = 22Hz to 20kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
V
= −0.5dB, f = 1kHz
IN
−103
109
−100
dB
dB
dB
IN
V
= −60dB, f = 1kHz, A-weighted
IN
IN
Dynamic range, no weighting
V
= −60dB, f = 1kHz
IN
106
IN
Normal Speed, High Performance, f = 48kHz, BW = 22Hz to 20kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
V
= −0.5dB, f = 1kHz
IN
−105
112
−100
−100
dB
dB
dB
IN
V
= −60dB, f = 1kHz, A-weighted
IN
IN
Dynamic range, no weighting
V
= −60dB, f = 1kHz
IN
110
IN
Double Speed, f = 96kHz, BW = 22Hz to 40kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
V
= −0.5dB, f = 1kHz
IN
−103
112
dB
dB
dB
IN
V
= −60dB, f = 1kHz, A-weighted
IN
IN
Dynamic range, no weighting
V
= −60dB, f = 1kHz
IN
106
IN
= +3.3V
(2)
DYNAMIC PERFORMANCE
with V
CC
= +5V and V
DD
Normal Speed, Low Power, f = 48kHz, BW = 22Hz to 20kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
V
= −0.5dB, f = 1kHz
IN
−102
106
−100
−100
−100
dB
dB
dB
IN
V
= −60dB, f = 1kHz, A-weighted
IN
104
105
105
IN
Dynamic range, no weighting
V
= −60dB, f = 1kHz
IN
104
IN
Normal Speed, High Performance, f = 48kHz, BW = 22Hz to 20kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
V
= −0.5dB, f = 1kHz
IN
−105
112
dB
dB
dB
IN
V
= −60dB, f = 1kHz, A-weighted
IN
IN
Dynamic range, no weighting
V
= −60dB, f = 1kHz
IN
109
IN
Double Speed, f = 96kHz, BW = 22Hz to 40kHz
S
Total harmonic distortion + noise
Dynamic range
THD+N
V
= −0.5dB, f = 1kHz
IN
−103
111
dB
dB
dB
IN
V
= −60dB, f = 1kHz, A-weighted
IN
IN
Dynamic range, no weighting
DIGITAL DECIMATION FILTER
Passband edge
V
= −60dB, f = 1kHz
IN
106
IN
0.453f
Hz
dB
Hz
dB
sec
S
Passband ripple
0.005
Stop band edge
0.547f
S
Stop band attenuation
Group delay
−100
37/f
S
(1)
(2)
Applies to RATE (pin 5) and S/M (pin 6) inputs.
All typical dynamic performance specifications were measured using an Audio Precision System Two Cascade or Cascade Plus test system and a PCM4201EVM
evaluation module. For Normal Speed operation, the measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter and 20kHz low-pass filter.
For Double Speed mode, the measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter and a user-defined 40kHz low-pass filter (the
f /2 low pass filter may be utilized with similar results). All A-weighted measurements are made using the Audio Precision A-weighting filter in combination with
S
the filters previously noted here. Minimum and maximum dynamic performance limits are based upon the capability of the production test solution.
4
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified, all characteristics are measured with T = +25°C, V
= +5V, and V
CC DD
= +3.3V. System clock frequency is set to
A
24.576 MHz. Device is operated in Slave mode.
PCM4201
PARAMETER
DIGITAL HIGH PASS FILTER
Frequency response (−3dB)
POWER SUPPLY
CONDITIONS
MIN
TYP
MAX
UNITS
f /48000
S
Hz
V
V
+4.75
+1.65
+5.0
+3.3
7
+5.25
+3.6
8.2
15
V
CC
Supply voltage range
V
DD
Normal speed, low power
Normal speed, high performance
Double speed
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
13
13
2
I
I
I
I
CC
DD
CC
DD
16
Operating supply current
with V
CC
= +5V, V = +1.8V
DD
Normal speed, low power
Normal speed, high performance
Double speed
3.2
4.5
6.0
8.2
15
2.5
3.5
7
Normal speed, low power
Normal speed, high performance
Double speed
13
13
4
16
Operating supply current
with V = +5V, V = +3.3V
Normal speed, low power
Normal speed, high performance
Double speed
6.0
8.5
10.5
5
CC DD
5
7.5
I
I
CC
Power-Down mode current
with V = +5V, V = +1.8V or +3.3V
5
µA
CC DD
DD
Normal speed, low power
Normal speed, high performance
Double speed
49
82
90
39
70
72
61
mW
mW
mW
mW
mW
mW
Total power dissipation
with V = +5V, V = +3.3V
103
115
47
CC DD
Normal speed, low power
Normal speed, high performance
Double speed
Total power dissipation
with V = +5V, V = +1.8V
83
CC DD
91
(1)
(2)
Applies to RATE (pin 5) and S/M (pin 6) inputs.
All typical dynamic performance specifications were measured using an Audio Precision System Two Cascade or Cascade Plus test system and a PCM4201EVM
evaluation module. For Normal Speed operation, the measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter and 20kHz low-pass filter.
For Double Speed mode, the measurement bandwidth is limited using the Audio Precision 22Hz high-pass filter and a user-defined 40kHz low-pass filter (the
f /2 low pass filter may be utilized with similar results). All A-weighted measurements are made using the Audio Precision A-weighting filter in combination with
S
the filters previously noted here. Minimum and maximum dynamic performance limits are based upon the capability of the production test solution.
5
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
PIN ASSIGNMENT
PW PACKAGE
TSSOP-16
(TOP VIEW)
VIN
+
1
2
3
4
5
6
7
8
16 VREF
+
−
15
14
13
−
VIN
VREF
AGND
VCC
DGND
VDD
PCM4201
RATE
S/M
12 SCKI
11
10
9
BCK
RST
FSYNC
DATA
HPFD
Terminal Functions
TERMINAL
NAME
PIN NO.
I/O
DESCRIPTION
1
2
3
V
+
Input
Input
Noninverting Analog Input
Inverting Analog Input
Analog Ground
IN
V
−
IN
AGND
Ground
4
5
V
Power
Input
Analog Supply, +5V
CC
RATE
Sampling Mode Configuration (Tri-Level Input): 0 = Double Speed;
1 = Normal Speed, Low Power; Z = Normal Speed, High Performance.
Maximum external capacitive load is 100pF.
6
S/M
RST
Input
Input
Audio Serial Port Slave/Master Mode (0 = Master, 1 = Slave)
Reset/Power Down (Active Low)
High Pass Filter Disable (Active High)
Audio Serial Port Data
7
8
HPFD
DATA
FSYNC
BCK
Input
9
Output
I/O
10
11
12
13
14
15
16
Audio Serial Port Frame Synchronization Clock
Audio Serial Port Bit (or Data) Clock
System Clock
I/O
SCKI
Input
(1)
V
Power
Ground
Output
Output
Digital Supply, +3.3V Typical
DD
DGND
Digital Ground
V
V
−
+
Voltage Reference Low Output, Connect to AGND
Voltage Reference High Output, De-Coupling Only
REF
(2)
REF
(1)
(2)
The V
supply may be operated from +1.8V to +3.6V.
Unbuffered output. Do not use to drive external circuitry.
DD
6
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
At T = 25°C, V
= 1.8V, V = 5.0V, Master Mode, SCKI = 24.576MHz, unless otherwise noted.
CC
A
DD
HIGH−PERFORMANCE FFT PLOT
HIGH−PERFORMANCE FFT PLOT
−
−
(fS = 48kHz, fIN = 997Hz at 20dB)
(fS = 48kHz, fIN = 997Hz at 1dB)
0
20
40
60
80
0
−
−
−
−
−
−
−
−
20
40
60
80
−
−
−
−
100
120
140
160
−
−
−
−
100
120
140
160
20
20
20
100
1k
10k
10k
10k
24k
24k
24k
20
20
20
100
1k
10k
10k
10k
24k
24k
24k
Frequency (Hz)
Frequency (Hz)
HIGH−PERFORMANCE FFT PLOT
(fS = 48kHz, fIN = 997Hz at 60dB)
LOW−POWER FFT PLOT
−
−
(fS = 48kHz, fIN = 997Hz at 1dB)
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
100
1k
100
1k
Frequency (Hz)
Frequency (Hz)
LOW−POWER FFT PLOT
LOW−POWER FFT PLOT
−
−
(fS = 48kHz, fIN = 997Hz at 60dB)
(fS = 48kHz, fIN = 997Hz at 20dB)
0
0
−
−
−
−
−
−
−
−
20
40
60
80
20
40
60
80
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
100
1k
100
1k
Frequency (Hz)
Frequency (Hz)
7
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
At T = 25°C, V
= 1.8V, V = 5.0V, Master Mode, SCKI = 24.576MHz, unless otherwise noted.
CC
A
DD
DOUBLE−SPEED FFT PLOT
DOUBLE−SPEED FFT PLOT
−
−
(fS = 96kHz, fIN = 997Hz at 20dB)
(fS = 96kHz, fIN = 997Hz at 1dB)
0
0
20
40
60
80
−
−
−
−
−
−
−
−
20
40
60
80
−
−
−
−
−
−
−
−
100
120
140
160
100
120
140
160
20
100
1k
10k
48k
48k
0
20
100
1k
10k
48k
Frequency (Hz)
Frequency (Hz)
DOUBLE−SPEED FFT PLOT
THD+N vs AMPLITUDE, HIGH PERFORMANCE
(fS = 48kHz, fIN = 997Hz, BW = 20Hz to 20kHz)
−
(fS = 96kHz, fIN = 997Hz at 60dB)
−
0
100
102
104
106
108
−
−
−
−
−
20
40
60
80
−
−
−
VDD = 3.3V
−
−
−
−
−
110
112
114
116
118
120
−
−
−
−
100
120
140
160
VDD = 1.8V
−
−
−
−
−
−
−
20
20
100
1k
10k
120
100
80
60
40
0
Frequency (Hz)
Amplitude (dB)
THD+N vs AMPLITUDE, LOW POWER
(fS = 48kHz, fIN = 997Hz, BW = 20Hz to 20kHz)
THD+N vs AMPLITUDE, DOUBLE SPEED
(fS = 96kHz, fIN = 997Hz, BW = 20Hz to 40kHz)
−
−
−
−
−
−
100
102
104
106
108
100
102
104
106
108
VDD = 3.3V
−
VDD = 3.3V
VDD = 1.8V
−
−
−
VDD = 1.8V
−
−
−
−
−
−
−
−
−
−
110
112
114
116
118
120
110
112
114
116
118
120
−
−
−
−
−
−
−
−
−
−
−
−
−
−
20
120
100
80
60
40
20
120
100
80
60
40
0
Amplitude (dB)
Amplitude (dB)
8
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS (continued)
At T = 25°C, V
DD
= 1.8V, V = 5.0V, Master Mode, SCKI = 24.576MHz, unless otherwise noted.
CC
A
THD+N vs FREQUENCY, HIGH PERFORMANCE
THD+N vs FREQUENCY, LOW POWER
−
−
(fS = 48kHz, Input Level = 1dB, BW = 20Hz to 20kHz)
(fS = 48kHz, Input Level = 1dB, BW = 20Hz to 20kHz)
−
−
−
−
−
−
−
−
90.0
92.5
95.0
97.5
90.0
92.5
95.0
97.5
VDD = 3.3V
VDD = 3.3V
−
−
−
−
−
−
−
−
100.0
102.5
105.0
107.5
100.0
102.5
105.0
107.5
VDD = 1.8V
−
−
−
−
−
−
−
−
110.0
112.5
115.0
117.5
120.0
110.0
112.5
115.0
117.5
120.0
VDD = 1.8V
−
−
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs FREQUENCY, DOUBLE SPEED
−
(fS = 96kHz, Input Level = 1dB, BW = 20Hz to 40kHz)
−
−
−
−
90.0
92.5
95.0
97.5
VDD = 3.3V
−
−
−
−
−
−
−
−
100.0
102.5
105.0
107.5
VDD = 1.8V
110.0
112.5
115.0
117.5
120.0
−
20
100
1k
10k
40k
Frequency (Hz)
9
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
PRODUCT OVERVIEW
The PCM4202 is a single channel audio analog-to-digital
converter (ADC) designed for use in low power, battery-
operated or portable professional audio equipment. Target
applications include digital wireless microphones, and
portable digital audio recorders/processors. The
PCM4201 features 24-bit linear PCM output data, with a
format compatible with digital signal processors, digital
audio interface transmitters, and programmable logic
devices.
expense of increased power dissipation. The Double
Speed mode supports sampling frequencies up to 108kHz
and is provided for those applications where higher
sampling rates may be required.
A digital high-pass filter is included for DC removal.
Dedicated control pins are included for sampling mode
selection, Slave/Master mode audio serial port operation,
digital high-pass filter enable/disable, and reset/
power-down functions.
The PCM4201 includes three sampling modes, supporting
sampling rates up to 108kHz. The Normal Speed, Low
Power mode supports sampling rates up to 54kHz, and
employs 64x oversampling to reduce overall converter
power. The Normal Speed, High Performance mode
supports sampling rates up to 54kHz with 128x
oversampling, resulting in improved dynamic range and
THD+N when compared to the Low Power mode, at the
A +5V power supply is required for the analog section of
the device, while a +3.3V power supply is typically utilized
for the digital section. The digital supply may be operated
at voltages as low as +1.8V, with a corresponding 10 to 20
milliwatt (mW) reduction in power dissipation, depending
upon the sampling mode selection. Figure 1 shows the
functional block diagram for the PCM4201.
VINR+
Delta−Sigma
Modulator
Decimation
Filter
HPF
FSYNC
BCK
−
INR
V
Audio
Serial
Port
DATA
VREF
+
Voltage
Reference
−
VREF
S/M
HPFD
RATE
Reset
Logic
Clock
Control
Power
SCKI
RST
VCC AGND
VDD DGND
Figure 1. PCM4201 Functional Block Diagram
10
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
SCKI (pin 12). The acceptable system clock frequency
and duty cycle range are listed in the Electrical
Characteristics table of this datasheet.
ANALOG INPUTS
The PCM4201 features differential voltage inputs. V +
IN
(pin 1) and V − (pin 2) provide the noninverting and
IN
The PCM4201 supports specific system clock rates, which
are multiples of the desired output sampling frequency.
The supported system clock rate is also dependent upon
the audio serial port mode. Table 1 and Table 2 specify the
system clock rates required for common output sampling
frequencies for both Slave and Master mode audio
serial-port operation.
inverting inputs, respectively. The full-scale input voltage,
measured differentially across these two pins, is
approximately 5.0V
.
The input impedance is
PP
approximately 15kΩ per input pin.
In applications where the analog inputs can be driven
beyond the analog supply rails of the PCM4201, the input
buffer circuit should incorporate clamping or limiting
circuitry to ensure that the analog inputs are not driven
beyond the absolute maximum input levels for these pins.
Refer to the Absolute Maximum Ratings table of this
datasheet.
Table 1. System Clock Rates for Common Audio
Sampling Frequencies—Slave Mode Operation
SYSTEM CLOCK
FREQUENCY (MHZ)
SAMPLING
FREQUENCY
(kHz)
SAMPLING
MODE
SCKI = 256f
SCKI = 512f
S
S
VOLTAGE REFERENCE
Normal
Normal
Normal
Double
Double
32
44.1
48
88.2
96
8.192
11.2896
12.288
22.5792
24.576
16.384
22.5792
24.576
n/a
The PCM4201 includes an on-chip band gap reference for
the delta-sigma modulator, eliminating the need for
external reference circuitry. The reference voltage is set to
n/a
+2.5V nominal. The V
+ (pin 16) and V
− (pin 15)
REF
REF
outputs provide connections for reference decoupling
capacitors, which are connected between these two pins.
The VREF− output is then connected to analog ground.
Figure 2 shows the recommended decoupling capacitor
connections and values.
Table 2. System Clock Rates for Common Audio
Sampling Frequencies—Master Mode Operation
SYSTEM CLOCK
FREQUENCY (MHZ)
SAMPLING
FREQUENCY
(kHz)
SAMPLING
MODE
SCKI = 256f
SCKI = 512f
S
S
Normal
Normal
Normal
Double
Double
32
44.1
48
88.2
96
N/A
N/A
N/A
22.5792
24.576
16.384
22.5792
24.576
n/a
PCM4201
16
VREF
+
+
µ
µ
10 F
0.1 F
n/a
−
VREF
15
AGND
SAMPLING MODES
The PCM4201 supports three sampling modes, allowing the
user to select the most appropriate power/performance
Figure 2. Voltage Reference Connections
combination for
paragraphs describe the operation and tradeoffs for the three
sampling modes. For all cases, f is defined as the desired
output sampling rate at the audio serial port interface.
a given application. The following
The voltage reference output is not buffered, and should
not be connected to external circuitry other than the
decoupling capacitors. DC common-mode voltage for the
input buffer circuitry may be set using an external voltage
divider circuit, as shown in the Applications Information
section of this datasheet.
S
Normal Speed, Low Power mode provides the lowest
overall power dissipation, while supporting sampling rates
up to 54kHz. The modulator oversampling rate is 64f for
S
this mode, which results in lower dynamic range and
THD+N when compared to Normal Speed, High
Performance mode. For best dynamic performance and
lowest power consumption when using Low Power mode,
it is recommended to operate the PCM4201 from a +1.8V
digital power supply.
SYSTEM CLOCK
The PCM4201 requires an external system clock, which is
used internally to derive the modulator oversampling and
digital subsystem clocks. The system clock is input at
11
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
Normal Speed, High Performance mode provides the best
overall dynamic performance at the expense of increased
power dissipation. Sampling rates up to 54kHz are
Table 3. Sampling Mode Configuration
RATE (PIN 5)
SAMPLING MODE SELECTION
0
Double Speed
supported. The modulator oversampling rate is 128f for
S
1
Normal Speed, Low Power
Normal Speed, High Performance
this mode, improving the overall dynamic range and
THD+N when compared to Low Power mode.
Float or Hi Z
Double Speed mode supports sampling frequencies up to
108kHz with power dissipation that is somewhat higher
than Normal Speed, High Performance mode. The
AUDIO SERIAL PORT
The PCM4201 audio serial port is a 3-wire synchronous
serial interface comprised of the audio serial data output,
DATA (pin 9); a frame synchronization clock, FSYNC (pin
10); and a bit or data clock, BCK (pin 11). The FSYNC and
BCK clocks may be either inputs or outputs, supporting
either Slave or Master mode interfaces, respectively. The
audio data format is 24-bit linear PCM, represented as
two’s complement binary data with the MSB being the first
data bit in the frame. Figure 3 illustrates the audio frame
format, while Figure 4 and the Electrical Characteristics
table highlight the important timing parameters for the
audio serial port interface.
modulator oversampling rate is 64f for this mode.
S
The sampling mode is selected using the RATE input (pin
5). The RATE pin is a tri-level logic input, with the ability to
detect low, high, and floating (or high-impedance) states.
Table 3 shows the available sampling mode
configurations using the RATE pin. For the floating or
high-impedance case, it is best to drive the RATE pin with
a tri-state buffer, such as the Texas Instruments
SN74LVC1G125 or equivalent. This allows the buffer to be
disabled, setting the output to a high-impedance state.
One Frame (1)
1/fS
FSYNC (2)
Slave Mode
Frame Format
Data (4)
DATA
FSYNC (3)
Master Mode
Frame Format
Data (4)
DATA
NOTES: (1) One Frame = 128 BCK clock cycles for Normal Speed modes and 64 BCK clock cycles for Double Speed mode.
(2) For Slave Mode operation, the FSYNC pulse width high period must be at least one BCK clock cycle in length,
while the FSYNC pulse low period must be at least one BCK clock cycle in length. Best performance is achieved
when the FSYNC duty cycle is 50%.
(3) For Master mode operation, the FSYNC clock duty cycle is equal to 50%.
(4) The audio data word length is 24 bits and is Left−Justified in the frame. The audio data is always presented in
two’s complement binary format with the MSB being the first data bit in the frame.
Figure 3. Audio Serial-Port Frame Format
tDLK
FSYNC
BCK
tDBK
tBCKH
tBCKL
DATA
tS
tH
Figure 4. Audio Serial-Port Timing
12
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
Slave mode operation requires that the FSYNC and BCK
clocks be generated from an external audio processor or
master timing generator, as shown in Figure 5. Both clocks
are inputs in Slave mode. The FSYNC clock rate is the
DIGITAL HIGH-PASS FILTER
The PCM4201 includes a digital high-pass filter, which is
located at the output of the digital decimation filter block.
The purpose of the high-pass filter is to remove the DC
component from the digitized signal. The corner, or −3dB
frequency, for the digital high-pass filter is calculated using
the following relationship:
equal to the desired output sampling frequency, f . The
S
FSYNC high pulse width must be equal to at least one BCK
clock period. The BCK clock rate should be 128f for
S
Normal Speed modes (both Low Power and High
Performance), while the BCK clock rate is 64f for Double
Speed mode.
S
fS
48000
f
+
*3dB
(1)
where f = the output sampling frequency.
S
AUDIO DSP
FSR
PCM4201
The digital high-pass filter may be enabled or disabled
using the HPFD input (pin 8). When HPFD is forced low,
the high-pass filter is enabled. Forcing HPFD high
disables the high-pass filter. Distortion for signal
frequencies less than 100Hz may increase slightly when
the high-pass filter is enabled.
FSYNC SCKI
BCK
CLKR
DR
DATA
S/M
VDD
RESET OPERATION
System
Clock
The PCM4201 includes two reset functions: power on and
externally controlled. This section describes the operation
of each of these functions.
On power up, the internal reset signal is forced low, forcing
the PCM4201 into a reset state. The power-on reset circuit
Figure 5. PCM4201 Slave Mode Configuration
monitors the V (pin 13) and VCC (pin 4) power supplies.
DD
When the digital supply exceeds 0.6 × VDD nominal
For Master mode operation, the PCM4201 generates the
FSYNC and BCK clocks, deriving them from the system
clock input, SCKI (pin 12), as shown in Figure 6. The
FSYNC clock rate is equal to the output sampling
400mV, and the V supply exceeds +4.0V 400mV, the
CC
internal reset signal is forced high. The PCM4201 will then
wait for the system clock input (SCKI) to become active.
Once the system clock has been detected, the initialization
sequence begins. The initialization sequence requires
1024 system clock periods for completion. During the
initialization sequence, the ADC output data pin will be
forced low. Once the initialization sequence is completed,
the PCM4201 outputs valid data. Figure 7 shows the
power-on reset sequence timing.
frequency, f . The FSYNC clock duty cycle is 50% in
S
Master mode. The BCK clock rate is fixed at 128f for
S
Normal Speed modes (both Low Power and High
Performance), and 64f for Double Speed mode.
S
AUDIO DSP
FSR
PCM4201
The user may force a reset initialization sequence at any
time while the system clock input is active by utilizing the
RST input (pin 7). The RST input is active low, and requires
a minimum low pulse width of 40ns. The low-to-high
transition of the applied reset signal will force an
initialization sequence to begin. As in the case of the
power-on reset, the initialization sequence requires 1024
system clock periods for completion. Figure 8 illustrates
the reset sequence initiated when using the RST input.
FSYNC SCKI
BCK
CLKR
DR
DATA
S/M
DGND
System
Clock
Figure 9 shows the state of the audio data output (DATA)
for the PCM4201 before, during, and after the reset
operations.
Figure 6. PCM4201 Master Mode Configuration
13
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
~ 4.0V
VCC
0V
0.6 x VDD
Nominal(1)
VDD
0V
Internal
Reset
1024 System Clock Periods
Required for Initialization
0V
0V
SCKI
System Clock
Indeterminate
or Inactive
(1) VDD nominal range is +1.8V to +3.6V.
Figure 7. Power-On Reset Sequence
tRSTL > 40ns
RST
0V
1024 System Clock Periods
Required for Initialization
Internal
Reset
0V
0V
SCKI
Figure 8. External Reset Sequence
HI
Internal
Reset
LO
Output
Data Pins
Outputs Forced Low
for 1024 SCKI Periods
Valid Output Data
Outputs Forced Low
Valid Output Data
Initialization
Period
Figure 9. ADC Digital Output State for Reset Operation
14
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
mode, the system and audio clocks should be restarted.
Once the clocks are active, the RST input may be driven
high, which initiates a reset initialization sequence.
Figure 10 illustrates the state of the output data pins
before, during, and upon exiting the power down state.
POWER-DOWN OPERATION
The PCM4201 can be forced to a power-down state by
applying a low level to the RST input (pin 7) for a minimum
of 65,536 system clock cycles. In power-down mode, all
internal clocks are stopped, and the output data pin is
forced low. The system clock may then be removed to
conserve additional power. Before exiting power-down
HI
RST
LO
Output
Data Pins
Outputs
Forced Low
Outputs
Forced Low
Outputs
Forced Low
Valid Output Data
Valid Output Data
1024 SCKI Periods
Required for Initialization
65,536
SCKI Periods
Enter
Power−Down
State
Figure 10. ADC Digital Output State for Power-Down Operation
15
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
APPLICATIONS INFORMATION
A typical connection diagram for the PCM4201 is shown
in Figure 11. Power supply bypass and reference
decoupling capacitors are included, and are labeled with
recommended values. The 0.1µF capacitors should be
X7R ceramic chip type, although other low ESR capacitor
types may also be used. The 10µF capacitors may be low
ESR tantalum, multilayer ceramic, or aluminum
electrolytic capacitors. Analog and digital ground pins
should be connected at a common point, preferably
beneath the PCM4201 package.
INPUT BUFFER CIRCUIT EXAMPLES
The PCM4201 analog input requires some type of input
buffer or signal conditioning circuitry, especially when
interfacing to a microphone capsule. The input buffer or
amplifier must incorporate at least a single pole, RC
low-pass filter in order to provide antialias filtering for the
delta-sigma modulator. A filter with a −3dB corner
frequency in the range of 100kHz to 150kHz should be
sufficient for common audio output sampling rates equal to
or greater than 44.1kHz. However, a low-pass filter with a
lower corner frequency and possibly a higher filter order
will be required when running at the lower sampling rates,
depending upon the system requirements. Examples of
single-ended and differential input circuits are shown in
Figure 12 and Figure 13, respectively.
Printed circuit board layout is critical for best performance.
Please refer to the PCM4201EVM User’s Guide (TI
literature number SBAU108) for an example of a design
and layout that meets the published specifications for the
PCM4201.
Input
Buffer
1
16
VIN
+
VREF
+
Analog
Input
+
µ
µ
10 F
0.1 F
2
3
4
5
6
7
8
15
14
13
12
11
10
9
−
VIN
−
VREF
AGND
VCC
DGND
VDD
µ
µ
µ
µ
10 F
0.1 F
0.1 F
10 F
+
+
+1.8V to +3.6V
+5V
PCM4201
RATE
S/M
SCKI
From
BCK
Control
Logic
DSP, FPGA,
or
DIT4096
RST
FSYNC
DATA
HPFD
System Clock
Figure 11. Typical Connections for the PCM4201
16
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
For single-ended or unbalanced inputs, the input buffer
circuit shown in Figure 12 provides the conversion to a
differential signal required for the PCM4201 analog inputs.
The buffer circuit may be configured for the appropriate
gain/attenuation using resistors R1 and R2. Capacitor C1
is chosen to provide the low-pass corner frequency.
Additional low-pass filtering is provided by the RC network
at the output of the buffer.
A differential input buffer circuit is shown in Figure 13. Like
the unbalanced circuit, the differential buffer
gain/attenuation may be set by using the R1/R2 and R3/R4
resistor pairs. The resulting gain or attenuation must be the
same for both pairs. Filtering is provided by the feedback
capacitors and the capacitors at the buffer output. This
circuit configuration is used for the PCM4201EVM
evaluation module.
C1
R2
µ
10 F
µ
to 100 F
100pF
R1
Ω
40.2
Analog
Input
−
VIN
U1A
Ω
2.49k
Ω
2.49k
+5V
µ
0.022 F
Ω
40.2
Ω
Ω
10k
10k
VIN+
U1B
100pF
+
µ
10 F
µ
0.1 F
NOTE: U1 = OPA2134 or equivalent.
Figure 12. Single-Ended Input Buffer Circuit
R2
1000pF
µ
10 F
µ
to 100 F
R1
Ω
40.2
VIN+
U1A
+5V
100pF
Analog
Input
Ω
Ω
10k
2
3
µ
0.1 F
1
2700pF
+
µ
10 F
10k
Ground
Lift
Switch
µ
10 F
Ω
40.2
µ
to 100 F
−
VIN
R3
U1B
100pF
1000pF
NOTE: U1 = OPA2134 or equivalent.
R4
Figure 13. Differential Input Buffer Circuit
17
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆ
www.ti.com
SBAS342A − DECEMBER 2004 − REVISED MARCH 2005
The PCM4201 output data format is equivalent to the
Left-Justified data format supported by the DIT4096
transmitter. Although this format supports two channels for
stereo operation, the PCM4201 provides only one
channel, which corresponds to the left data channel of the
DIT4096 Left-Justified data format, and channel A of the
AES3 frame format. Figure 14 shows the physical
interface between the PCM4201 and the DIT4096
INTERFACING TO THE DIT4096 DIGITAL AUDIO
TRANSMITTER
The Texas Instruments DIT4096 digital audio transmitter
encodes linear PCM audio data into AES3 standard
formatted data, which is compatible with a number of
professional and consumer audio specifications and
interfaces. This encoding provides a convenient, standard
transmission format over which the audio data from the
PCM4201 may be carried. The physical interface may be
twisted pair or coaxial cable, or all-plastic optical fiber. The
combination of the PCM4201, the DIT4096, and the
appropriate microphone element and preamplifier circuit
may be used to create a cost-effective, digital-interface
microphone solution.
transmitter. The digital supply for the PCM4201 (V ) and
DD
the digital I/O supply for the DIT4096 (V ) must be set to
IO
the same voltage in order to ensure logic level
compatibility.
Preamplifier/Buffer
PCM4201
DIT4096
To
SCLK
SYNC
SDIN
BCK
FSYNC
DATA
VIN
+
TX+
Microphone
Capsule
Balanced or Unbalanced
Line Interface or
Optical Transmitter
−
VIN
−
TX
S/M
SCKI
MCLK
M/S
Master
Clock
NOTES: The PCM4201 is in Master mode, while the DIT4096 is in Slave mode.
Both operate from the same Master clock source.
The data format for the DIT4096 is configured for Left−Justified mode.
Figure 14. Digital Interface Microphone Example
18
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2005
PACKAGING INFORMATION
Orderable Device
PCM4201PW
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
16
94 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
PCM4201PWR
TSSOP
PW
16
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明