PCM66P [BB]

16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER; 16位CMOS单片音频数位类比转换器


型号：	PCM66P
厂家：	BURR-BROWN CORPORATION
描述：	16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER 16位CMOS单片音频数位类比转换器转换器
文件：	总7页 (文件大小：93K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PCM66P

FPO

16-Bit CMOS Monolithic Audio

DIGITAL-TO-ANALOG CONVERTER

FEATURES

● LOW COST 16-BIT 2-CHANNEL CMOS

DESCRIPTION

The PCM66P is a low cost, dual output 16-bit CMOS

digital-to-analog converter. The PCM66P features true

glitch-free voltage outputs, internal reference and re-

quires only a single +5V supply. Total power dissipa-

tion is less than 50mW max. Low maximum Total

Harmonic Distortion + Noise (–86dB max; PCM66P-

J) is 100% tested. Either one or two channel output

modes are fully user selectable.

MONOLITHIC D/A CONVERTER

● SINGLE SUPPLY +5V OPERATION

● 50mW POWER DISSIPATION

● GLITCH-FREE VOLTAGE OUTPUTS

● LOW DISTORTION: –86dB max THD + N

● COMPLETE WITH REFERENCE

● SERIAL INPUT FORMAT

The PCM66P comes in a space-saving 20-pin plastic

SOIC package. PCM66P accepts a serial data input

format and is compatible with other Burr-Brown PCM

products such as the industry standard PCM56P.

● SINGLE OR DUAL DAC MODE

OPERATION

● PLASTIC 20-PIN SOIC PACKAGE

V_REF

V_CC(+5V)

SDM SEL

Reference

A_COM

16-Bit

V_OUTDAC

Integrate

& Hold Amp

LRDAC

LRCLK

WDCLK

CLK

L CH Out

Control

Logic

V_OUT

Integrate

R CH Out

Serial-to-Parallel

Shift Register

& Hold Amp

DATA

D_COM

International Airport Industrial Park

•

Mailing Address: PO Box 11400

Cable: BBRCORP

•

Tucson, AZ 85734

•

Street Address: 6730 S. Tucson Blvd.

• Tucson, AZ 85706

Tel: (602) 746-1111

•

Twx: 910-952-1111

•

Telex: 066-6491

•

FAX: (602) 889-1510

•

Immediate Product Info: (800) 548-6132

PDS-1051D

Printed in U.S.A. October, 1993

SPECIFICATIONS

ELECTRICAL

All specifications at 25°C, and +V_CC= +5V unless otherwise noted.

PCM66P AND PCM66P, J

TYP

PARAMETER

CONDITIONS

MIN

MAX

UNITS

Bits

RESOLUTION

DYNAMIC RANGE

DIGITAL INPUT

Logic Family

Logic Level: V_IH

V_IL

Data Format

Input Clock Frequency

TTL Compatible CMOS

I_IH= +40µA max

I_IL= –40µA max

+2.4

+5.25

0.8

Serial BTC⁽¹⁾

8.5

MHz

DYNAMIC CHARACTERISTICS

TOTAL HARMONIC DISTORTION + N⁽²⁾

PCM60P/66P: f = 991Hz (0dB)⁽³⁾

f = 991Hz (–20dB)

f = 991Hz (–60dB)

PCM60P-J/66P-J: f = 991Hz (0dB)

f = 991Hz (–20dB)

f_S= 176.4kHz⁽⁴⁾

f_S= 176.4kHz

–88

–68

–28

–92

–68

–28

–82

–86

f = 99lHz (–60db)

CHANNEL SEPARATION

+80

+85

TRANSFER CHARACTERISTICS

ACCURACY

Gain Error

Gain Mismatch

Bipolar Zero Error⁽⁵⁾

Gain Drift

V_OUT= 2.6

Channel to Channel

±2

±1

±30

100

±10

ppm/°C

minute

0°C to 70°C

Warm-up Time

IDLE CHANNEL SNR⁽⁶⁾

20-20kHz with A-weighted filter

±90

ANALOG OUTPUT

Output Range

Output Impedance

Short Circuit Duration

Settling Time

2.6

Vp-p

Ω

To Be Determined

Suffieicnt to Meet 176.4kHz THD + N Specs

Glitch Energy

Meets All THD + N Specs Without External Output Deglitching

POWER SUPPLY REQUIREMENTS

+V_CCSupply Voltage

Supply Current

+4.75

+9.5

+5.25

Power Dissipation

V_CC= +5V

TEMPERATURE RANGE

Specification

Operating

–30

–60

+70

+100

°C

Storage

NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (Distortion_RMS+ Noise_RMS) / Signal_RMS. (3) D/A converter output frequency/signal level (on both left and

right channels). (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling per channel). (5) Offset error at bipolar zero. (6) Ratio of output at BPZ (Bipolar

Zero) to the full scale range using 20kHz low pass filter in addition to an A-weighted filter.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject

to change without notice. No patent right or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize

or warrant any BURR-BROWN product for use in life support devices and/or systems.

PCM66P

PACKAGE INFORMATION⁽¹⁾

PCM66P PIN ASSIGNMENTS

DESCRIPTION

MNEMONIC

PACKAGE DRAWING

NUMBER

MODEL

PACKAGE

Left/Right Clock

Word Clock

Clock Input

LRCLK

WDCLK

CLK

PCM66P

PCM66P, J

20-Pin SOIC

248

Data Input

DATA

D_COM

A_COM

L CH Out

V_COM

R CH Out

+V_CC

C_REF

V_REFSENSE

V_REF

+V_CC

SDM SEL

LRDAC

NOTE: (1) For detailed drawing and dimension table, please see end of data

sheet, or Appendix D of Burr-Brown IC Data Book.

No Connection

Digital Common

Analog Common

Left Channel V_OUT

Output Common

Right Channel V_OUT

Analog Supply

Reference Decouple

Reference Sense

Reference Output

Analog Supply

Digital Supply

USA OEM PRICES

ORDERING INFORMATION

PCM66P -X

100+

MODEL

1–24

25-99

Basic Model Number

PCM66P

$11.80

13.30

$10.40

11.70

$9.15

10.30

P: Plastic

PCM66P-J

Performance Grade Code

ABSOLUTE MAXIMUM RATINGS

Single DAC Mode

Left/Right DAC Select

DC Supply Voltage ............................................................................ ±10V

Input Voltage Range ........................................................... –3V to +5.25V

Power Dissipation ............................................................................ 50mW

Operating Temperature .................................................... –30°C to +70°C

Storage Temperature...................................................... –60°C to +100°C

Lead Temperature (soldering, 10s) ............................................... +300°C

THEORY OF OPERATION

ships. Data for left and right channel output is loaded

alternately into the PCM66P while the control logic

switches the left and right output amplifiers between the

appropriate integrate and hold modes. Data word latch-

ing is controlled by WDCLK (word clock) and channel

selection is made by LRCLK (left/right clock). Figure 1

shows the timing for the single DAC two-channel mode

of operation. The block diagram in Figure 2 shows how

a single DAC output provides switched output to both

integrate and hold amplifiers. Output between left and

right channels in this mode is not in phase. See Figure 3

for proper connection of the PCM66P in the two-channel

DAC mode.

The PCM66P is a dual output, 16-bit CMOS digital-to-analog

audio converter. The PCM66P, complete with internal refer-

ence, has two glitch-free voltage outputs and requires only a

single +5V power supply. Output modes using either one or two

channels per DAC are user selectable. The PCM66P accepts a

serial data input format that is compatible with other Burr-

Brown PCM products such as the industry standard PCM56P.

ONE DAC TWO-CHANNEL OPERATION

Normally, the PCM66P is operated with a continuous clock

input in a two-channel output mode. This mode is selected when

SDM SEL is held low (single DAC mode select). Refer to the

truth table shown by Table I for exact control logic relation-

PIN FUNCTIONS

SERIAL

DATA WORD

INPUT

LEFT

CHANNEL

OUTPUT

RIGHT

CHANNEL

OUTPUT

SDM SEL

LRDAC

LRCLCK

WDCLK

Right

Left

Hold

Integrate

Hold

Left

Hold

Integrate

Inhibited

Left

V_COM

Hold

Integrate

Left

Right

Inhibited

V_COM

Hold

Integrate

NOTE: Positive edge of CLK (P3) latches LRCLK (P1), WDCLK (P2), and DATA (P4).

TABLE I. PCM66P Logic Truth Table.

PCM66P

TWO CHANNEL PER DAC OUTPUT MODE

P3 (CLK)

P2 (WDCLK)

P1 (LRCLK)

Load Right Channel Data

Load Left Channel Data

P4 (DATA)

10 11 12 13 14 15 16

Hold

Integrate

Hold

P10 (LCH OUT)

P10 (LCH V_OUT

)

Hold

Integrate

P12 (RCH OUT)

P12 (RCH V_OUT

)

NOTES: Single DAC Mode Select = 0; L/R DAC Select = X; WDCLK = 50% duty cycle; Serial Data is read in MSB first with BTC coding (MSB

= Bit 1).

SINGLE CHANNEL PER DAC OUTPUT MODE

P3 (CLK)

Both DACs

P2 (WDCLK)

Both DACs

P1 (LRCLK)

Both DACs

Load Right DAC Data

Load Left DAC Data

P4 (DATA)

Both DACs

10 11 12 13 14 15 16

P12 (RCH OUT)

Right DAC

Hold

Integrate

P12 (RCH V_OUT

)

Right DAC

P12 (RCH OUT)

Left DAC

Hold

Integrate

P12 (RCH V_OUT

)

Left DAC

NOTES: Single DAC Mode Select = 1; L/R DAC Select = 0 (Left DAC) or 1 (Right DAC).

FIGURE 1. PCM66P Timing Diagram.

PCM66P

DATA

CLK

Serial/Parallel

Shift Register

WDCLK

LRCLK

16-Bit Input

Data Latch

4kΩ

30kΩ

LRDAC

10kΩ

20kΩ

16-Bit D/A

Converter

–

LCH

V_OUT

SDM SEL

0–3.5V

V_COM

4kΩ

30kΩ

Reference

–

20kΩ

–

R CH

V_OUT

+V_CC

V_REFV_REF

SEN

C_REF+V_CC

FIGURE 2. PCM66P Block Diagram.

input with no additional input signals being required to latch

the appropriate data from an alternating L/R data word input

stream. In the single DAC mode, the PCM66P’s left channel

output is disabled and held at +V_COM. In this mode both

DACs share common inputs for DATA, CLK, WDCLK, and

LRCLK. Otherwise circuit connection is the same as the

two-channel DAC mode, with the exception of LRDAC

whose level selects whether the single DAC will output

dedicated left or right channel data.

PCM66P

Mode Select

LRCLK

WDCLK

CLK

Mode 2 20

Mode 1 19

+V_CC18

Digital

Input

DATA

+V_CC17

+V_CC16

D_COM

V_REF15

10µF

A_COM

V_REFSEN 14

C_REF13

INTEGRATE AND HOLD OUTPUT AMPLIFIERS

L CH Out

V_COM

The PCM66P incorporates integrate and hold amplifiers on

each output channel. This allows a single, very fast DAC to

feed both amplifiers and reduce circuit complexity. It also

serves to block the output glitch from the DAC to the

individual channel outputs and effectively makes the PCM66P

outputs “glitch-free.” The PCM66P is a single +5V supply

device with a voltage output swing of 2.8Vp-p. The outputs

swing asymmetrically around V_COM(+V_CC– 2.33V). See

Table II for exact input/output relationships. Since true

CMOS amplifiers are used on the PCM66P, the load resis-

tance on the outputs should not be less than 100kΩ and the

capacitive loads should not exceed 100pF. For maximum

low-distortion performance, output buffer amplifiers should

be considered.

0.1µF

330pF

C_REF

L CH Out

+V_CC12

10 R CH Out

C_COM

+V_CC11

100µF

R CH Out

3.3µF

+V_CC

+5V

FIGURE 3. PCM66P Connection Diagram.

TWO DAC TWO-CHANNEL OPERATION

In phase, two-channel output can be obtained by using two

PCM66Ps and choosing the single DAC mode (setting SDM

SEL high). With the use of a high or low input level on

LRDAC (P left/right DAC select), each DAC can have its

right channel output dedicated to either left or right data

PCM66P

performance is typically indicative of 14-bit to 15-bit inte-

gral linearity in the DAC depending on the grade specified.

The relationship between THD + N and linearity, however,

is not such that an absolute linearity specification for every

individual output code can be guaranteed.

DIGITAL INPUT

ANALOG OUTPUT

Binary Two’s

Complement (Hex)

Voltage (V)

_OUTMode

DAC Output (V)

7FFF

0000

8000

2E5B

+FS

BPZ

–FS

V_COM

+3.5629443

+2.1629871

+0.7630299

+2.6700000

IDLE CHANNEL SNR

TABLE II. PCM66P Input/Output Relationships.

Another appropriate spec for a digital audio converter is idle

channel signal-to-noise ratio (idle channel SNR). This is the

ratio of the noise on either DAC output at bipolar zero in

relation to the full scale range of the DAC. The output of the

DAC is band limited from 20Hz to 20kHz and an A-

weighted filter is applied to make this measurement.

DISCUSSION OF

SPECIFICATIONS

TOTAL HARMONIC DISTORTION + NOISE

The key specification for the PCM66P is total harmonic

distortion plus noise. Digital data words are read into the

PCM66P at four times the standard audio sampling fre-

quency of 44.1kHz or 176.4kHz for each channel, such that

a sine wave output of 991Hz is realized. For production

testing, the output of the DAC goes to a programmable gain

amplifier to provide gain at lower signal output test levels

and then through a 20kHz low pass filter before being fed

into an analog type distortion analyzer. Figure 4 shows a

block diagram of the production THD + N test setup.

OFFSET, GAIN, AND TEMPERATURE DRIFT

The PCM66P is specified for other important parameters

such as channel separation and gain mismatch between

output channels. And although the PCM66P is primarily

meant for use in dynamic applications, typical specs are also

given for more traditional DC parameters such as gain error,

bipolar zero offset error, and temperature gain drift.

TIMING CONSIDERATIONS

In terms of signal measurement, THD + N is the ratio of

Distortion_RMS+ Noise_RMS/Signal_RMSexpressed in dB. For the

PCM66P, THD + N is 100% tested at three different output

levels using the test setup shown in Figure 4. It is significant

to note that this circuit does not include any output deglitching

circuitry. This means the PCM66P meets even its –60dB

THD + N specification without use of external deglitchers.

The data format of the PCM66P is binary two’s complement

(BTC) with the most significant bit (MSB) being first in the

serial input bit stream. Table II describes the exact input data

to voltage output coding relationship. Any number of bits

can precede the 16 bits to be loaded, as only the last 16 will

be transferred to the parallel DAC register on the first

positive edge of CLK (clock input) after WDCLK (word

clock) has gone low. All inputs to the PCM66P are TTL

level compatible.

ABSOLUTE LINEARITY

Even though absolute integral and differential linearity specs

are not given for the PCM66P, the extremely low THD + N

Use 400Hz High-Pass

Low-Pass

Filter

(Toko APQ-25

Programmable

Gain Amp

0dB to 60dB

Distortion Meter

(Shiba Soku Model

725 or Equivalent)

Filter and 30kHz

Low-Pass Filter

Meter Settings

LOW-PASS FILTER

CHARACTERISTIC

or Equivalent)

–20

–40

Binary

Counter

Digital Code

(EPROM)

Parallel-to-Serial

Conversion

DUT

(PC(PMC6M06P6/P6)6P)

–60

–80

–100

–120

10¹10²10³10⁴10⁵

Frequency (Hz)

Clock

Latch Enable

Sampling Rate = 44.1kHz x 4 (176.4kHz)

Output Frequency = 991Hz

Timing

Logic

FIGURE 4. THD + N Test Setup Diagram.

PCM66P

WDCLK DUTY CYCLE

60ns min

WDCLK is the input signal that controls when data is loaded

and how long each output is in the integrate mode. It is

therefore recommended that a 50% (high) duty cycle be

maintained on WDCLK. This will ensure that each output

will have enough time to reach its final output value, and that

the output level of each channel will be within the gain

mismatch specification. Refer to Figure 1 for exact timing

relationships of WDCLK to CLK and LRCLK and the

outputs of the PCM66P. The WDCLK can be high longer

than 50%, as long as setup and hold times shown in Figure

5 are observed and the time high is roughly equivalent for

both left and right channels.

P3 (CLK)

P4 (DATA)

15ns min

P2 (WDCLK)

P1 (LRCLK)

15ns min

FIGURE 5. PCM66P Setup and Hold Timing Diagram.

SETUP AND HOLD TIME

100µF decoupling capacitor as shown in Figure 3 should be

used regardless of how good the +5V supply is to maximize

power supply rejection. All grounds should be connected to

the analog ground plane as close to the PCM66P as possible.

The individual serial data bit shifts, the serial to parallel data

transfer, and left/right control are triggered on positive CLK

edges. The setup time required for DATA, WDCLK, and

LRCLK to be latched by the next positive going CLK is

15ns minimum. A minimum hold time of 15ns is also

required after the positive going CLK edge for each data bit

to be shifted into the serial input register. Refer to Figure 5

for the timing relationship of these signals.

FILTER CAPACITOR REQUIREMENTS

As shown in Figure 3, C_REFand V_REFSENSE should have

decoupling capacitors of 0.1µF (C₄) and 10µF (C₅) to +V_CC

respectively with no special tolerance being required. To

maximize channel separation between left and right chan-

nels, 5% 300pF capacitors (C₂and C₃) between V_COMand left

and right channel outputs are required in addition to a 5%

3µF capacitor (C₁) between V_COMand +5V. The ratio of 10k

to 1 is the important factor here for proper circuit operation.

Placement of all capacitors should be as close to the appro-

priate pins of the PCM66P as possible to reduce noise

pickup from surrounding circuitry.

MAXIMUM CLOCK RATE

The 100% tested maximum clock rate of 8.47MHz for the

PCM66P is derived by multiplying the standard audio sample

rate of 44.1kHz times eight (4X oversampling times two

channels) times the standard audio word bit length of 24

(44.1kHz x 4 x 2 x 24 = 8.47MHz). Note that this clock rate

accommodates a 24-bit word length, even though only 16

bits are actually being used.

APPLICATIONS

“STOPPED-CLOCK” OPERATION

Probably the most popular use of the PCM66P is in applica-

tions requiring single power supply operation. For example,

the PCM66P is ideal for automotive compact disk (CD) and

digital audio tape (DAT) playback units. To use a more

complex bipolar DAC requiring ±5V supplies in the +12V

application, for example, would require driving a stable

“floating” ground and regulating the +12V to +10V. The

single supply CMOS PCM66P would only require a +5V

zener diode to regulate its 50mW max supply. The outputs

could be AC coupled to the rest of the circuit for perfectly

acceptable high dynamic performance. The PCM66P is ideal

in any application requiring a minimum of additional cir-

cuitry as well as ultra-low-power CMOS performance.

The PCM66P is normally operated with a continuous clock

input signal. If the clock is to be stopped between input data

words, the last 16 bits shifted in are not actually shifted from

the serial register to the latched parallel DAC register until

the first clock after the one used to input bit 16 (LSB). This

means the data is not shifted into the DHC latch until the

start of the next 16-bit data word input, unless at least one

additional clock accompanies the 16 used to serially shift in

data in the first place. In either case, the setup and hold times

for DATA, WDCLK, and LRCLK must still be observed.

INSTALLATION

Of course, the PCM66P is the D/A converter of choice in

any application requiring very low power dissipation. Por-

table battery powered test and measurement equipment re-

quiring very low distortion digital to analog converters

would be an ideal application for the CMOS PCM66P with

its 50mW max power dissipation.

The PCM66P only requires a single +5V supply. The +5V

supply, however, is used in deriving the internal reference.

It is therefore very important that this supply be as “clean”

as possible to reduce coupling of supply noise to the outputs.

If a good analog supply is available at greater than +5V, a

zener diode can be used to obtain a stable +5V supply. A

PCM66P

PCM66P [BB]

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