TLV320AIC33IZQE [BB]
LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY; 低功耗立体声音频编解码器用于便携式音频/电话
| 型号： | TLV320AIC33IZQE |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY |
| 文件： | 总93页 (文件大小：1467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV320AIC33
SLAS480A–JANUARY 2006–REVISED JULY 2006
LOW POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
FEATURES
– Digital I/O: 1.1 V–3.6 V
•
Stereo Audio DAC
•
Packages: 5 × 5 mm 80-VFBGA;
7 × 7 mm 48-QFN
– 100-dBA Signal-to-Noise Ratio
– 16/20/24/32-Bit Data
DESCRIPTION
– Supports Rates From 8 kHz to 96 kHz
– 3D/Bass/Treble/EQ/De-emphasis Effects
Stereo Audio ADC
The TLV320AIC33 is a low power stereo audio
codec with stereo headphone amplifier, as well as
multiple inputs and outputs programmable in
single-ended or fully differential configurations.
Extensive register- based power control is included,
enabling stereo 48-kHz DAC playback as low as 14
mW from a 3.3-V analog supply, making it ideal for
portable battery-powered audio and telephony
applications.
•
•
– 92-dBA Signal-to-Noise Ratio
– Supports Rates From 8 kHz to 96 kHz
Ten Audio Input Pins
– Programmable in Single-Ended or Fully
Differential Configurations
– 3-State Capability for Floating Input
Configurations
The record path of the TLV320AIC33 contains
integrated microphone bias, digitally controlled stereo
microphone preamplifier, and automatic gain control
(AGC), with mix/mux capability among the multiple
analog inputs. The playback path includes mix/mux
capability from the stereo DAC and selected inputs,
through programmable volume controls, to the
various outputs.
•
•
Seven Audio Output Drivers
– Stereo 8-Ω, 500-mW/Channel Speaker Drive
Capability
– Stereo Fully Differential or Single-Ended
Headphone Drivers
– Fully Differential Stereo Line Outputs
– Fully Differential Mono Output
The TLV320AIC33 contains four high-power output
drivers as well as three fully differential output
drivers. The high-power output drivers are capable of
driving a variety of load configurations, including up
to four channels of single-ended 16-Ω headphones
using ac-coupling capacitors, or stereo 16-Ω
headphones in a capacitorless output configuration.
In addition, pairs of drivers can be used to drive 8-Ω
speakers in a BTL configuration at 500 mW per
channel.
Low Power: 14-mW Stereo 48-kHz Playback
With 3.3-V Analog Supply
•
•
•
•
Programmable Input/Output Analog Gains
Automatic Gain Control (AGC) for Record
Programmable Microphone Bias Level
Programmable PLL for Flexible Clock
Generation
The stereo audio DAC supports sampling rates from
8 kHz to 96 kHz and includes programmable digital
filtering in the DAC path for 3D, bass, treble,
midrange effects, speaker equalization, and
de-emphasis for 32-kHz, 44.1-kHz, and 48-kHz
rates. The stereo audio ADC supports sampling rates
•
•
Control Bus Selectable SPI or I2C
Audio Serial Data Bus Supports I2S,
Left/Right-Justified, DSP, and TDM Modes
Alternate Serial PCM/I2S Data Bus for Easy
•
Connection to Bluetooth™ Module
from
8 kHz to 96 kHz and is preceded by
•
•
•
Digital Microphone Input Support
Extensive Modular Power Control
Power Supplies:
programmable gain amplifiers providing up to
+59.5-dB analog gain for low-level microphone
inputs.
– Analog: 2.7 V–3.6 V.
– Digital Core: 1.525 V–1.95 V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MIcroStar Junior is a trademark of Texas Instruments.
Bluetooth is a trademark of Bluetooth SIG, Inc..
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLV320AIC33
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SLAS480A–JANUARY 2006–REVISED JULY 2006
DESCRIPTION (CONTINUED)
The serial control bus supports SPI or I2C protocols, while the serial audio data bus is programmable for I2S,
left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and
support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz,
with special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz
system clocks.
The TLV320AIC33 operates from an analog supply of 2.7 V–3.6 V, a digital core supply of 1.525 V–1.95 V, and
a digital I/O supply of 1.1 V–3.6 V. The device is available in 5 × 5-mm, 80-ball MIcroStar Junior™ BGA and 7 ×
7-mm, 48-lead QFN.
2
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SLAS480A–JANUARY 2006–REVISED JULY 2006
SIMPLIFIED BLOCK DIAGRAM
SDA/GPIO
SCL/GPIO
MISO/GPIO
MOSI/GPIO
SCLK/I2C_ADR1
CSEL/I2C_ADR0
SELECT
K L C W
K L C B
T U O D
N I
D
RESETB
I O V D D
D V S
S
D D V D
S S V R D
D D V R D
S S V R D
D D V R D
S _ D V A S A C
GPIO_2
GPIO_1
MCLK
V D A D _ D A C
S _ A V D S A C
V D A D _ A D C
MICBIAS
MICDET
3
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SLAS480A–JANUARY 2006–REVISED JULY 2006
PACKAGING/ORDERING INFORMATION
PACKAGE
DESIGNATOR
OPERATING
TEMPERATURE
RANGE
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE
TLV320AIC33IZQE
TLV320AIC33IZQER
TLV320AIC33IGQE
TLV320AIC33IGQER
TLV320AIC33IRGZT
TLV320AIC33IRGZR
Trays, 360
ZQE
GQE
RGZ
Tape and Reel, 3000
Trays, 360
BGA-80
QFN-48
TLV320AIC33
–40°C to 85°C
Tape and Reel, 3000
Tape and Reel, 250
Tape and Reel, 2000
PIN ASSIGNMENTS
1
1 2
1 3
4 8
J
H
G
F
E
D
C
B
A
3 7
2 4
2 5
1
2
3
4
5
6
7
8
9
3 6
48−lead QFN Package (Bottom view)
5x5mm 80−Ball BGA Package (Bottom View)
(Not to scale)
TERMINAL FUNCTIONS
TERMINAL
QFN
DESCRIPTION
BGA
BALL
NAME
A2
A1
13
14
15
MICBIAS
MIC3R
AVSS_ADC
Microphone Bias Voltage Output
MIC3 Input (Right or Multifunction)
Analog ADC Ground Supply, 0 V
C2,D2
B1,C1
D1
16,17 DRVDD
ADC Analog and Output Driver Voltage Supply, 2.7 V–3.6 V
High-Power Output Driver (Left Plus)
18
19
HPLOUT
HPLCOM
E1
High-Power Output Driver (Left Minus or Multifunctional)
Analog Output Driver Ground Supply, 0 V
High-Power Output Driver (Right Minus or Multifunctional)
High-Power Output Driver (Right Plus)
E2,F2
F1
20,21 DRVSS
22
23
24
25
26
27
HPRCOM
HPROUT
DRVDD
G1
H1
ADC Analog and Output Driver Voltage Supply, 2.7 V– 3.6 V
Analog DAC Voltage Supply, 2.7 V–3.6 V
Analog DAC Ground Supply, 0 V
J1
AVDD
G2,H2
J2
AVSS_DAC
MONO_LOP
Mono Line Output (Plus)
4
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SLAS480A–JANUARY 2006–REVISED JULY 2006
PIN ASSIGNMENTS (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
DESCRIPTION
BGA
BALL
QFN
NAME
J3
J4
J5
J6
J7
H8
28
29
30
31
32
33
MONO_LOM
LEFT_LOP
LEFT_LOM
RIGHT_LOP
RIGHT_LOM
RESET
Mono Line Output (Minus)
Left Line Output (Plus)
Left Line Output (Minus)
Right Line Output (Plus)
Right Line Output (Minus)t
Reset
General-Purpose Input/Output #2 (Input/Output) / Digital Microphone Data Input / PLL Clock Input /
Audio Serial Data Bus Bit Clock Input/Output
J8
J9
34
35
GPIO2
GPIO1
General-Purpose Input/Output #1 (Input/Output) / PLL/Clock Mux Output / Short Circuit Interrupt /
AGC Noise Flag / Digital Microphone Clock Audio Serial Data Bus Word Clock Input/Output
H9
G8
G9
F9
E9
F8
D9
E8
C9
B8
B9
A8
A9
C8
D8
A7
A6
A5
B7
B6
A4
B5
B4
A3
B3
B2
36
37
38
39
40
41
42
43
44
45
46
47
48
1
DVDD
Digital Core Voltage Supply, 1.525V – 1.95V
Master Clock Inputt
MCLK
BCLK
Audio Serial Data Bus Bit Clock (Input/Output)
Audio Serial Data Bus Word Clock (Input/Output)
Audio Serial Data Bus Data Input (Input)
WCLK
DIN
DOUT
Audio Serial Data Bus Data Output (Output)t
DVSS
Digital Core / I/O Ground Supply, 0V
Control Mode Select Pin (1=SPI, 0=I2C)
SELECT
IOVDD
MFP0
I/O Voltage Supply, 1.1V – 3.6V
Multifunction pin #0 - SPI Chip Select / GPI / I2C Address Pin #0
Multifunction pin #1 - SPI Serial Clock / GPI / I2C Address Pin #1S
Multifunction pin #2 - SPI MISO Slave Serial Data Output / GPOI
Multifunction pin #3 - SPI MOSI Slave Serial Data Input / GPI / Audio Serial Data Bus Data Input
I2C Serial Clock / GPIO
MFP1
MFP2
MFP3
SCL
2
SDA
I2C Serial Data Input/Output / GPIO
NC
No Connect
3
4
LINE1LP
LINE1LM
LINE1RP
LINE1RM
LINE2LP
LINE2LM
LINE2RP
LINE2RM
MIC3L
MICDET
MIC1 or Line1 Analog Input (Left Plus or Multifunction)
MIC1 or Line1 Analog Input (Left Minus or Multifunction)I
MIC1 or Line1 Analog Input (Right Plus or Multifunction)I
MIC1 or Line1 Analog Input (Right Minus or Multifunction)
MIC2 or Line2 Analog Input (Left Plus or Multifunction)
MIC2 or Line2 Analog Input (Left Minus or Multifunction)I
MIC2 or Line2 Analog Input (Right Plus or Multifunction)I
MIC2 or Line2 Analog Input (Right Minus or Multifunction)I
MIC3 Input (Left or Multifunction)
5
6
7
8
9
10
11
12
Microphone Detect
5
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SLAS480A–JANUARY 2006–REVISED JULY 2006
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)(2)
VALUE
–0.3 to 3.9
–0.3 to 3.9
–0.3 to 3.9
–0.3 to 2.5
–0.1 to 0.1
–0.3 V to IOVDD+0.3
–0.3 V to AVDD+0.3
-40 to +85
UNIT
V
AVDD to AVSS, DRVDD to DRVSS
AVDD to DRVSS
V
IOVDD to DVSS
V
DVDD to DVSS
V
AVDD to DRVDD
V
Digital input voltage to DVSS
Analog input voltage to AVSS
Operating temperature range
Storage temperature range
V
V
°C
°C
°C
-65 to +105
105
TJ Max
Junction temperature
Power dissipation
(TJ Max – TA) / θJA
63
θJA
Thermal impedance , BGA package
Thermal impedance, QFN package
°C/W
°C/W
38.5
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) ESD complicance tested to EIA / JESD22-A114-B and passed.
DISSIPATION RATINGS(1)
Package Type
TA = 25°C
POWER RATING
DERATING
FACTOR
TA = 75°C
POWER RATING
TA = 85°C
POWER RATING
BGA
QFN
1.27 W
2.08 W
15.9 mW/°C
26.0 mW/°C
476 mW
779 mW
317 mW
519 mW
(1) This data was taken using 2 oz. trace and copper pad that is soldered directly to a JEDEC standard 4-layer 3 in × 3 in PCB.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
AVDD,
DRVDD1
/2(1)
Analog supply voltage
2.7
3.3
3.6
V
DVDD(1) Digital core supply voltage
IOVDD(1) Digital I/O supply voltage
1.525
1.1
1.8
1.8
1.95
3.6
V
V
VI
Analog full-scale 0 dB input voltage (DRVDD1 = 3.3 V)
0.707
VRMS
kΩ
Ω
Stereo line-output load resistance
Stereo headphone-output load resistance
Digital output load capacitance
10
16
10
pF
°C
TA
Operating free-air temperature
–40
85
(1) Analog voltage values are with respect to AVSS1, AVSS2, DRVSS; digital voltage values are with respect to DVSS.
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SLAS480A–JANUARY 2006–REVISED JULY 2006
ELECTRICAL CHARACTERISTICS
At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO ADC
Input signal level (0-dB)
Single-ended input
0.707
92
VRMS
dB
Signal-to-noise ratio,
A-weighted(1)(2)
Fs = 48 kHz, 0 dB PGA gain, MIC1/LINE1 inputs
selected and AC-shorted to ground
80
Fs = 48 kHz, 1-kHz –60 dB full-scale input applied at
MIC1/LINE1 inputs, 0-dB PGA gain
Dynamic range, A-weighted(1)(2)
92
dB
dB
–90
–75
Fs = 48 kHz, 1-kHz –2dB full-scale input applied at
MIC1/LINE1 inputs, 0-dB PGA gain
THD Total harmonic distortion
0.003% 0.017%
234 Hz, 100 mVpp on AVDD, DRVDD, single-ended
input
46
Power supply rejection ratio
dB
dB
234 Hz, 100mVpp on AVDD, DRVDD, differential
input
68
1 kHz, –2 dB MIC3L to MIC3R
1 kHz, –2 dB MIC2L to MIC2R
1 kHz, –2 dB MIC1L to MIC1R
1 kHz input, 0 dB PGA gain
–80
–99
–-73
0.7
ADC channel separation
ADC gain error
dB
dB
ADC programmable gain
amplifier maximum gain
1-kHz input tone, RSOURCE < 50 Ω
59.5
0.5
20
ADC programmable gain
amplifier step size
dB
MIC1/LINE1 inputs, routed to single ADC
Input mix attenuation = 0 dB
MIC2/LINE2 inputs, input mix attenuation = 0 dB
MIC3/LINE3 inputs, input mix attenuation = 0 dB
20
20
MIC1/LINE1 inputs,
input mix attenuation = –12 dB
Input resistance
kΩ
80
80
MIC2/LINE2 inputs,
input mix attenuation = –12 dB
MIC3/LINE3 inputs,
input mix attenuation = –12 dB
80
10
0
Input capacitance
MIC1/LINE1 inputs
pF
dB
Input level control minimum
attenuation setting
Input level control maximum
attenuation setting
12
dB
dB
Input level control attenuation
step size
1.5
ADC DIGITAL DECIMATION FILTER,
Filter gain from 0 to 0.39 Fs
Filter gain at 0.4125 Fs
Fs = 48 kHz
±0.1
–0.25
–3
dB
dB
Filter gain at 0.45 Fs
dB
Filter gain at 0.5 Fs
–17.5
–75
dB
Filter gain from 0.55 Fs to 64 Fs
Filter group delay
dB
17/Fs
Sec
(1) Ratio of output level with 1-kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a
20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may
result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter
removes out-of-band noise, which, although not audible, may affect dynamic specification values.
7
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ELECTRICAL CHARACTERISTICS (continued)
At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER
MICROPHONE BIAS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.0
2.5
2.25
2.75
4
Bias voltage
Programmable settings, load = 750 Ω
V
AVDD-
0.2
Current sourcing
2.5 V setting
mA
AUDIO DAC
Differential Line output, load = 10 kΩ, 50 pF
1.414
4.0
VRMS
VPP
Full-scale differential output
voltage
0-dB gain to line outputs. DAC output common-mode
setting = 1.35 V, output level control gain = 0-dB
Signal-to-noise ratio,
A-weighted(3)
Fs = 48 kHz, 0-dB gain to line outputs, zero signal
applied, referenced to full-scale input level
90
100
100
dB
dB
Fs = 48 kHz, 0-dB gain to line outputs,
1 kHz –60 dB signal applied
Dynamic range, A-weighted
Total harmonic distortion
Fs = 48 kHz, 1 kHz 0 dB input signal applied
234 Hz, 100 mVpp on AVDD, DRVDD1/2
–93
81
–75
dB
dB
Power supply rejection ratio
DAC channel separation (left to
right)
1-kHz, 0-dB
–100
dB
DAC interchannel gain mismatch 1 kHz input, 0dB gain
0.1
dB
dB
DAC Gain Error
1 kHz input, 0dB gain
–0.4
DAC DIGITAL INTERPOLATION
FILTER
Fs = 48-kHz
Passband
Passband ripple
High-pass filter disabled
High-pass filter disabled
0.45×Fs
Hz
dB
±0.06
Transition band
0.45×Fs
0.55×Fs
0.55×Fs
7.5×Fs
Hz
Stopband
Hz
Stopband attenuation
Group delay
65
dB
21/Fs
Sec
STEREO HEADPHONE DRIVER
AC-coupled output configuration(4)
0-dB gain to high power outputs. Output
common-mode voltage setting = 1.35 V
0-dB full-scale output voltage
0.707
VRMS
First option
1.35
1.50
1.65
1.8
Programmable output common
mode voltage (applicable to Line
Outputs also)
Second option
Third option
Fourth option
V
Maximum programmable output
level control gain
9
1
dB
dB
Programmable output level
control gain step size
RL = 32 Ω
RL = 16 Ω
15
30
PO
Maximum output power
mW
dB
Signal-to-noise ratio,
A-weighted(5)
94
(3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω
single-ended load.
(4) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω
single-ended load.
(5) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to
20-kHz bandwidth.
8
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ELECTRICAL CHARACTERISTICS (continued)
At 25°C, AVDD, DRVDD, IOVDD = 3.3 V, DVDD = 1.8 V, Fs = 48-kHz, 16-bit audio data (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
–77
MAX
UNIT
1-kHz output, PO = 5 mW, RL = 32 Ω
0.014
–76
1-kHz output, PO = 10 mW, RL = 32 Ω
1-kHz output, PO = 10 mW, RL = 16 Ω
1-kHz output, PO = 20 mW, RL = 16 Ω
0.016
–73
Total harmonic distortion
dB%
0.022
–71
0.028
90
Channel separation
Power supply rejection ratio
Mute attenuation
1 kHz, 0 dB input
dB
dB
dB
217 Hz, 100 mVpp on AVDD, DRVDD1/2
1-kHz output
48
107
DIGITAL I/O
0.3 ×
IOVDD
VIL
VIH
Input low level
IIL = +5-µA
–0.3
V
V
V
V
0.7 ×
IOVDD
Input high level(6)
IIH = +5-µA
0.1 ×
IOVDD
VOL Output low level
IIH = 2 TTL loads
0.8 ×
IOVDD
VOH Output high level
IOH = 2 TTL loads
SUPPLY CURRENT
Fs = 48-kHz
AVDD+DRVDD
DVDD
3.0
2.0
2.2
1.1
4.2
1.3
1.2
1
Fs = 48-kHz, PLL off, headphone
drivers off, DAC direct mode
Stereo line playback
Mono record
Stereo record
PLL
mA
mA
mA
mA
AVDD+DRVDD
DVDD
Fs = 48-kHz, PLL and AGC off
Fs = 48-kHz, PLL and AGC off
AVDD+DRVDD
DVDD
AVDD+DRVDD
DVDD
Additional power consumed when
PLL is powered
AVDD+DRVDD
LINE2LP/RP only routed to stereo
single-ended headphones, DAC
and PLL off, no signal applied
5.6
Headphone amplifier
Power down
mA
DVDD
0
0.1
0.5
AVDD+DRVDD
DVDD
All supply voltages applied, all
blocks programmed in lowest
power state
µA
(6) When IOVDD < 1.6V, minimum VIH is 1.1V.
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SLAS480A–JANUARY 2006–REVISED JULY 2006
AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM
WCLK
td(WS)
td(DO-WS)
td(DO-BCLK)
BCLK
SDOUT
SDIN
th(DI)
ts(DI)
Figure 1. I2S/LJF/RJF Timing in Master Mode
TIMING CHARACTERISTICS(1)
All specifications typical at 25°C, DVDD = 1.8 V
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
50
MIN
MAX
td (WS)
ADWS/WCLK delay time
15
20
15
ns
ns
ns
td (DO-WS) ADWS/WCLK to DOUT delay time
50
td
BCLK to DOUT delay time
50
(DO-BCLK)
ts(DI)
th(DI)
tr
DIN setup time
DIN hold time
Rise time
10
10
6
6
ns
ns
ns
ns
30
30
10
10
tf
Fall time
(1) All timing specifications are measured at characterization but not tested at final test.
WCLK
td(WS)
td(WS)
BCLK
SDOUT
SDIN
td(DO-BCLK)
th(DI)
ts(DI)
Figure 2. DSP Timing in Master Mode
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SLAS480A–JANUARY 2006–REVISED JULY 2006
TIMING CHARACTERISTICS(1)
All specifications typical at 25°C, DVDD = 1.8 V
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
15
td (WS)
ADWS/WCLK delay time
50
50
ns
ns
ns
ns
ns
ns
td (DO-BCLK) BCLK to DOUT delay time
15
ts(DI)
th(DI)
tr
DIN setup time
DIN hold time
Rise time
10
10
6
6
30
30
10
10
tf
Fall time
(1) All timing specifications are measured at characterization but not tested at final test.
WCLK
th(WS)
ts(WS)
tL(BCLK)
td(DO-BCLK)
td(DO-WS)
BCLK
tH(BCLK)
tP(BCLK)
SDOUT
th(DI)
ts(DI)
SDIN
Figure 3. I2S/LJF/RJF Timing in Slave Mode
TIMING CHARACTERISTICS(1)
All specifications typical at 25°C, DVDD = 1.8 V
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
70
MAX
MIN
35
35
6
MAX
tH (BCLK)
tL (BCLK)
ts(WS)
BCLK high period
ns
ns
ns
ns
ns
ns
BCLK low period
70
ADWS/WCLK setup time
ADWS/WCLK hold time
10
th(WS)
10
6
td (DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only)
TBD
50
TBD
20
td
BCLK to DOUT delay time
(DO-BCLK)
ts(DI)
th(DI)
tr
DIN setup time
DIN hold time
Rise time
10
10
6
6
ns
ns
ns
ns
8
8
4
4
tf
Fall time
(1) All timing specifications are measured at characterization but not tested at final test.
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th(WS)
th(WS)
ts(WS)
ts(WS)
tL(BCLK)
td(DO-BCLK)
tH(BCLK)
tP(BCLK)
ts(DI)
Figure 4. DSP Timing in Slave Mode
TIMING CHARACTERISTICS(1)
All specifications typical at 25°C, DVDD = 1.8 V
IOVDD = 1.1 V
IOVDD = 3.3 V
PARAMETER
UNIT
MIN
70
MAX
MIN
35
35
8
MAX
tH (BCLK)
tL (BCLK)
ts(WS)
BCLK high period
ns
ns
ns
ns
ns
BCLK low period
70
ADWS/WCLK setup time
ADWS/WCLK hold time
BCLK to DOUT delay time
10
th(WS)
10
8
td
50
20
(DO-BCLK)
ts(DI)
th(DI)
tr
DIN setup time
DIN hold time
Rise time
10
10
6
6
ns
ns
ns
ns
8
8
4
4
tf
Fall time
(1) All timing specifications are measured at characterization but not tested at final test.
TYPICAL CHARACTERISTICS
-20
-30
-40
-50
-60
-70
-80
-90
-20
-30
-40
-50
-60
-70
-80
-90
Capless, VDD = 3.6 V
AC-Coupled,VDD=3.6V
AC-Coupled,VDD=2.7V
Capless,VDD=3.6V
Capless,VDD=2.7V
AC-Coupled, VDD = 2.7 V
AC-Coupled, VDD = 3.6 V
Capless, VDD = 2.7 V
0.015
0.02
0.025
0.03
0.035
0.04
Power - W
0.005 0.007 0.009 0.011 0.013 0.015 0.017 0.019 0.021 0.023 0.025
Power,W
Figure 5. Headphone Power vs THD, 16 Ω Load
Figure 6. Headphone Power vs THD, 32 Ω Load
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TYPICAL CHARACTERISTICS (continued)
0.00
-20.00
-40.00
-60.00
-80.00
-100.00
-120.00
-140.00
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Frequency - kHz
Figure 7. DAC to Line Output FFT Plot
0
-20
-40
-60
-80
-100
-120
-140
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
Frequency - kHz
Figure 8. Line Input to ADC FFT Plot
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TYPICAL CHARACTERISTICS (continued)
-10.00
-20.00
-30.00
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
VDD = 2.7 V
VDD = 3.3 V
VDD = 3.6 V
0.10
0.20
0.30
0.40
0.50
0.60
Power - W
Figure 9. Speaker Power vs THD, 8 Ω Load
3 8
3 6
3 4
3 2
3 0
2 8
2 6
0
1 0
2 0
30
40
5 0
6 0
PGA Gain Setting - dB
Figure 10. ADC SNR vs PGA Gain Setting, –65 dBFS Input
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TYPICAL CHARACTERISTICS (continued)
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
Left ADC
Right ADC
0
10
20
30
40
50
60
PGA Gain Setting - dB
Figure 11. ADC Gain Error vs PGA Gain Setting
3.5
3.4
3.3
3.2
3.1
3
MICBIAS=AVDD
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
MICBIAS=2.5V
MICBIAS=2.0V
3.3
1.9
1.8
2.7
2.8
2.9
3
3.1
3.2
3.4
3.5
3.6
AVDD - V
Figure 12. MICBIAS Output Voltage vs AVDD
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TYPICAL CHARACTERISTICS (continued)
3.2
3
MICBIAS=AVDD
2.8
2.6
2.4
2.2
2
MICBIAS=2.5V
MICBIAS=2.0V
1.8
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temp - C
Figure 13. MICBIAS Output Voltage vs Ambient Temperature
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TYPICAL CHARACTERISTICS (continued)
TYPICAL CIRCUIT CONFIGURATION
IOVDD
I2C ADDRESS
Multimedia
Processor
DBB /
Modem
Rp
R
p
AVDD
(2.7V−3.6V)
MICBIAS
AVDD_ADC
MIC3L
µF
1 kΩ
1 kΩ
AVDD_DAC
µF
0.47 µF
0.47 µF
µF
DRVDD
DRVDD
µF
µF
µF
LINE2LP
LINE2LM
µF
Handset Mic
µF
µF
IOVDD
(1.1−3.3V)
A
A
AIC33
0.47 µF
LINE1LP
LINE1LM
IOVDD
DVDD
1.525−1.95V
µF
Line In /
FM
µF
LINE1RP
LINE1RM
µF
µF
SELECT
DVSS
MONO_LOP
MONO_LOM
LINE2RP
D
Analog Baseband /
Modem
AVSS_ADC
AVSS_DAC
DRVSS
LINE2RM
VBAT
DRVSS
A
µF
560
Ω
A
PVDD
560
2 kΩ
Ω
0.47 µF
HEADSET_MIC
HEADSET_GND
Earjack mic
and
4700 pF
headset
speakers
(capless)
HEADSET_SPKR_R
HEADSET_SPKR_L
560
Ω
560
Ω
4700 pF
TLV320AIC33 Connections
PVSS
A
Stereo Speakers with Multiple Audio Processors
TPA2012D2 Class−D Spkr Amp
Figure 14. Typical Connections for Capless Headphone and External Speaker Amp
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OVERVIEW
The TLV320AIC33 is a highly flexible, low power, stereo audio codec with extensive feature integration, intended
for applications in smartphones, PDAs, and portable computing, communication, and entertainment applications.
Available in a 5x5mm 80-ball BGA (with 51 balls actually used) and 7x7mm 48-lead QFN, the product integrates
a host of features to reduce cost, board space, and power consumption in space-constrained, battery-powered,
portable applications.
The TLV320AIC33 consists of the following blocks:
•
•
•
•
•
•
•
•
Stereo audio multi-bit delta-sigma DAC (8 kHz – 96 kHz)
Stereo audio multi-bit delta-sigma ADC (8 kHz – 96 kHz)
Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, de-emphasis)
Six audio inputs
Four high-power audio output drivers (headphone/speaker drive capability)
Three fully differential line output drivers
Fully programmable PLL
Headphone/headset jack detection with interrupt
Communication to the TLV320AIC33 for control is pin-selectable (using the SELECT pin) as either SPI or I2C.
The SPI interface requires that the Slave Select signal (MFP0) be driven low to communicate with the
TLV320AIC33. Data is then shifted into or out of the TLV320AIC33 under control of the host microprocessor,
which also provides the serial data clock. The I2C interface supports both standard and fast communication
modes, and also enables cascading of up to four multiple codecs on the same I2C bus through the use of two
pins for addressing (MFP0, MFP1).
HARDWARE RESET
The TLV320AIC33 requires a hardware reset after power-up for proper operation. After all power supplies are at
their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the 'AIC33 may not respond properly to register reads/writes.
DIGITAL CONTROL SERIAL INTERFACE
The TLV320AIC33 control interface supports SPI or I2C communication protocols, with the protocol selectable
using the SELECT pin. For SPI, SELECT should be tied high; for I2C, SELECT should be tied low. It is not
recommended to change the state of SELECT during device operation.
SPI CONTROL MODE
/SS
SCLK
MOSI
MISO
RA(6)
RA(5)
RA(0)
D(7)
D(6)
D(0)
7−bit Register Address
Write
8−bit Register Data
Figure 15. SPI Write
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OVERVIEW (continued)
/SS
SCLK
MOSI
RA(6)
RA(5)
RA(0)
DON’T CARE
Read
7-Bit Register Address
MISO
D(7)
D(6)
D(0)
8-Bit Register Data
Figure 16. SPI Read
In the SPI control mode, the TLV320AIC33 uses the pins MFP0=SSB, MFP1=SCLK, MFP2=MISO, MFP3=MOSI
as a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI
port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral
devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven
onto SCLK) and initiates transmissions. The SPI slave devices (such as the TLV320AIC33) depend on a master
to start and synchronize transmissions.
A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the
slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the
MOSI pin, a byte shifts out on the MISO pin to the master shift register.
The TLV320AIC33 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI
control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its MISO pin on the
first serial clock edge. The SSB pin can remain low between transmissions; however, the TLV320AIC33 only
interprets the first 8 bits transmitted after the falling edge of SSB as a command byte, and the next 8 bits as a
data byte only if writing to a register. Reserved register bits should be written to their default values.
SPI COMMUNICATION PROTOCOL
The TLV320AIC33 is entirely controlled by registers. Reading and writing these registers is accomplished by the
use of an 8-bit command, which is sent to the MOSI pin of the part prior to the data for that register. The
command is constructed as shown in the Command Word table. The first 7 bits specify the register address
which is being written or read, from 0 to 127 (decimal). The command word ends with an R/W bit, which
specifies the direction of data flow on the serial bus. In the case of a register write, the R/W bit should be set to
0. A second byte of data is sent to the MOSI pin and contains the data to be written to the register.
Reading of registers is accomplished in similar fashion. The 8-bit command word sends the 7-bit register
address, followed by R/W bit = 1 to signify a register read is occurring,. The 8-bit register data is then clocked
out of the part on the MISO pin during the second 8 SCLK clocks in the frame.
Command Word
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR ADDR ADDR ADDR ADDR ADDR ADDR R/W
6
5
4
3
2
1
0
The register map of the TLV320AIC33 actually consists of multiple pages of registers, with each page containing
128 registers. The register at address zero on each page is used as a page-control register, and writing to this
register determines the active page for the device. All subsequent read/write operations will access the page
that is active at the time, unless a register write is performed to change the active page. Only two pages of
registers are implemented in this product, with the active page defaulting to page 0 upon device reset.
For example, at device reset, the active page defaults to page 0, and thus all register read/write operations for
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addresses 1 to 127 will access registers in page 0. If registers on page 1 must be accessed, the user must write
the 8-bit sequence 0x01 to register 0, the page control register, to change the active page from page 0 to page
1. After this write, it is recommended the user also read back the page control register, to safely ensure the
change in page control has occurred properly. Future read/write operations to addresses 1 to 127 will now
access registers in page 1. When page 0 registers must be accessed again, the user writes the 8-bit sequence
0x00 to register 0, the page control register, to change the active page back to page 0. After a recommended
read of the page control register, all further read/write operations to addresses 1 to 127 will now access page 0
registers again.
Limitation on Register Writing
When writing registers in SPI mode related to the audio output drivers mux, mix, gain configuration, etc., do not
use the auto-increment mode. In addition, between two successive writes to these registers, the host should
keep MFP0 (SPI chip select) high for at least 6.25us, to ensure that the register writes have occurred properly.
CONTINUOUS READ / WRITE OPERATION
The TLV320AIC33 includes the ability to read/write registers continuously, without needing to provide an
address for every register accessed. In SPI mode, a continuous write is executed by transitioning MFP0 (SPI
chip select) low to start the frame, sending the first 8-bit command word to read/write a particular register, and
then sending multiple bytes of register data, intended for the addressed register and those following. A
continuous read is done similarly, with multiple bytes read in from the addressed register and the following
registers on the page. When the MFP0 (SPI chip select) pin is transitioned high again, the frame ends, as does
the continuous read/write operation. A new frame must begin again with a new command word, to start the next
bus transaction.
Note that this continuous read/write operation does not continue past a page boundary. The user should not
attempt to read/write past the end of a page, since this may result in undesirable operation.
I2C CONTROL MODE
The TLV320AIC33 supports the I2C control protocol when the SELECT pin is tied low, using 7-bit addressing
and capable of both standard and fast modes. When in I2C control mode, the TLV320AIC33 can be configured
for one of four different addresses, using the multifunction pins MFP0 and MFP1, which control the two LSBs of
the device address. The 5 MSBs of the device address are fixed as 00110 and cannot be changed, while the
two LSBs are given by MFP1:MFP0. This results in four possible device addresses:
I2C slave device addresses for MFP1, MFP0 settings.
MFP1
MFP0
Device Address
0011000
0
0
1
1
0
1
0
1
0011001
0011010
0011011
I2C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pull-up resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I2C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction
of the master. Some I2C devices can act as masters or slaves, but the TLV320AIC33 can only act as a slave
device.
An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is
transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the
appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one).
Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit
into the receivers shift register.
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The I2C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.
Under normal circumstances the master drives the clock line.
Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When
communication is taking place, the bus is active. Only master devices can start a communication. They do this
by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock
line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its
counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from
HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.
After the master issues a START condition, it sends a byte that indicates which slave device it wants to
communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to
which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.) The master
sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to
the slave device.
Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit.
When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the
slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends
a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA
LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit.
A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not
present on the bus, and the master attempts to address it, it will receive a not–acknowledge because no device
is present at that address to pull the line LOW.
When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP
condition is issued, the bus becomes idle again. A master may also issue another START condition. When a
START condition is issued while the bus is active, it is called a repeated START condition.
The TLV320AIC33 also responds to and acknowledges a General Call, which consists of the master issuing a
command with a slave address byte of 00H.
SCL
DA(6)
DA(0)
RA(7)
RA(0)
D(7)
D(0)
SDA
Slave
Ack
(S)
Slave
Ack
(S)
Slave
Ack
(S)
Start
(M)
7-bit Device Address
(M)
Write
(M)
8-bit Register Address
(M)
8-bit Register Data
(M)
Stop
(M)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Figure 17. I2C Write
SCL
SDA
DA(6)
DA(0)
D(7)
D(0)
DA(6)
DA(0)
RA(7)
RA(0)
Start
(M)
Master
No Ack
(M)
Stop
(M)
7-bit Device Address
(M)
Write
(M)
Slave
Ack
(S)
8-bit Register Address
(M)
Slave
Ack
(S)
Repeat
Start
(M)
7-bit Device Address
(M)
Read
(M)
Slave
Ack
(S)
8-bit Register Data
(S)
(M) => SDA Controlled by Master
(S) => SDA Controlled by Slave
Figure 18. I2C Read
In the case of an I2C register write, if the master does not issue a STOP condition, then the device enters
auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental
register.
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Similarly, in the case of an I2C register read, after the device has sent out the 8-bit data from the addressed
register, if the master issues an ACKNOWLEDGE, the slave takes over control of SDA bus and transmit for the
next 8 clocks the data of the next incremental register.
DIGITAL AUDIO DATA SERIAL INTERFACE
Audio data is transferred between the host processor and the TLV320AIC33 via the digital audio data serial
interface, or audio bus. The audio bus on this device is very flexible, including left or right justified data options,
support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation,
very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple
devices within a system directly.
The data serial interface uses two sets of pins for communication between external devices, with the particular
pin used controlled through register programming. This configuration is shown in Figure 19 below.
WCLK
BCLK
DIN DOUT
GPIO1 GPIO2 MFP3
Audio Serial Data Bus
Figure 19. Alternate Audio Bus Mulitplexing Function
In cases where MFP3 is needed for a secondary device digital input, the TLV320AIC33 must be used in I2C
mode (when in SPI mode, MFP3 is used as the SPI bus MOSI pin and thus cannot be used here as an alternate
digital input source).
This mux capability allows the TLV320AIC33 to communicate with two separate devices with independent
I2S/PCM buses. An example of such an application is a cellphone containing a Bluetooth transceiver with
PCM/I2S interface, as shown in Figure 20. The applications processor can be connected to the WCLK, BCLK,
DIN, DOUT pins on the TLV320AIC33, while a Bluetooth device with PCM interface can be connected to the
GPIO1, GPIO2, MFP3, and DOUT pins on the TLV320AIC33. By programming the registers via I2C control, the
applications processor can determine which device is communicating with the TLV320AIC33. This is attractive in
cases where the TLV320AIC33 can be configured to communicate data with the Bluetooth device, then the
applications processor can be put into a low power sleep mode, while voice/audio transmission still occurs
between the Bluetooth device and the TLV320AIC33.
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Processor
Processor
1
2
AIC33
Possible Processor Types:
Application Processor, Multimedia Processor,
Compressed Audio Decoder, Wireless Modem,
Bluetooth Module, Additional Audio/Voice Codec
Figure 20. AIC33 Connected to Multiple Audio Devices
The audio bus of the TLV320AIC33 can be configured for left or right justified, I2S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word
clock (WCLK or GPIO1) and bit clock (BCLK or GPIO2) can be independently configured in either Master or
Slave mode, for flexible connectivity to a wide variety of processors
The word clock (WCLK or GPIO1) is used to define the beginning of a frame, and may be programmed as either
a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC
and DAC sampling frequencies.
The bit clock (BCLK or GPIO2) is used to clock in and out the digital audio data across the serial bus. When in
Master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock
mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are
generated, so in general the number of bit clocks per frame will be two times the data width. For example, if data
width is chosen as 16-bits, then 32 bit clocks will be generated per frame. If the bit clock signal in master mode
will be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data width selections be
used. These cases result in a low jitter bit clock signal being generated, having frequencies of 32×Fs or 64×Fs.
In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame will not all be
of equal period, due to the device not having a clean 40×Fs or 48×Fs clock signal readily available. The average
frequency of the bit clock signal is still accurate in these cases (being 40×Fs or 48×Fs), but the resulting clock
signal has higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC33 further includes programmability to tri-state the DOUT line during all bit clocks when valid
data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the
audio data will begin, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to
use a single audio serial data bus.
When the audio serial data bus is powered down while configured in master mode, the pins associated with the
interface will be put into a tri-state output condition.
RIGHT JUSTIFIED MODE
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
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1/fs
WCLK
BCLK
Left Channel
Right Channel
n−3
SDIN/
SDOUT
n−1 n−2
0
n−3
2
1
0
2
1
0
n−1 n−2
MSB
LSB
Figure 21. Right Justified Serial Bus Mode Operation
LEFT JUSTIFIED MODE
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
n-1 n-2 n-3
n-1 n-2 n-3
Figure 22. Left Justified Serial Data Bus Mode Operation
I2S MODE
In I2S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock.
n-2 n-3
n-1 n-2 n-3
n-1
Figure 23. I2S Serial Data Bus Mode Operation
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DSP MODE
In DSP mode, the rising edge of the word clock starts the data transfer with the left channel data first and
immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock.
1/fs
WCLK
BCLK
Left Channel
Right Channel
n−1 n−2 n−3
SDIN/
SDOUT
n−1 n−2 n−3 n−4
LSBMSB
2
1
0
2
1
0
LSBMSB
LSBMSB
Figure 24. DSP Serial Bus Mode Operation
TDM DATA TRANSFER
Time-division multiplexed data transfer can be realized in any of the above transfer modes if the 256-clock bit
clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By
changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the
serial data output driver (DOUT) can also be programmed to tri-state during all bit clocks except when valid data
is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their
data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the
bus except where it is expected based on the programmed offset.
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other
in the frame. This differs from left-justified mode, where the left and right channel data will always be a
half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both
the left and right channel data move across the frame, but still stay a full half-frame apart from each other. This
is depicted in Figure 25 for the two cases.
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DSP Mode
word
clock
bit clock
data
in/out
N-1 N-2
1
0
N-1 N-2
1
0
Right Channel Data
Left Channel Data
offset
Left Justified Mode
word
clock
bit clock
data
N-1 N-2
in/out
1
0
N-1 N-2
1
0
Right Channel Data
Left Channel Data
offset
offset
Figure 25. DSP Mode and Left Justified Modes, Showing the
Effect of a Programmed Data Word Offset
AUDIO DATA CONVERTERS
The TLV320AIC33 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at
different sampling rates in various combinations, which are described further below.
The data converters are based on the concept of an Fsref rate that is used internal to the part, and it is related
to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, Fsref will be
either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with
additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and
DAC, and also to enable high quality playback of low sampling rate data, without high frequency audible noise
being generated.
The sampling rate of the ADC and DAC can be set to Fsref/NDAC or 2×Fsref/NDAC, with NDAC being 1, 1.5, 2,
2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6.
While only one Fsref can be used at a time in the part, the ADC and DAC sampling rates can differ from each
other by using different NADC and NDAC divider ratios for each. For example, with Fsref=44.1-kHz, the DAC
sampling rate can be set to 44.1-kHz by using NDAC=1, while the ADC sampling rate can be set to 8.018-kHz
by using NADC=5.5.
When the ADCs and DACs are operating at different sampling rates, an additional word clock is required, to
provide information regarding where data begins for the ADC versus the DAC. In this case, the standard bit
clock signal (which can be supplied through the BCLK pin or through GPIO2) is used to transfer both ADC and
DAC data, the standard word clock signal is used to identify the start of the DAC data, and a separate ADC
word clock signal (denoted ADWK) is used. This clock can be supplied or generated from GPIO1 at the same
time the DAC word clock is supplied or generated from WCLK.
AUDIO CLOCK GENERATION
The audio converters in the TLV320AIC33 need an internal audio master clock at a frequency of 256×Fsref,
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC33 is shown in Figure 26.
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MCLK
BCLK
GPIO2
CLKDIV_CLKIN
PLL_CLKIN
CLKDIV_IN
PLL_IN
K = J.D
J = 1,2,3,. . . , 62,63
D= 0000,0001, . . . ,9998,9999
R= 1,2,3,4, . . . ,15,16
P= 1,2, . . . . ,7,8
Q = 3,3, . . . . ,16,17
K*R/P
2/Q
CLKDIV_OUT
PLL_OUT
1/8
PLLDIV_OUT
CODEC_CLKIN
CLKMUX_OUT
CODEC_CLK=256*Fsref
CLKOUT_IN
M =1,2,4,8
N = 2,3, . . . ., 16,17
2/(N*M)
CODEC
CLKOUT
DAC_FS
ADC_FS
GPIO1
WCLK= Fsref/ Ndac
GPIO1= Fsref/ Nadc
Ndac=1,1.5,2, . . ., 5.5,6
DAC DRA => Ndac = 0.5
Ndac=1,1.5,2, . . ., 5.5,6
ADC DRA => Nadc = 0.5
Figure 26. Audio Clock Generation Processing
The part can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a
programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK or
GPIO2 inputs can also be used to generate the internal audio master clock.
This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is
not powered up. The user can supply a separate clock to GPIO2, route this through the PLL, with the resulting
output clock driven out GPIO1, for use by other devices in the system
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies
available in the system. This device includes a highly programmable PLL to accommodate such situations
easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with
particular focus paid to the standard MCLK rates already widely used.
When the PLL is disabled,
Fsref = CLKDIV_IN / (128 × Q)
Where Q = 2, 3, …, 17
CLKDIV_IN can be MCLK, BCLK, or GPIO2, selected by register 102, bits D7-D6.
NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as
high as 50 MHz, and Fsref should fall within 39 kHz to 53 kHz.
When the PLL is enabled,
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Fsref = (PLLCLK_IN × K × R) / (2048 × P), where
P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5-D4
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal
point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of
precision).
Examples:
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified
performance:
2 MHz ≤ ( PLLCLK_IN / P ) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P ) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D≠0000, the following conditions must be satisfied to meet specified performance:
10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
Example:
MCLK = 12 MHz and Fsref = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
Example:
MCLK = 12 MHz and Fsref = 48.0 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
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The table below lists several example cases of typical MCLK rates and how to program the PLL to achieve
Fsref = 44.1 kHz or 48 kHz.
Fsref = 44.1 kHz
MCLK (MHz)
2.8224
5.6448
12.0
P
1
1
1
1
1
1
1
4
R
1
1
1
1
1
1
1
1
J
32
16
7
D
ACHIEVED FSREF
44100.00
% ERROR
0.0000
0.0000
0.0000
0.0007
0.0000
0.0000
–0.0007
0.0000
0
0
44100.00
5264
9474
6448
7040
5893
5264
44100.00
13.0
6
44099.71
16.0
5
44100.00
19.2
4
44100.00
19.68
4
44100.30
48.0
7
44100.00
Fsref = 48 kHz
MCLK (MHz)
2.048
P
1
1
1
1
1
1
1
1
1
1
4
R
1
1
1
1
1
1
1
1
1
1
1
J
48
32
24
16
12
8
D
0
ACHIEVED FSREF
48000.00
48000.00
48000.00
48000.00
48000.00
48000.00
47999.71
48000.00
48000.00
47999.79
48000.00
% ERROR
0.0000
0.0000
0.0000
0.0000
0.0000
0.0000
0.0006
0.0000
0.0000
0.0004
0.0000
3.072
0
4.096
0
6.144
0
8.192
0
12.0
1920
5618
1440
1200
9951
1920
13.0
7
16.0
6
19.2
5
19.68
4
48.0
8
The AIC33 can also output a separate clock on the GPIO1 pin. If the PLL is being used for the audio data
converter clock, the M and N settings can be used to provide a divided version of the PLL output. If the PLL is
not being used for the audio data converter clock, the PLL can still be enabled to provide a completely
independent clock output on GPIO1. The formula for the GPIO1 clock output when PLL is enabled and
CLKMUX_OUT is 0 is:
GPIO1 = (PLLCLK_IN× 2 × K × R) / (M × N × P)
When CLKMUX_OUT is 1, regardless of whether PLL is enabled or disabled, the input to the clock output
divider can be selected as MCLK, BCLK, or GPIO2. Is this case, the formula for the GPIO1 clock is:
GPIO1 = (CLKDIV_IN × 2) / (M × N), where
M = 1, 2, 4, 8
N = 2, 3, …, 17
CLKDIV_IN can be BCLK, MCLK, or GPIO2, selected by page 0, register 102, bits D7-D6
STEREO AUDIO ADC
The TLV320AIC33 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times
oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from
8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in
operation, the device requires an audio master clock be provided and appropriate audio clock generation be
setup within the part.
In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to
support the case where only mono record capability is required. In addition, both channels can be fully powered
or entirely powered down.
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The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an
initial sampling rate of 128 Fs to the final output sampling rate of Fs. The decimation filter provides a linear
phase output response with a group delay of 17/Fs. The –3 dB bandwidth of the decimation filter extends to 0.45
Fs and scales with the sample rate (Fs). The filter has minimum 75dB attenuation over the stopband from 0.55
Fs to 64 Fs. Independent digital highpass filters are also included with each ADC channel, with a corner
frequency that can be independently set to three different settings or can be disabled entirely.
Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering,
requirements for analog anti-aliasing filtering are very relaxed. The TLV320AIC33 integrates a second order
analog anti-aliasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter,
provides sufficient anti-aliasing filtering without requiring additional external components.
The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to
59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that
only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on
the register programming (see registers Page-0/Reg-19 and 22). This soft-stepping ensures that volume control
changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and upon
power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the
gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled
by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part
after the ADC power down register is written to ensure the soft-stepping to mute has completed. When the ADC
powerdown flag is no longer set, the audio master clock can be shut down.
AUTOMATIC GAIN CONTROL (AGC)
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally
constant output signal amplitude when recording speech signals (it can be fully disabled if not desired). This
circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when
a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has
several programmable settings, including target gain, attack and decay time constants, noise threshold, and
maximum PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The
algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a
measure of the nominal amplitude of the output signal.
Note that completely independent AGC circuitry is included with each ADC channel with entirely independent
control over the algorithm from one channel to the next. This is attractive in cases where two microphones are
used in a system, but may have different placement in the end equipment and require different dynamic
performance for optimal system operation.
Target gain represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC33 allows programming of eight different target gains, which can be programmed from –5.5 dB
to –24 dB relative to a full-scale signal. Since the device reacts to the signal absolute average and not to peak
levels, it is recommended that the larger gain be set with enough margin to avoid clipping at the occurrence of
loud sounds.
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 8 ms to 20 ms.
Decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied
in the range from 100 ms to 500 ms.
Noise gate threshold determines the level below which if the input speech average value falls, AGC considers
it as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every FS and sets the noise threshold
flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This
ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm
is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This
operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling
between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is
set, the status of gain applied by the AGC and the saturation flag should be ignored.
Maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the
AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than
programmed noise threshold. It can be programmed from 0 dB to +59.5 dB in steps of 0.5 dB.
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Input
Signal
Output
Signal
AGC
Gain
Attack
Time
Decay Time
Figure 27. Typical Operation of the AGC Algorithm During Speech Recording
Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time
constants are achieved using the Fsref value programmed in the control registers. However, if the Fsref is set in
the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a
different Fsref in practice, then the time constants would not be correct.
STEREO AUDIO DAC
The TLV320AIC33 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each channel
of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multi-bit digital
delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced
performance at low sampling rates through increased oversampling and image filtering, thereby keeping
quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the
audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 × Fsref and
changing the oversampling ratio as the input sample rate is changed. For an Fsref of 48 kHz, the digital
delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated
within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly,
for an Fsref rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.
The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is
enabled in the DAC.
Allowed Q values = 4, 8, 9, 12, 16
Q values where equivalent Fsref can be achieved by turning on PLL
Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16.0 and PLL enabled)
Q = 10, 14 (set P = 5, 7 and K = 8.0 and PLL enabled)
DIGITAL AUDIO PROCESSING
The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment,
speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable
digital filter block with fully programmable coefficients (see Page-1/Reg-21-26 for left channel, Page-1/Reg-47-52
for right channel). If de-emphasis is not required in a particular application, this programmable filter block can be
used for some other purpose. The de-emphasis filter transfer function is given by:
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*1
N0 ) N1 z
H(z) +
*1
32768 * D1 z
(1)
where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that
should be loaded to implement standard de-emphasis filters are given in Table 1.
Table 1. De-Emphasis Coefficients for Common Audio Sampling Rates
SAMPLING FREQUENCY
32-kHz
N0
N1
D1
16950
15091
14677
–1220
–2877
–3283
17037
20555
21374
44.1-kHz
48-kHz(1)
(1) Default de-emphasis coefficients.
In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth order digital IIR
filter with programmable coefficients (one set per channel). This filter is implemented as cascade of two biquad
sections with frequency response given by:
N0 ) 2 N1 z*1 ) N2 z*2
N3 ) 2 N4 z*1 ) N5 z*2
ǒ
Ǔǒ
Ǔ
32768 2 D1 z*1 D2 z*2 32768 2 D4 z*1 D5 z*2
(2)
The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure
of the filtering when configured for independent channel processing is shown below in Figure 28, with LB1
corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly
corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 and
RB2 filters refer to the first and second right-channel biquad filters, respectively.
LB1
LB2
RB1
RB2
Figure 28. Structure of the Digital Effects Processing for Independent Channel Processing
The coefficients for this filter implement a variety of sound effects, with bass-boost or treble boost being the most
commonly used in portable audio applications. The default N and D coefficients in the part are given in Table 2
and implement a shelving filter with 0-dB gain from DC to approximately 150 Hz, at which point it rolls off to a
3-dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D
coefficients are represented by 16-bit two’s complement numbers with values ranging from –32768 to 32767.
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Table 2. Default Digital Effects Processing Filter Coefficients,
When in Independent Channel Processing Configuration
Coefficients
N0 = N3
N1 = N4
N2 = N5
D1 = D4
D2 = D5
27619
-27034
26461
32131
-31506
The digital processing also includes capability to implement 3-D processing algorithms by providing means to
process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo
output playback. The architecture of this processing mode, and the programmable filters available for use in the
system, is shown in Figure 29. Note that the programmable attenuation block provides a method of adjusting the
level of 3-D effect introduced into the final stereo output. This combined with the fully programmable biquad
filters in the system enables the user to fully optimize the audio effects for a particular system and provide
extensive differentiation from other systems using the same device.
L
LB2
RB2
TOLEFTCHANNEL
TO RIGHT CHANNEL
LB1
Atten
R
Figure 29. Architecture of the Digital Audio Processing When 3-D Effects are Enabled
It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
While new coefficients are being written to the device over the control port, it is possible that a filter using
partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable
audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of
effects can be entirely avoided.
DIGITAL INTERPOLATION FILTER
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/Fs. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still
audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter is designed to maintain at least 65-dB rejection of images that land below 7.455 Fs. In order to utilize the
programmable interpolation capability, the Fsref should be programmed to a higher rate (restricted to be in the
range of 39 kHz to 53 kHz when the PLL is in use), and the actual Fs is set using the NDAC divider. For
example, if Fs = 8 kHz is required, then Fsref can be set to 48 kHz, and the DAC Fs set to Fsref/6. This ensures
that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.
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DELTA-SIGMA AUDIO DAC
The stereo audio DAC incorporates a third order multi-bit delta-sigma modulator followed by an analog
reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise
shaping techniques. The analog reconstruction filter design consists of a 6-tap analog FIR filter followed by a
continuous time RC filter. The analog FIR operates at a rate of 128 × Fsref (6.144 MHz when Fsref = 48 kHz,
5.6448 MHz when Fsref = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive
clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.
AUDIO DAC DIGITAL VOLUME CONTROL
The audio DAC includes a digital volume control block which implements a programmable digital gain. The
volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for
each channel. The volume level of both channels can also be changed simultaneously by the master volume
control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by
one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can
be slowed to one step per two input samples through a register bit.
Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be
important if the host wishes to mute the DAC before making a significant change, such as changing sample
rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit
that alerts the host when the part has completed the soft-stepping and the actual volume has reached the
desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is
enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this
flag is set, the internal soft-stepping process and power down sequence is complete, and the MCLK can then be
stopped if desired.
The TLV320AIC33 also includes functionality to detect when the user switches on or off the de-emphasis or
digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the
digital effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output
due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or down the
DAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired
volume level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the
circuitry.
ANALOG OUTPUT COMMON-MODE ADJUSTMENT
The output common-mode voltage and output range of the analog output are determined by an internal bandgap
reference, in contrast to other codecs that may use a divided version of the supply. This scheme is used to
reduce the coupling of noise that may be on the supply (such as 217-Hz noise in a GSM cellphone) into the
audio signal path.
However, due to the possible wide variation in analog supply range (2.7 V – 3.6 V), an output common-mode
voltage setting of 1.35 V, which would be used for a 2.7 V supply case, will be overly conservative if the supply
is actually much larger, such as 3.3 V or 3.6 V. In order to optimize device operation, the TLV320AIC33 includes
a programmable output common-mode level, which can be set by register programming to a level most
appropriate to the actual supply range used by a particular customer. The output common-mode level can be
varied among four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to
1.8 V (most appropriate for high supply ranges, near 3.6 V). Note that there is also some limitation on the range
of DVDD voltage as well in determining which setting is most appropriate.
Table 3. Appropriate Settings
CM SETTING
1.35
RECOMMENDED AVDD, DRVDD
2.7 V – 3.6 V
RECOMMENDED DVDD
1.525 V – 1.95 V
1.65 V – 1.95 V
1.8 V – 1.95 V
1.95 V
1.50
3.0 V – 3.6 V
1.65 V
1.8 V
3.3 V – 3.6 V
3.6 V
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AUDIO DAC POWER CONTROL
The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can
be powered up or down independently. This provides power savings when only a mono playback stream is
needed.
AUDIO ANALOG INPUTS
The TLV320AIC33 includes ten analog audio input pins, which can be configured as up to four fully-differential
pair plus one single-ended pair of audio inputs, or up to six single-ended audio inputs. . These pins connect
through series resistors and switches to the virtual ground terminals of two fully differential opamps (one per
ADC/PGA channel). By selecting to turn on only one set of switches per opamp at a time, the inputs can be
effectively muxed to each ADC PGA channel.
By selecting to turn on multiple sets of switches per opamp at a time, mixing can also be achieved. Mixing of
multiple inputs can easily lead to PGA outputs that exceed the range of the internal opamps, resulting in
saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the user should take
adequate precautions to avoid such a saturation case from occurring. In general, the mixed signal should not
exceed 2 Vpp (single-ended) or 4 Vpp (differential).
In most mixing applications, there is also a general need to adjust the levels of the individual signals being
mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal
generally should be amplified to a level comparable to the large signal before mixing. In order to accommodate
this need, the TLV320AIC33 includes input level control on each of the individual inputs before they are mixed or
muxed into the ADC PGAs, with gain programmable from 0 dB to –12 dB in 1.5 dB steps. Note that this input
level control is not intended to be a volume control, but instead used occasionally for level setting. Soft-stepping
of the input level control settings is implemented in this device, with the speed and functionality following the
settings used by the ADC PGA for soft-stepping.
The TLV320AIC33 supports the ability to mix up to three fully-differential analog inputs into each ADC PGA
channel. Figure 30 shows the mixing configuration for the left channel, which can mix the signals
LINE1LP-LINE1LM, LINE2LP-LINE2LM, and LINE1RP-LINE1RM
GAIN=0,−1.5,−3,..,−12dB,MUTE
LINE1LP
LINE1LM
GAIN=0,−1.5,−3,..,−12dB, MUTE
LINE2LP
TO LEFT ADC
PGA
LINE2LM
GAIN=0,−1.5,−3,..,−12dB,MUTE
LINE1RP
LINE1RM
Figure 30. Left Channel Fully-Differential Analog Input Mixing Configuration
Three fully-differential analog inputs can similarly be mixed into the right ADC PGA as well, consisting of
LINE1RP-LINE1RM, LINE2RP-LINE2RM, and LINE1LP-LINE1LM. Note that it is not necessary to mix all three
fully-differential signals if this is not desired – unnecessary inputs can simply be muted using the input level
control registers.
Inputs can also be selected as single-ended instead of fully-differential, and mixing or muxing into the ADC
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PGAs is also possible in this mode. It is not possible, however, for an input pair to be selected as
fully-differential for connection to one ADC PGA and simultaneously selected as single-ended for connection to
the other ADC PGA channel. However, it is possible for an input to be selected or mixed into both left and right
channel PGAs, as long as it has the same configuration for both channels (either both single-ended or both
fully-differential).
Figure 31 shows the single-ended mixing configuration for the left channel ADC PGA, which enables mixing of
the signals LINE1LP, LINE2LP, LINE1RP, MIC3L, and MIC3R. The right channel ADC PGA mix is similar,
enabling mixing of the signals LINE1RP, LINE2RP, LINE1LP, MIC3L, and MIC3R.
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE1LP/MIC1L
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE2L/MIC2LP
GAIN=0,-1.5,-3,..,-12dB,MUTE
TO LEFT ADC
PGA
LINE1R/MIC1RP
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE3L/MIC3L
GAIN=0,-1.5,-3,..,-12dB,MUTE
LINE3R/MIC3R
Figure 31. Left Channel Single-Ended Analog Input Mixing Configuration
ANALOG INPUT BYPASS PATH FUNCTIONALITY
The TLV320AIC33 includes the additional ability to route some analog input signals past the integrated data
converters, for mixing with other analog signals and then direction connection to the output drivers. This
capability is useful in a cellphone, for example, when a separate FM radio device provides a stereo analog
output signal that needs to be routed to headphones. The TLV320AIC33 supports this in a low power mode by
providing a direct analog path through the device to the output drivers, while all ADCs and DACs can be
completely powered down to save power.
For fully-differential inputs, the TLV320AIC33 provides the ability to pass the signals LINE2LP-LINE2LM and
LINE2RP-LINE2RM to the output stage directly. If in single-ended configuration, the device can pass the signal
LINE2LP and LINE2RP to the output stage directly.
ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
In addition to the input bypass path described above, the TLV320AIC33 also includes the ability to route the
ADC PGA output signals past the ADC, for mixing with other analog signals and then direction connection to the
output drivers. These bypass functions are described in more detail in the sections on output mixing and output
driver configurations.
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INPUT IMPEDANCE AND VCM CONTROL
The TLV320AIC33 includes several programmable settings to control analog input pins, particularly when they
are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a
tri-state condition, such that the input impedance seen looking into the device is extremely high. Note, however,
that the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any
voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS,
these protection diodes will begin conducting current, resulting in an effective impedance that no longer appears
as a tri-state condition.
Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input
voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the need
for them to charge up suddenly when the input is changed from being unselected to selected for connection to
an ADC PGA. This option is controlled in Page-0/Reg-20 and 23. The user should ensure this option is disabled
when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, since it
can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320AIC33 should be ac-coupled to analog input sources, the
only exception to this generally being if an ADC is being used for DC voltage measurement. The ac-coupling
capacitor will cause a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of
0-dB, and increasing to approximately 80-kΩ when the input level control is set at –12 dB. For example, using a
0.1 µF ac-coupling capacitor at an analog input will result in a highpass filter pole of 80 Hz when the 0 dB input
level control setting is selected.
MICBIAS GENERATION
The TLV320AIC33 includes a programmable microphone bias output voltage (MICBIAS), capable of providing
output voltages of 2.0 V or 2.5 V (both derived from the on-chip bandgap voltage) with 4-mA output current
drive. In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch,
or it can be powered down completely when not needed, for power savings. This function is controlled by
register programming in Page-0/Reg-25.
DIGITAL MICROPHONE CONNECTIVITY
The TLV320AIC33 includes support for connection of a digital microphone to the device by routing the digital
signal directly into the ADC digital decimation filter, where it is filtered, downsampled, and provided to the host
processor over the audio data serial bus.
When digital microphone mode is enabled, the TLV320AIC33 provides an oversampling clock output for use by
the digital microphone to transmit its data. The TLV320AIC33 includes the capability to latch the data on either
the rising, falling, or both edges of this supplied clock, enabling support for stereo digital microphones.
In this mode, the oversampling ratio of the digital mic modulator can be programmed as 128, 64 or 32 times the
ADC sample rate, ADCFS. The GPIO1 pin will output the serial oversampling clock at the programmed rate.
TLV320AIC33 latches the data input on GPIO2 as the Left and Right channel digital microphone data. For the
Left channel input, GPIO2 will be sampled on the rising edge of the clock, and for the Right channel input,
GPIO2 will be sampled on the falling edge of the clock. If a single digital mic channel is needed then the
corresponding ADC channel should be powered up, and the unused channel should be powered down. When
digital microphone mode is enabled, neither ADC can be used for digitizing analog inputs.
ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
The TLV320AIC33 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load.
The output stage design leading to the fully differential line output drivers is shown in Figure 32 and Figure 33.
This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond
that already provided by the PGA gain and the DAC digital volume control.
The LINE2L/R signals refer to the signals that travel through the analog input bypass path to the output stage.
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The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to
the output stage. Note that since both left and right channel signals are routed to all output drivers, a mono mix
of any of the stereo signals can easily be obtained by setting the volume controls of both left and right channel
signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix as well through
register control.
DAC_L1
DAC_L
DAC_L2
DAC_L3
STEREO
AUDIO
DAC
DAC_R1
DAC_R2
DAC_R3
DAC_R
LINE2L
LINE2R
PGA_L
VOLUME
CONTROLS,
MIXING
LEFT_LOP
LEFT_LOM
PGA_R
DAC_L1
DAC_R1
Gain = 0dB to +9dB,
Mute
DAC_L3
LINE2L
LINE2R
PGA_L
VOLUME
CONTROLS,
MIXING
RIGHT_LOP
RIGHT_LOM
PGA_R
DAC_L1
DAC_R1
Gain = 0dB to +9 dB,
Mute
DAC_R3
LINE2L
LINE2R
PGA_L
MONO_LOP
MONO_LOM
VOLUME
CONTROLS,
MIXING
PGA_R
DAC_L1
DAC_R1
Gain = 0dB to +9dB,
Mute
Figure 32. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers
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0dB to -78dB
0dB to -78dB
0dB to -78dB
0dB to -78dB
0dB to -78dB
0dB to -78dB
LINE2L/MIC2L
LINE2R/MIC2R
PGA_L
+
PGA_R
DAC_L1
DAC_R1
Figure 33. Detail of the Volume Control and Mixing Function Shown in Figure 28 and Figure 17
The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based
on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC
output is only needed at the stereo line outputs, then it is recommended to use the routing through path
DAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher quality output performance,
but also in lower power operation, since the analog volume controls and mixing blocks ahead of these drivers
can be powered down.
If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to
LEFT_LOP/M, RIGHT_LOP/M, and MONO_LOP/M) or must be mixed with other analog signals, then the DAC
outputs should be switched through the DAC_L1/R1 path. This option provides the maximum flexibility for
routing of the DAC analog signals to the output drivers
The TLV320AIC33 includes an output level control on each output driver with limited gain adjustment from 0 dB
to 9 dB. The output driver circuitry in this device are designed to provide a low distortion output while playing
fullscale stereo DAC signals at a 0dB gain setting. However, a higher amplitude output can be obtained at the
cost of increased signal distortion at the output. This output level control allows the user to make this tradeoff
based on the requirements of the end equipment. Note that this output level control is not intended to be used
as a standard output volume control. It is expected to be used only sparingly for level setting, i.e., adjustment of
the fullscale output range of the device.
Each differential line output driver can be powered down independently of the others when it is not needed in the
system. When placed into powerdown through register programming, the driver output pins will be placed into a
tri-stated, high-impedance state.
ANALOG HIGH POWER OUTPUT DRIVERS
The TLV320AIC33 includes four high power output drivers with extensive flexibility in their usage. These output
drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and they
can be used in pairs to drive up to 500 mW into an 8-Ω load connected in bridge-terminated load (BTL)
configuration between two driver outputs.
The high power output drivers can be configured in a variety of ways, including:
1. driving up to two fully differential output signals
2. driving up to four single-ended output signals
3. driving two single-ended output signals, with one or two of the remaining drivers driving a fixed VCM level,
for a pseudo-differential stereo output
4. driving one or two 8-Ω speakers connected BTL between pairs of driver output pins
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5. driving stereo headphones in single-ended configuration with two drivers, while the remaining two drivers are
connected in BTL configuration to an 8-Ω speaker.
The output stage architecture leading to the high power output drivers is shown in Figure 34, with the volume
control and mixing blocks being effectively identical to that shown in Figure 33. Note that each of these drivers
have a output level control block like those included with the line output drivers, allowing gain adjustment up to
+9dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as a
standard volume control, but instead is included for additional fullscale output signal level control.
Two of the output drivers, HPROUT and HPLOUT, include a direct connection path for the stereo DAC outputs
to be passed directly to the output drivers and bypass the analog volume controls and mixing networks, using
the DAC_L2/R2 path. As in the line output case, this functionality provides the highest quality DAC playback
performance with reduced power dissipation, but can only be utilized if the DAC output does not need to route to
multiple output drivers simultaneously, and if mixing of the DAC output with other analog signals is not needed.
This direction connection path will attenuate the signal by a factor of 1dB.
LINE2LP
LINE2RP
VOLUME
PGA_L
Volume Level 0dB to
+9dB, mute
CONTROLS,
MIXING
HPLOUT
PGA_R
DAC_L1
DAC_R1
DAC_L2
LINE2LM
LINE2RM
VOLUME
CONTROLS,
Volume Level 0 dB to
+9dB, mute
HPLCOM
VCM
PGA_L
PGA_R
MIXING
DAC_L1
DAC_R1
LINE2LM
LINE2RP
VOLUME
CONTROLS,
MIXING
PGA_L
PGA_R
Volume Level 0 dB
to +9dB, mute
VCM
HPRCOM
DAC_L1
DAC_R1
DAC_R2
LINE2LM
LINE2RM
PGA_L
PGA_R
VOLUME
CONTROLS,
MIXING
Volume Level 0dB to
+9dB, mute
HPROUT
DAC_L1
DAC_R1
Figure 34. Architecture of the output stage leading to the high power output drivers
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The high power output drivers include additional circuitry to avoid artifacts on the audio output during power-on
and power-off transient conditions. The user should first program the type of output configuration being used in
Page-0/Reg-14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The
power-up delay time for the high power output drivers is also programmable over a wide range of time delays,
from instantaneous up to 4-sec, using Page-0/Reg-42.
When these output drivers are powered down, they can be placed into a variety of output conditions based on
register programming. If lowest power operation is desired, then the outputs can be placed into a tri-state
condition, and all power to the output stage is removed. However, this generally results in the output nodes
drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results
in a longer delay requirement to avoid output artifacts during driver power-on. In order to reduce this required
power-on delay, the TLV320AIC33 includes an option for the output pins of the drivers to be weakly driven to the
VCM level they would normally rest at when powered with no signal applied. This output VCM level is
determined by an internal bandgap voltage reference, and thus results in extra power dissipation when the
drivers are in powerdown. However, this option provides the fastest method for transitioning the drivers from
powerdown to full power operation without any output artifact introduced.
The device includes a further option that falls between the other two – while it requires less power drawn while
the output drivers are in powerdown, it also takes a slightly longer delay to power-up without artifact than if the
bandgap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a
voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage will not
match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a
much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output
voltage options are controlled in Page-0/Reg-42.
The high power output drivers can also be programmed to power up first with the output level control in a highly
attenuated state, then the output driver will automatically slowly reduce the output attenuation to reach the
desired output level setting programmed. This capability is enabled by default but can be enabled in
Page-0/Reg-40.
SHORT CIRCUIT OUTPUT PROTECTION
The TLV320AIC33 includes programmable short-circuit protection for the high power output drivers, for
maximum flexibility in a given application. By default, if these output drivers are shorted, they will automatically
limit the maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device
from an over-current condition. In this mode, the user can read Page-0/Reg-95 to determine whether the part is
in short-circuit protection or not, and then decide whether to program the device to power down the output
drivers. However, the device includes further capability to automatically power down an output driver whenever it
does into short-circuit protection, without requiring intervention from the user. In this case, the output driver will
stay in a power down condition until the user specifically programs it to power down and then power back up
again, to clear the short-circuit flag.
JACK / HEADSET DETECTION
The TLV320AIC33 includes extensive capability to monitor a headphone, microphone, or headset jack,
determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wired
to the plug. Figure 35 shows one configuration of the device that enables detection and determination of headset
type when a pseudo-differential (capless) stereo headphone output configuration is used. The registers used for
this function are Page-0/Reg 14, 37, 38, and 13. The type of headset detected can be read back from
Page-0/Reg-13. Note that for best results, it is recommended to select a MICBIAS value as high as possible,
and to program the output driver common-mode level at a 1.35V or 1.5V level.
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AVDD
To Detection block
MICBIAS
MICDET
Stereo
g
s
s
s
s
MIC3(L/R)
Cellular
g
g
m
m
HPLOUT
HPROUT
Stereo +
Cellular
s
m = mic
HPRCOM
HPLCOM
To
s = speaker
detection
block
g = ground/midbias
1.35
Figure 35. Configuration of device for jack detection using a pseudo-differential (capless) headphone
output connection.
A modified output configuration used when the output drivers are ac-coupled is shown in Figure 36. Note that in
this mode, the device cannot accurately determine the type of headset inserted if a mono or stereo headphone.
AVDD
MICBIAS
Stereo
g
s
s
s
s
MICDET
To Detection block
MIC3(L/R)
g
g
m
m
Cellular
HPLOUT
HPROUT
Stereo +
Cellular
s
m = mic
s = speaker
g = ground/midbias
Figure 36. Configuration of device for jack detection using an ac-coupled stereo headphone output
connection.
An output configuration for the case of the outputs driving fully differential stereo headphones is shown in
Figure 37. In this mode there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to
ground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode to
function properly, short-circuit detection should be enabled and configured to power-down the drivers if a
short-circuit is detected. The registers that control this functionality are in Page-0/Reg-38/Bit-D2-D1.
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This switch closes when
jack is removed
MICDET
To Detection block
HPLOUT
HPLCOM
HPRCOM
HPROUT
Figure 37. Configuration of device for jack detection using a fully differential stereo headphone output
connection.
GENERAL PURPOSE I/O
AIC33 has two dedicated pins for General Purpose IO. These pins can be used to read status of external signals
through register read when configured as General Purpose Input. When configured as General Purpose Output ,
these pins can also drive logic high or low. Besides these standard GPIO functions, these pins can also be used
in a variety of ways such as output for internal clocks and interrupt signals. AIC33 generates a variety of
interrupts of use to the host processor such interrupts on jack detection, button press, short circuit detection and
AGC noise detection. All these interrupts can be routed individually to the GPIO pins or can be combined by a
logical OR. In case of a combined interrupt, user can read an internal status register to find the actual cause of
interrupt. When configured as interrupt, AIC33 also offers the flexibility of generating a single pulse or a train of
pulses till the interrupt status register is read by the user.
CONTROL REGISTERS
The control registers for the TLV320AIC33 are described in detail below. All registers are 8 bit in width, with D7
referring to the most significant bit of each register, and D0 referring to the least significant bit.
Page 0 / Register 0:
Page Select Register
BIT(1)
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D1
D0
X
0000000 Reserved, write only zeros to these register bits
R/W
0
Page Select Bit
Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a
one to this bit sets Page-1 as the active page for following register accesses. It is recommended
that the user read this register bit back after each write, to ensure that the proper page is being
accessed for future register read/writes.
(1) When resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to
the registers instead of using software reset.
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Page 0 / Register 1:
Software Reset Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
W
0
Software Reset Bit
0 : Don’t Care
1 : Self clearing software reset
D6–D0
W
0000000 Reserved; don’t write
Page 0 / Register 2:
Codec Sample Rate Select Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
ADC Sample Rate Select
0000: ADC Fs = Fsref/1
0001: ADC Fs = Fsref/1.5
0010: ADC Fs = Fsref/2
0011: ADC Fs = Fsref/2.5
0100: ADC Fs = Fsref/3
0101: ADC Fs = Fsref/3.5
0110: ADC Fs = Fsref/4
0111: ADC Fs = Fsref/4.5
1000: ADC Fs = Fsref/5
1001: ADC Fs = Fsref/5.5
1010: ADC Fs = Fsref / 6
1011–1111: Reserved, do not write these sequences.
D3-D0
R/W
0000
DAC Sample Rate Select
0000 : DAC Fs = Fsref/1
0001 : DAC Fs = Fsref/1.5
0010 : DAC Fs = Fsref/2
0011 : DAC Fs = Fsref/2.5
0100 : DAC Fs = Fsref/3
0101 : DAC Fs = Fsref/3.5
0110 : DAC Fs = Fsref/4
0111 : DAC Fs = Fsref/4.5
1000 : DAC Fs = Fsref/5
1001: DAC Fs = Fsref/5.5
1010: DAC Fs = Fsref / 6
1011–1111 : Reserved, do not write these sequences.
Page 0 / Register 3:
PLL Programming Register A
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PLL Control Bit
0: PLL is disabled
1: PLL is enabled
D6–D3
R/W
0010
PLL Q Value
0000: Q = 16
0001 : Q = 17
0010 : Q = 2
0011 : Q = 3
0100 : Q = 4
…
1110: Q = 14
1111: Q = 15
D2–D0
R/W
000
PLL P Value
000: P = 8
001: P = 1
010: P = 2
011: P = 3
100: P = 4
101: P = 5
110: P = 6
111: P = 7
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Page 0 / Register 4:
PLL Programming Register B
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D2
R/W
000001
PLL J Value
000000: Reserved, do not write this sequence
000001: J = 1
000010: J = 2
000011: J = 3
…
111110: J = 62
111111: J = 63
D1–D0
R/W
00
Reserved, write only zeros to these bits
Page 0 / Register 5:
PLL Programming Register C(1)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
00000000 PLL D value – Eight most significant bits of a 14-bit unsigned integer valid values for D are from
zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be
written into these registers that would result in a D value outside the valid range.
(1) Note that whenever the D value is changed, register 5 should be written, immediately followed by register 6. Even if only the MSB or
LSB of the value changes, both registers should be written.
Page 0 / Register 6:
PLL Programming Register D
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D2
R/W
00000000 PLL D value – Six least significant bits of a 14-bit unsigned integer valid values for D are from
zero to 9999, represented by a 14-bit integer located in Page-0/Reg-5-6. Values should not be
written into these registers that would result in a D value outside the valid range.
D1-D0
R
00
Reserved, write only zeros to these bits.
Page 0 / Register 7:
Codec Datapath Setup Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Fsref setting
This register setting controls timers related to the AGC time constants.
0: Fsref = 48-kHz
1: Fsref = 44.1-kHz
D6
R/W
0
ADC Dual rate control
0: ADC dual rate mode is disabled
1: ADC dual rate mode is enabled
Note: ADC Dual Rate Mode must match DAC Dual Rate Mode
D5
R/W
R/W
0
DAC Dual Rate Control 0: DAC dual rate mode is disabled 1: DAC dual rate mode is enabled
D4–D3
00
Left DAC Datapath Control
00: Left DAC datapath is off (muted)
01: Left DAC datapath plays left channel input data
10: Left DAC datapath plays right channel input data
11: Left DAC datapath plays mono mix of left and right channel input data
D2–D1
D0
R/W
R/W
00
0
Right DAC Datapath Control
00: Right DAC datapath is off (muted)
01: Right DAC datapath plays right channel input data
10: Right DAC datapath plays left channel input data
11: Right DAC datapath plays mono mix of left and right channel input data
Reserved. Only write zero to this register.
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Page 0 / Register 8:
Audio Serial Data Interface Control Register A
BIT
READ/ RESET
WRITE VALUE
DESCRIPTION
D7
R/W
R/W
R/W
R/W
0
0
0
0
Bit Clock Directional Control
0: Bit clock is an input (slave mode)
1: Bit clock is an output (master mode)
D6
D5
D4
Word Clock Directional Control
0: Word clock is an input (slave mode)
1: Word clock is an output (master mode)
Serial Output Data Driver (DOUT) 3-state control
0: Do not 3-state DOUT when valid data is not being sent
1: 3-state DOUT when valid data is not being sent
Bit/ Word Clock Drive Control
0:
1:
Bit clock and word clock will not be transmitted when in master mode if codec is powered down
Bit clock and word clock will continue to be transmitted when in master mode, even if codec is
powered down
D3
D2
R/W
R/W
0
0
Reserved. Only write zero to this bit.
3-D Effect Control
0: Disable 3-D digital effect processing
1: Enable 3-D digital effect processing
D1-D0
R/W
00
Digital Microphone Functionality Control
00: Digital microphone support is disabled
01: Digital microphone support is enabled with an oversampling rate of 128
10: Digital microphone support is enabled with an oversampling rate of 64
11: Digital microphone support is enabled with an oversampling rate of 32
Page 0 / Register 9:
Audio Serial Data Interface Control Register B
BIT
READ/ RESET
WRITE VALUE
DESCRIPTION
D7–D6
R/W
R/W
R/W
00
00
0
Audio Serial Data Interface Transfer Mode
00: Serial data bus uses I2S mode
01: Serial data bus uses DSP mode
10: Serial data bus uses right-justified mode
11: Serial data bus uses left-justified mode
D5–D4
D3
Audio Serial Data Word Length Control
00: Audio data word length = 16-bits
01: Audio data word length = 20-bits
10: Audio data word length = 24-bits
11: Audio data word length = 32-bits
Bit Clock Rate Control
This register only has effect when bit clock is programmed as an output
0: Continuous-transfer mode used to determine master mode bit clock rate
1: 256-clock transfer mode used, resulting in 256 bit clocks per frame
D2
D1
D0
R/W
R/W
R/W
0
0
DAC Re-Sync
0: Don’t Care
1:
Re-Sync Stereo DAC with Codec Interface if the group delay changes by more than ±DACFS/4.
ADC Re-Sync
0: Don’t Care
1:
Re-Sync Stereo ADC with Codec Interface if the group delay changes by more than ±ADCFS/4.
Re-Sync Mute Behavior
0: Re-Sync is done without soft-muting the channel. (ADC/DAC)
1: Re-Sync is done by internally soft-muting the channel. (ADC/DAC)
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Page 0 / Register 10:
Audio Serial Data Interface Control Register C
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D0
R/W
00000000
Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling
the offset from beginning of the frame where valid data begins. The offset is measured from
the rising edge of word clock when in DSP mode.
00000000: Data offset = 0 bit clocks
00000001: Data offset = 1 bit clock
00000010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode the maximum offset is 17 for I2S/LJF/RJF modes and 16
for DSP mode. In 256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for
DSP modes.
11111110: Data offset = 254 bit clocks
11111111: Data offset = 255 bit clocks
Page 0 / Register 11:
Audio Codec Overflow Flag Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
0
Left ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D6
D5
R
0
Right ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
R
0
Left DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D4
R
0
Right DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is
removed. The register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D3–D0
R/W
0001
PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
Page 0 / Register 12:
Audio Codec Digital Filter Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
00
Left ADC Highpass Filter Control
00: Left ADC highpass filter disabled
01: Left ADC highpass filter –3-dB frequency = 0.0045 × ADC Fs
10: Left ADC highpass filter –3-dB frequency = 0.0125 × ADC Fs
11: Left ADC highpass filter –3-dB frequency = 0.025 × ADC Fs
D5–D4
R/W
00
Right ADC Highpass Filter Control
00: Right ADC highpass filter disabled
01: Right ADC highpass filter –3-dB frequency = 0.0045 × ADC Fs
10: Right ADC highpass filter –3-dB frequency = 0.0125 × ADC Fs
11: Right ADC highpass filter –3-dB frequency = 0.025 × ADC Fs
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Page 0 / Register 12:
Audio Codec Digital Filter Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D3
R/W
R/W
R/W
R/W
0
0
0
0
Left DAC Digital Effects Filter Control
0: Left DAC digital effects filter disabled (bypassed)
1: Left DAC digital effects filter enabled
D2
D1
D0
Left DAC De-emphasis Filter Control
0: Left DAC de-emphasis filter disabled (bypassed)
1: Left DAC de-emphasis filter enabled
Right DAC Digital Effects Filter Control
0: Right DAC digital effects filter disabled (bypassed)
1: Right DAC digital effects filter enabled
Right DAC De-emphasis Filter Control
0: Right DAC de-emphasis filter disabled (bypassed)
1: Right DAC de-emphasis filter enabled
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Page 0 / Register 13:
Headset / Button Press Detection Register A
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Headset Detection Control
0: Headset detection disabled
1: Headset detection enabled
D6-D5
D4-D2
R
00
Headset Type Detection Results
00: No headset detected
01: Stereo headset detected
10: Cellular headset detected
11: Stereo + cellular headset detected
R/W
000
Headset Glitch Suppression Debounce Control for Jack Detection
000: Debounce = 16msec( sampled with 2ms clock)
001: Debounce = 32msec( sampled with 4ms clock)
010: Debounce = 64msec( sampled with 8ms clock)
011: Debounce = 128msec( sampled with 16ms clock)
100: Debounce = 256msec( sampled with 32ms clock)
101: Debounce = 512msec( sampled with 64ms clock)
110: Reserved, do not write this bit sequence to these register bits.
111: Reserved, do not write this bit sequence to these register bits.
D1-D0
R/W
00
Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0msec
01: Debounce = 8msec(sampled with 1ms clock)
10: Debounce = 16msec(sampled with 2ms clock)
11: Debounce = 32msec(sampled with 4ms clock)
Page 0 / Register 14:
Headset / Button Press Detection Register B
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6(1)
R/W
R
0
Stereo Output Driver Configuration A
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used
1: A stereo fully-differential output configuration is being used
D5
0
Button Press Detection Flag
This register is a sticky bit, and will stay set to 1 after a button press has been detected, until the
register is read. Upon reading this register, the bit is reset to zero.
0: A button press has not been detected
1: A button press has been detected
D4
R
0
0
Headset Detection Flag
0: A headset has not been detected
1: A headset has been detected
D3(1)
R/W
Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudo-differential output configuration is not being used
1: A stereo pseudo-differential output configuration is being used
D2–D0
R
000
Reserved. Write only zeros to these bits.
(1) Do not set D6 and D3 to 1 simultaneously
Page 0 / Register 15:
Left ADC PGA Gain Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
1
Left ADC PGA Mute
0: The left ADC PGA is not muted
1: The left ADC PGA is muted
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Page 0 / Register 15:
Left ADC PGA Gain Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D6-D0
R/W
0000000 Left ADC PGA Gain Setting
0000000: Gain = 0.0-dB
0000001: Gain = 0.5-dB 0000010: Gain = 1.0-dB
…
1110110: Gain = 59.0-dB
1110111: Gain = 59.5-dB
1111000: Gain = 59.5-dB
…
1111111: Gain = 59.5-dB
Page 0 / Register 16:
Right ADC PGA Gain Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
1
Right ADC PGA Mute
0: The right ADC PGA is not muted
1: The right ADC PGA is muted
D6-D0
R/W
0000000 Right ADC PGA Gain Setting
0000000: Gain = 0.0-dB
0000001: Gain = 0.5-dB
0000010: Gain = 1.0-dB
…
1110110: Gain = 59.0-dB
1110111: Gain = 59.5-dB
1111000: Gain = 59.5-dB
…
1111111: Gain = 59.5-dB
Page 0 / Register 17:
MIC3L/R to Left ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
1111
MIC3L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the left ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the left ADC PGA
D3-D0
R/W
1111
MIC3R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the left ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to the left ADC PGA
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Page 0 / Register 18:
MIC3L/R to Right ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D4
R/W
1111
MIC3L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3L to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3L is not connected to the right ADC PGA
D3–D0
R/W
1111
MIC3R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects MIC3R to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: MIC3R is not connected to right ADC PGA
Page 0 / Register 19:
LINE1L to Left ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
D6–D3
R/W
1111
LINE1L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the left ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the left ADC PGA
D2
R/W
R/W
0
Left ADC Channel Power Control
0: Left ADC channel is powered down
1: Left ADC channel is powered up
D1–D0
00
Left ADC PGA Soft-Stepping Control
00: Left ADC PGA soft-stepping at once per Fs
01: Left ADC PGA soft-stepping at once per two Fs
10–11: Left ADC PGA soft-stepping is disabled
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Page 0 / Register 20:
LINE2L to Left(1) ADC Control Register
BIT
READ/ RESET
WRITE VALUE
DESCRIPTION
D7
R/W
0
LINE2L Single-Ended vs Fully Differential Control
If LINE2L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2L is configured in single-ended mode
1: LINE2L is configured in fully differential mode
D6–D3
R/W
1111 LINE2L Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2L to the left ADC PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE2L is not connected to the left ADC PGA
D2
R/W
R
0
Left ADC Channel Weak Common-Mode Bias Control
0:
1:
Left ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
Left ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1-D0
00
Reserved. Write only zeros to these register bits
(1) LINE1R SEvsFD control is available for both left and right channels. However this setting must be same for both the channels.
Page 0 / Register 21:
LINE1R to Left ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
D6–D3
R/W
1111
LINE1R Input Level Control for Left ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the left ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1R is not connected to the left ADC PGA
D2–D0
R
000
Reserved. Write only zeros to these register bits.
Page 0 / Register 22:
LINE1R to Right ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE1R Single-Ended vs Fully Differential Control
If LINE1R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1R is configured in single-ended mode
1: LINE1R is configured in fully differential mode
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Page 0 / Register 22:
LINE1R to Right ADC Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D6–D3
R/W
1111
LINE1R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1R to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1R is not connected to the right ADC PGA
D2
R/W
R/W
0
Right ADC Channel Power Control
0: Right ADC channel is powered down
1: Right ADC channel is powered up
D1–D0
00
Right ADC PGA Soft-Stepping Control
00: Right ADC PGA soft-stepping at once per Fs
01: Right ADC PGA soft-stepping at once per two Fs
10-11: Right ADC PGA soft-stepping is disabled
Page 0 / Register 23:
LINE2R to Right ADC Control Register
BIT
READ/ RESET
WRITE VALUE
DESCRIPTION
D7
R/W
0
LINE2R Single-Ended vs Fully Differential Control
If LINE2R is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE2R is configured in single-ended mode
1: LINE2R is configured in fully differential mode
D6–D3
R/W
1111 LINE2R Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE2R to the right ADC PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = -–1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001-1110: Reserved. Do not write these sequences to these register bits
1111: LINE2R is not connected to the right ADC PGA
D2
R/W
R
0
Right ADC Channel Weak Common-Mode Bias Control
0:
1:
Right ADC channel unselected inputs are not biased weakly to the ADC common-mode voltage
Right ADC channel unselected inputs are biased weakly to the ADC common- mode voltage
D1–D0
00
Reserved. Write only zeros to these register bits
Page 0 / Register 24:
LINE1L to Right ADC Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE1L Single-Ended vs Fully Differential Control
If LINE1L is selected to both left and right ADC channels, both connections must use the same
configuration (single-ended or fully differential mode).
0: LINE1L is configured in single-ended mode
1: LINE1L is configured in fully differential mode
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Page 0 / Register 24:
LINE1L to Right ADC Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D6–D3
R/W
1111
LINE1L Input Level Control for Right ADC PGA Mix
Setting the input level control to a gain below automatically connects LINE1L to the right ADC
PGA mix
0000: Input level control gain = 0.0-dB
0001: Input level control gain = –1.5-dB
0010: Input level control gain = –3.0-dB
0011: Input level control gain = –4.5-dB
0100: Input level control gain = –6.0-dB
0101: Input level control gain = –7.5-dB
0110: Input level control gain = –9.0-dB
0111: Input level control gain = –10.5-dB
1000: Input level control gain = –12.0-dB
1001–1110: Reserved. Do not write these sequences to these register bits
1111: LINE1L is not connected to the right ADC PGA
D2–D0
R
000
Reserved. Write only zeros to these register bits.
Page 0 / Register 25:
MICBIAS Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
00
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD
D5–D3
D2–D0
R
R
000
Reserved. Write only zeros to these register bits.
Reserved. Write only zeros to these register bits.
XXX
Page 0 / Register 26:
Left AGC Control Register A
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Left AGC Enable
0: Left AGC is disabled
1: Left AGC is enabled
D6–D4
R/W
000
Left AGC Target Gain
000: Left AGC target gain = –5.5-dB
001: Left AGC target gain = –8-dB
010: Left AGC target gain = –10-dB
011: Left AGC target gain = –12-dB
100: Left AGC target gain = –14-dB
101: Left AGC target gain = –17-dB
110: Left AGC target gain = –20-dB
111: Left AGC target gain = –24-dB
D3–D2
D1–D0
R/W
R/W
00
00
Left AGC Attack Time
These time constants(1) will not be accurate when double rate audio mode is enabled.
00: Left AGC attack time = 8-msec
01: Left AGC attack time = 11-msec
10: Left AGC attack time = 16-msec
11: Left AGC attack time = 20-msec
Left AGC Decay Time
These time constants(1) will not be accurate when double rate audio mode is enabled.
00: Left AGC decay time = 100-msec
01: Left AGC decay time = 200-msec
10: Left AGC decay time = 400-msec
11: Left AGC decay time = 500-msec
(1) Time constants are valid when DRA is not enabled. The values would change if DRA is enabled.
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Page 0 / Register 27:
Left AGC Control Register B
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D1
R/W
1111111 Left AGC Maximum Gain Allowed
0000000: Maximum gain = 0.0-dB
0000001: Maximum gain = 0.5-dB
0000010: Maximum gain = 1.0-dB
…
1110110: Maximum gain = 59.0-dB
1110111–111111: Maximum gain = 59.5-dB
D0
R/W
0
Reserved. Write only zero to this register bit.
Page 0 / Register 28:
Left AGC Control Register C
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
00
Noise Gate Hysteresis Level Control
00: Hysteresis is disabled
01: Hysteresis = 1-dB
10: Hysteresis = 2-dB
11: Hysteresis = 3-dB
D5–D1
R/W
00000
Left AGC Noise Threshold Control
00000: Left AGC Noise/Silence Detection disabled
00001: Left AGC noise threshold = –30-dB
00010: Left AGC noise threshold = –32-dB
00011: Left AGC noise threshold = –34-dB
…
11101: Left AGC noise threshold = –86-dB
11110: Left AGC noise threshold = –88-dB
11111: Left AGC noise threshold = –90-dB
D0
R/W
0
Left AGC Clip Stepping Control
0: Left AGC clip stepping disabled
1: Left AGC clip stepping enabled
Page 0 / Register 29:
Right AGC Control Register A
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Right AGC Enable
0: Right AGC is disabled
1: Right AGC is enabled
D6-D4
R/W
000
Right AGC Target Gain
000: Right AGC target gain = –5.5-dB
001: Right AGC target gain = –8-dB
010: Right AGC target gain = –10-dB
011: Right AGC target gain = –12-dB
100: Right AGC target gain = –14-dB
101: Right AGC target gain = –17-dB
110: Right AGC target gain = –20-dB
111: Right AGC target gain = –24-dB
D3–D2
D1–D0
R/W
R/W
00
00
Right AGC Attack Time
These time constants will not be accurate when double rate audio mode is enabled.
00: Right AGC attack time = 8-msec
01: Right AGC attack time = 11-msec
10: Right AGC attack time = 16-msec
11: Right AGC attack time = 20-msec
Right AGC Decay Time
These time constants will not be accurate when double rate audio mode is enabled.
00: Right AGC decay time = 100-msec
01: Right AGC decay time = 200-msec
10: Right AGC decay time = 400-msec
11: Right AGC decay time = 500-msec
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Page 0 / Register 30:
Right AGC Control Register B
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D1
R/W
1111111 Right AGC Maximum Gain Allowed
0000000: Maximum gain = 0.0-dB
0000001: Maximum gain = 0.5-dB
0000010: Maximum gain = 1.0-dB
…
1110110: Maximum gain = 59.0-dB
1110111–111111: Maximum gain = 59.5-dB
D0
R/W
0
Reserved. Write only zero to this register bit.
Page 0 / Register 31:
Right AGC Control Register C
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
00
Noise Gate Hysteresis Level Control
00: Hysteresis is disabled
01: Hysteresis = 1-dB
10: Hysteresis = 2-dB
11: Hysteresis = 3-dB
D5–D1
R/W
00000
Right AGC Noise Threshold Control
00000: Right AGC Noise/Silence Detection disabled
00001: Right AGC noise threshold = –30-dB
00010: Right AGC noise threshold = –32-dB
00011: Right AGC noise threshold = –34-dB
…
11101: Right AGC noise threshold = –86-dB
11110: Right AGC noise threshold = –88-dB
11111: Right AGC noise threshold = –90-dB
D0
R/W
0
Right AGC Clip Stepping Control
0: Right AGC clip stepping disabled
1: Right AGC clip stepping enabled
Page 0 / Register 32:
Left AGC Gain Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D0
R
00011000 Left Channel Gain Applied by AGC Algorithm
00000000: Gain = –12.0-dB
00000001: Gain = –11.5-dB
00000010: Gain = –11.0-dB
…
00011000: Gain = 0.0-dB
00011001: Gain = +0.5-dB
…
10000011: Gain = +59.0-dB
10000100: Gain = +59.5-dB
Page 0 / Register 33:
Right AGC Gain Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R
00011000 Right Channel Gain Applied by AGC Algorithm
00000000: Gain = –12.0-dB
00000001: Gain = –11.5-dB
00000010: Gain = –11.0-dB
…
00011000: Gain = 0.0-dB
00011001: Gain = +0.5-dB
…
10000011: Gain = +59.0-dB
10000100: Gain = +59.5-dB
56
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Page 0 / Register 34:
Left AGC Noise Gate Debounce Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D3
R/W
00000
Left AGC Noise Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
00000: Debounce = 0-msec
00001: Debounce = 0.5-msec
00010: Debounce = 1-msec
00011: Debounce = 2-msec
00100: Debounce = 4-msec
00101: Debounce = 8-msec
00110: Debounce = 16-msec
00111: Debounce = 32-msec
01000: Debounce = 64×1 = 64ms
01001: Debounce = 64×2 = 128ms
01010: Debounce = 64×3 = 192ms
…
11110: Debounce = 64×23 = 1472ms
11111: Debounce = 64×24 = 1536ms
D2–D0
R/W
000
Left AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled
Page 0 / Register 35:
Right AGC Noise Gate Debounce Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D3
R/W
00000
Right AGC Noise Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
00000: Debounce = 0-msec
00001: Debounce = 0.5-msec
00010: Debounce = 1-msec
00011: Debounce = 2-msec
00100: Debounce = 4-msec
00101: Debounce = 8-msec
00110: Debounce = 16-msec
00111: Debounce = 32-msec
01000: Debounce = 64×1 = 64ms
01001: Debounce = 64×2 = 128ms
01010: Debounce = 64×3 = 192ms
…
11110: Debounce = 64×23 = 1472ms
11111: Debounce = 64×24 = 1536ms
D2–D0
R/W
000
Right AGC Signal Detection Debounce Control
These times(1) will not be accurate when double rate audio mode is enabled.
000: Debounce = 0-msec
001: Debounce = 0.5-msec
010: Debounce = 1-msec
011: Debounce = 2-msec
100: Debounce = 4-msec
101: Debounce = 8-msec
110: Debounce = 16-msec
111: Debounce = 32-msec
(1) Time constants are valid when DRA is not enabled. The values would change when DRA is enabled.
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Page 0 / Register 36:
ADC Flag Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Left ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
D6
D5
D4
D3
D2
D1
D0
Left ADC Power Status
0: Left ADC is in a power down state
1: Left ADC is in a power up state
Left AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
Left AGC Saturation Flag
0: Left AGC is not saturated
1: Left AGC gain applied = maximum allowed gain for left AGC
Right ADC PGA Status
0: Applied gain and programmed gain are not the same
1: Applied gain = programmed gain
Right ADC Power Status
0: Right ADC is in a power down state
1: Right ADC is in a power up state
Right AGC Signal Detection Status
0: Signal power is greater than noise threshold
1: Signal power is less than noise threshold
Right AGC Saturation Flag
0: Right AGC is not saturated
1: Right AGC gain applied = maximum allowed gain for right AGC
Page 0 / Register 37:
DAC Power and Output Driver Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
Left DAC Power Control
0: Left DAC not powered up
1: Left DAC is powered up
D6
R/W
R/W
0
Right DAC Power Control
0: Right DAC not powered up
1: Right DAC is powered up
D5–D4
00
HPLCOM Output Driver Configuration Control
00: HPLCOM configured as differential of HPLOUT
01: HPLCOM configured as constant VCM output
10: HPLCOM configured as independent single-ended output
11: Reserved. Do not write this sequence to these register bits.
D3–D0
R
000
Reserved. Write only zeros to these register bits.
Page 0 / Register 38:
High Power Output Driver Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6
D5-D3
R
00
Reserved. Write only zeros to these register bits.
HPRCOM Output Driver Configuration Control
R/W
000
000: HPRCOM configured as differential of HPROUT 001: HPRCOM configured as constant
VCM output
010: HPRCOM configured as independent single-ended output
011: HPRCOM configured as differential of HPLCOM 100: HPRCOM configured as external
feedback with HPLCOM as constant VCM output
101–111: Reserved. Do not write these sequences to these register bits.
D2
D1
R/W
R/W
0
0
Short Circuit Protection Control
0: Short circuit protection on all high power output drivers is disabled
1: Short circuit protection on all high power output drivers is enabled
Short Circuit Protection Mode Control
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Page 0 / Register 38:
High Power Output Driver Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
0:
1:
If short circuit protection enabled, it will limit the maximum current to the load
If short circuit protection enabled, it will power down the output driver automatically when a
short is detected
D0
R
0
Reserved. Write only zero to this register bit.
Page 0 / Register 39:
Reserved Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D0
R
00000000 Reserved. Do not write to this register.
Page 0 / Register 40:
High Power Output Stage Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
R/W
R/W
R/W
00
00
00
00
Output Common-Mode Voltage Control
00: Output common-mode voltage = 1.35V
01: Output common-mode voltage = 1.5V
10: Output common-mode voltage = 1.65V
11: Output common-mode voltage = 1.8V
D5–D4
D3–D2
D1–D0
LINE2L Bypass Path Control
00: LINE2L bypass is disabled
01: LINE2L bypass uses LINE2LP single-ended
10: LINE2L bypass uses LINE2LM single-ended
11: LINE2L bypass uses LINE2LP/M differentially
LINE2R Bypass Path Control
00: LINE2R bypass is disabled
01: LINE2R bypass uses LINE2RP single-ended
10: LINE2R bypass uses LINE2RM single-ended
11: LINE2R bypass uses LINE2RP/M differentially
Output Volume Control Soft-Stepping
00: Output soft-stepping = one step per Fs
01: Output soft-stepping = one step per 2Fs
10: Output soft-stepping disabled
11: Reserved. Do not write this sequence to these register bits.
Page 0 / Register 41:
DAC Output Switching Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7–D6
R/W
00
Left DAC Output Switching Control
00: Left DAC output selects DAC_L1 path
01: Left DAC output selects DAC_L3 path to left line output driver
10: Left DAC output selects DAC_L2 path to left high power output drivers
11: Reserved. Do not write this sequence to these register bits.
(1)
D5–D4
R/W
00
Right DAC Output Switching Control
00: Right DAC output selects DAC_R1 path
01: Right DAC output selects DAC_R3 path to right line output driver
10: Right DAC output selects DAC_R2 path to right high power output drivers
11: Reserved. Do not write this sequence to these register bits.
(1)
D3–D2
D1–D0
R/W
R/W
00
00
Reserved. Write only zeros to these bits.
DAC Digital Volume Control Functionality
00: Left and right DAC channels have independent volume controls
01: Left DAC volume follows the right channel control register
10: Right DAC volume follows the left channel control register
11: Left and right DAC channels have independent volume controls (same as 00)
(1) When using the DAC direct paths (DAC_L2 and DAC_R2), the signal will be gain up by a factor of -1dB.
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Page 0 / Register 42:
Output Driver Pop Reduction Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
Output Driver Power-On Delay Control
0000: Driver power-on time = 0-µsec
0001: Driver power-on time = 10-µsec
0010: Driver power-on time = 100-µsec
0011: Driver power-on time = 1-msec
0100: Driver power-on time = 10-msec
0101: Driver power-on time = 50-msec
0110: Driver power-on time = 100-msec
0111: Driver power-on time = 200-msec
1000: Driver power-on time = 400-msec
1001: Driver power-on time = 800-msec
1010: Driver power-on time = 2-sec
1011: Driver power-on time = 4-sec
1100–1111: Reserved. Do not write these sequences to these register bits.
D3-D2
D1
R/W
R/W
R/W
00
0
Driver Ramp-up Step Timing Control
00: Driver ramp-up step time = 0-msec
01: Driver ramp-up step time = 1-msec
10: Driver ramp-up step time = 2-msec
11: Driver ramp-up step time = 4-msec
Weak Output Common-mode Voltage Control
0:
Weakly driven output common-mode voltage is generated from resistor divider off the AVDD
supply
1:
Weakly driven output common-mode voltage is generated from bandgap reference
D0
0
Reserved. Write only zero to this register bit.
Page 0 / Register 43:
Left DAC Digital Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
1
Left DAC Digital Mute
0: The left DAC channel is not muted
1: The left DAC channel is muted
D6–D0
R/W
0000000 Left DAC Digital Volume Control Setting
0000000: Gain = 0.0-dB
0000001: Gain = –0.5-dB
0000010: Gain = –1.0-dB
…
1111101: Gain = –62.5-dB
1111110: Gain = –63.0-dB
1111111: Gain = –63.5-dB
Page 0 / Register 44:
Right DAC Digital Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
1
Right DAC Digital Mute
0: The right DAC channel is not muted
1: The right DAC channel is muted
D6–D0
R/W
0000000 Right DAC Digital Volume Control Setting
0000000: Gain = 0.0-dB
0000001: Gain = –0.5-dB
0000010: Gain = –1.0-dB
…
1111101: Gain = –62.5-dB
1111110: Gain = –63.0-dB
1111111: Gain = –63.5-dB
60
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Output Stage Volume Controls
A basic analog volume control with range from 0 dB to -78 dB and mute is replicated multiple times in the output
stage network, connected to each of the analog signals that route to the output stage. In addition, to enable
completely independent mixing operations to be performed for each output driver, each analog signal coming
into the output stage may have up to seven separate volume controls. These volume controls all have
approximately 0.5-dB step programmability over most of the gain range, with steps increasing slightly at the
lowest attenuations. Table 4 lists the detailed gain versus programmed setting for this basic volume control.
Table 4. Output Stage Volume Control Settings and Gains
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
Gain Setting
Analog Gain
(dB)
0 0.0
1
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
-15.0
-15.5
-16.0
-16.5
-17.0
-17.5
-18.0
-18.6
-19.1
-19.6
-20.1
-20.6
-21.1
-21.6
-22.1
-22.6
-23.1
-23.6
-24.1
-24.6
-25.1
-25.6
-26.1
-26.6
-27.1
-27.6
-28.1
-28.6
-29.1
-29.6
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
-30.1
-30.6
-31.1
-31.6
-32.1
-32.6
-33.1
-33.6
-34.1
-34.6
-35.1
-35.7
-36.1
-36.7
-37.1
-37.7
-38.2
-38.7
-39.2
-39.7
-40.2
-40.7
-41.2
-41.7
-42.2
-42.7
-43.2
-43.8
-44.3
-44.8
90
91
-45.2
-45.8
-46.2
-46.7
-47.4
-47.9
-48.2
-48.7
-49.3
-50.0
-50.3
-51.0
-51.4
-51.8
-52.2
-52.7
-53.7
-54.2
-55.3
-56.7
-58.3
-60.2
-62.7
-64.3
-66.2
-68.7
-72.2
-78.3
Mute
-0.5
-1.0
2
92
3
-1.5
93
4
-2.0
94
5
-2.5
95
6
-3.0
96
7
-3.5
97
8
-4.0
98
9
-4.5
99
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
-5.0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118–127
-5.5
-6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
-12.5
-13.0
-13.5
-14.0
-14.5
Page 0 / Register 45:
LINE2L to HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPLOUT
1: LINE2L is routed to HPLOUT
D6-D0
R/W
0000000 LINE2L to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
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Page 0 / Register 46:
PGA_L to HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPLOUT
1: PGA_L is routed to HPLOUT
D6-D0
R/W
0000000 PGA_L to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 47:
DAC_L1 to HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLOUT
1: DAC_L1 is routed to HPLOUT
D6-D0
R/W
0000000 DAC_L1 to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 48:
LINE2R to HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPLOUT
1: LINE2R is routed to HPLOUT
D6-D0
R/W
0000000 LINE2R to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 49:
PGA_R to HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPLOUT
1: PGA_R is routed to HPLOUT
D6-D0
R/W
0000000 PGA_R to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 50:
DAC_R1 to HPLOUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLOUT
1: DAC_R1 is routed to HPLOUT
D6-D0
R/W
0000000
DAC_R1 to HPLOUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 51:
HPLOUT Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
HPLOUT Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
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Page 0 / Register 51:
HPLOUT Output Level Control Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D3
D2
D1
D0
R/W
0
1
0
0
HPLOUT Mute
0: HPLOUT is muted
1: HPLOUT is not muted
R/W
R
HPLOUT Power Down Drive Control
0: HPLOUT is weakly driven to a common-mode when powered down
1: HPLOUT is tri-stated with powered down
HPLOUT Volume Control Status
0: All programmed gains to HPLOUT have been applied
1: Not all programmed gains to HPLOUT have been applied yet
R/W
HPLOUT Power Control
0: HPLOUT is not fully powered up
1: HPLOUT is fully powered up
Page 0 / Register 52:
LINE2L to HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPLCOM
1: LINE2L is routed to HPLCOM
D6-D0
R/W
0000000 LINE2L to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 53:
PGA_L to HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPLCOM
1: PGA_L is routed to HPLCOM
D6-D0
R/W
0000000 PGA_L to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 54:
DAC_L1 to HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLCOM
1: DAC_L1 is routed to HPLCOM
D6-D0
R/W
0000000
DAC_L1 to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 55:
LINE2R to HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPLCOM
1: LINE2R is routed to HPLCOM
D6-D0
R/W
0000000
LINE2R to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
63
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Page 0 / Register 56:
PGA_R to HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPLCOM
1: PGA_R is routed to HPLCOM
D6-D0
R/W
0000000
PGA_R to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 57:
DAC_R1 to HPLCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLCOM
1: DAC_R1 is routed to HPLCOM
D6-D0
R/W
0000000
DAC_R1 to HPLCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 58:
HPLCOM Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
HPLCOM Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
D2
D1
D0
R/W
R/W
R
0
1
0
0
HPLCOM Mute
0: HPLCOM is muted
1: HPLCOM is not muted
HPLCOM Power Down Drive Control
0: HPLCOM is weakly driven to a common-mode when powered down
1: HPLCOM is tri-stated with powered down
HPLCOM Volume Control Status
0: All programmed gains to HPLCOM have been applied
1: Not all programmed gains to HPLCOM have been applied yet
R/W
HPLCOM Power Control
0: HPLCOM is not fully powered up
1: HPLCOM is fully powered up
Page 0 / Register 59:
LINE2L to HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPROUT
1: LINE2L is routed to HPROUT
D6-D0
R/W
0000000
LINE2L to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 60:
PGA_L to HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPROUT
1: PGA_L is routed to HPROUT
D6-D0
R/W
0000000
PGA_L to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
64
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Page 0 / Register 61:
DAC_L1 to HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPROUT
1: DAC_L1 is routed to HPROUT
D6-D0
R/W
0000000
DAC_L1 to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 62:
LINE2R to HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPROUT
1: LINE2R is routed to HPROUT
D6-D0
R/W
0000000
LINE2R to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 63:
PGA_R to HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPROUT
1: PGA_R is routed to HPROUT
D6-D0
R/W
0000000
PGA_R to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 64:
DAC_R1 to HPROUT Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPROUT
1: DAC_R1 is routed to HPROUT
D6-D0
R/W
0000000
DAC_R1 to HPROUT Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 65:
HPROUT Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
HPROUT Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
D2
D1
D0
R/W
R/W
R
0
1
0
0
HPROUT Mute
0: HPROUT is muted
1: HPROUT is not muted
HPROUT Power Down Drive Control
0: HPROUT is weakly driven to a common-mode when powered down
1: HPROUT is tri-stated with powered down
HPROUT Volume Control Status
0: All programmed gains to HPROUT have been applied
1: Not all programmed gains to HPROUT have been applied yet
R/W
HPROUT Power Control
0: HPROUT is not fully powered up
1: HPROUT is fully powered up
65
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Page 0 / Register 66:
LINE2L to HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to HPRCOM
1: LINE2L is routed to HPRCOM
D6-D0
R/W
0000000
LINE2L to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 67:
PGA_L to HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to HPRCOM
1: PGA_L is routed to HPRCOM
D6-D0
R/W
0000000
PGA_L to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 68:
DAC_L1 to HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPRCOM
1: DAC_L1 is routed to HPRCOM
D6-D0
R/W
0000000
DAC_L1 to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 69:
LINE2R to HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to HPRCOM
1: LINE2R is routed to HPRCOM
D6-D0
R/W
0000000 LINE2R to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 70:
PGA_R to HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to HPRCOM
1: PGA_R is routed to HPRCOM
D6-D0
R/W
0000000 PGA_R to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 71:
DAC_R1 to HPRCOM Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPRCOM
1: DAC_R1 is routed to HPRCOM
D6-D0
R/W
0000000 DAC_R1 to HPRCOM Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
66
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Page 0 / Register 72:
HPRCOM Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
HPRCOM Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
D2
D1
D0
R/W
R/W
R
0
1
0
0
HPRCOM Mute
0: HPRCOM is muted
1: HPRCOM is not muted
HPRCOM Power Down Drive Control
0: HPRCOM is weakly driven to a common-mode when powered down
1: HPRCOM is tri-stated with powered down
HPRCOM Volume Control Status
0: All programmed gains to HPRCOM have been applied
1: Not all programmed gains to HPRCOM have been applied yet
R/W
HPRCOM Power Control
0: HPRCOM is not fully powered up
1: HPRCOM is fully powered up
Page 0 / Register 73:
LINE2L to MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to MONO_LOP/M
1: LINE2L is routed to MONO_LOP/M
D6-D0
R/W
0000000
LINE2L to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 74:
PGA_L to MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to MONO_LOP/M
1: PGA_L is routed to MONO_LOP/M
D6-D0
R/W
0000000
PGA_L to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 75:
DAC_L1 to MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to MONO_LOP/M
1: DAC_L1 is routed to MONO_LOP/M
D6-D0
R/W
0000000
DAC_L1 to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 76:
LINE2R to MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to MONO_LOP/M
1: LINE2R is routed to MONO_LOP/M
D6-D0
R/W
0000000
LINE2R to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
67
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Page 0 / Register 77:
PGA_R to MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to MONO_LOP/M
1: PGA_R is routed to MONO_LOP/M
D6-D0
R/W
0000000 PGA_R to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 78:
DAC_R1 to MONO_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to MONO_LOP/M
1: DAC_R1 is routed to MONO_LOP/M
D6-D0
R/W
0000000
DAC_R1 to MONO_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 79:
MONO_LOP/M Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
R/W
0000
MONO_LOP/M Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
0
MONO_LOP/M Mute
0: MONO_LOP/M is muted
1: MONO_LOP/M is not muted
D2
D1
R/W
R
0
0
Reserved. Write only zero to this register bit.
MONO_LOP/M Volume Control Status
0: All programmed gains to MONO_LOP/M have been applied
1: Not all programmed gains to MONO_LOP/M have been applied yet
D0
R/W
0
MONO_LOP/M Power Control
0: MONO_LOP/M is not fully powered up
1: MONO_LOP/M is fully powered up
Page 0 / Register 80:
LINE2L to LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to LEFT_LOP/M
1: LINE2L is routed to LEFT_LOP/M
D6-D0
R/W
0000000
LINE2L to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 81:
PGA_L to LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to LEFT_LOP/M
1: PGA_L is routed to LEFT_LOP/M
D6-D0
R/W
0000000
PGA_L to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
68
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Page 0 / Register 82:
DAC_L1 to LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to LEFT_LOP/M
1: DAC_L1 is routed to LEFT_LOP/M
D6-D0
R/W
0000000
DAC_L1 to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 83:
LINE2R to LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to LEFT_LOP/M
1: LINE2R is routed to LEFT_LOP/M
D6-D0
R/W
0000000
LINE2R to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 84:
PGA_R to LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to LEFT_LOP/M
1: PGA_R is routed to LEFT_LOP/M
D6-D0
R/W
0000000 PGA_R to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 85:
DAC_R1 to LEFT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to LEFT_LOP/M
1: DAC_R1 is routed to LEFT_LOP/M
D6-D0
R/W
0000000
DAC_R1 to LEFT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 86:
LEFT_LOP/M Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
LEFT_LOP/M Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
R/W
0
LEFT_LOP/M Mute
0: LEFT_LOP/M is muted
1: LEFT_LOP/M is not muted
D2
D1
R/W
R
0
0
Reserved. Write only zero to this register bit.
LEFT_LOP/M Volume Control Status
0: All programmed gains to LEFT_LOP/M have been applied
1: Not all programmed gains to LEFT_LOP/M have been applied yet
D0
R/W
0
LEFT_LOP/M Power Control
0: LEFT_LOP/M is not fully powered up
1: LEFT_LOP/M is fully powered up
69
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Page 0 / Register 87:
LINE2L to RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2L Output Routing Control
0: LINE2L is not routed to RIGHT_LOP/M
1: LINE2L is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
LINE2L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 88:
PGA_L to RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP/M
1: PGA_L is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
PGA_L to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 89:
DAC_L1 to RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP/M
1: DAC_L1 is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
DAC_L1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 90:
LINE2R to RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
LINE2R Output Routing Control
0: LINE2R is not routed to RIGHT_LOP/M
1: LINE2R is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
LINE2R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 91:
PGA_R to RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
PGA_R Output Routing Control
0: PGA_R is not routed to RIGHT_LOP/M
1: PGA_R is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
PGA_R to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
Page 0 / Register 92:
DAC_R1 to RIGHT_LOP/M Volume Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R/W
0
DAC_R1 Output Routing Control
0: DAC_R1 is not routed to RIGHT_LOP/M
1: DAC_R1 is routed to RIGHT_LOP/M
D6-D0
R/W
0000000
DAC_R1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 4
70
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Page 0 / Register 93:
RIGHT_LOP/M Output Level Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
RIGHT_LOP/M Output Level Control
0000: Output level control = 0-dB
0001: Output level control = 1-dB
0010: Output level control = 2-dB
...
1000: Output level control = 8-dB
1001: Output level control = 9-dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3
R/W
0
RIGHT_LOP/M Mute
0: RIGHT_LOP/M is muted
1: RIGHT_LOP/M is not muted
D2
D1
R/W
R
0
0
Reserved. Write only zero to this register bit.
RIGHT_LOP/M Volume Control Status
0: All programmed gains to RIGHT_LOP/M have been applied
1: Not all programmed gains to RIGHT_LOP/M have been applied yet
D0
R/W
0
RIGHT_LOP/M Power Control
0: RIGHT_LOP/M is not fully powered up
1: RIGHT_LOP/M is fully powered up
Page 0 / Register 94:
Module Power Status Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
0
0
0
0
0
0
0
0
Left DAC Power Status
0: Left DAC not fully powered up
1: Left DAC fully powered up
D6
D5
D4
D3
D2
D1
D0
R
Right DAC Power Status
0: Right DAC not fully powered up
1: Right DAC fully powered up
R
MONO_LOP/M Power Status
0: MONO_LOP/M output driver powered down
1: MONO_LOP/M output driver powered up
R
LEFT_LOP/M Power Status
0: LEFT_LOP/M output driver powered down
1: LEFT_LOP/M output driver powered up
R
RIGHT_LOP/M Power Status
0: RIGHT_LOP/M is not fully powered up
1: RIGHT_LOP/M is fully powered up
R
HPLOUT Driver Power Status
0: HPLOUT Driver is not fully powered up
1: HPLOUT Driver is fully powered up
R/W
R
HPROUT Driver Power Status
0: HPROUT Driver is not fully powered up
1: HPROUT Driver is fully powered up
Reserved. Do not write to this register bit.
Page 0 / Register 95:
Output Driver Short Circuit Detection Status Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
0
0
0
HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT
1: Short circuit detected at HPLOUT
D6
D5
R
R
HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT
1: Short circuit detected at HPROUT
HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM
1: Short circuit detected at HPLCOM
71
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Page 0 / Register 95:
Output Driver Short Circuit Detection Status Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D4
R
R
R
R
0
HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM
1: Short circuit detected at HPRCOM
D3
D2
0
HPLCOM Power Status
0: HPLCOM is not fully powered up
1: HPLCOM is fully powered up
0
HPRCOM Power Status
0: HPRCOM is not fully powered up
1: HPRCOM is fully powered up
D1-D0
00
Reserved. Do not write to these register bits.
Page 0 / Register 96:
Sticky Interrupt Flags Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
R
R
R
R
R
R
R
0
HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
Button Press Detection Status
0: No Headset Button Press detected
1: Headset Button Pressed
Headset Detection Status
0: No Headset insertion/removal is detected
1: Headset insertion/removal is detected
Left ADC AGC Noise Gate Status
0: Left ADC Signal Power Greater than Noise Threshold for Left AGC
1: Left ADC Signal Power Lower than Noise Threshold for Left AGC
Right ADC AGC Noise Gate Status
0: Right ADC Signal Power Greater than Noise Threshold for Right AGC
1: Right ADC Signal Power Lower than Noise Threshold for Right AGC
Page 0 / Register 97:
Real-time Interrupt Flags Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7
R
R
R
R
0
0
0
0
HPLOUT Short Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6
D5
D4
HPROUT Short Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
HPLCOM Short Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
HPRCOM Short Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
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Page 0 / Register 97:
Real-time Interrupt Flags Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D3
R
0
0
0
0
Button Press Detection Status(1)
0: No Headset Button Press detected
1: Headset Button Pressed
D2
D1
D0
R
R
R
Headset Detection Status
0: No Headset is detected
1: Headset is detected
Left ADC AGC Noise Gate Status
0: Left ADC Signal Power Greater than Noise Threshold for Left AGC
1: Left ADC Signal Power Lower than Noise Threshold for Left AGC
Right ADC AGC Noise Gate Status
0: Right ADC Signal Power Greater than Noise Threshold for Right AGC
1: Right ADC Signal Power Lower than Noise Threshold for Right AGC
(1) This bit is a sticky bit, cleared only when page 0, register 14 is read.
Page 0 / Register 98:
GPIO1 Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
GPIO1 Output Control
0000: GPIO1 is disabled
0001: GPIO1 used for audio serial data bus ADC word clock
0010: GPIO1 output = clock mux output divided by 1 (M=1)
0011: GPIO1 output = clock mux output divided by 2 (M=2)
0100: GPIO1 output = clock mux output divided by 4 (M=4)
0101: GPIO1 output = clock mux output divided by 8 (M=8)
0110: GPIO1 output = short circuit interrupt
0111: GPIO1 output = AGC noise interrupt
1000: GPIO1 = general purpose input
1001: GPIO1 = general purpose output
1010: GPIO1 output = digital microphone modulator clock
1011: GPIO1 = word clock for audio serial data bus (programmable as input or output)
1100: GPIO1 output = hook-switch/button press interrupt (interrupt polarity: active high, typical
interrupt duration: button pressed time + clock resolution. Clock resolution depends upon debounce
programmability. Typical interrupt delay from button: debounce duration + 0.5ms)
1101: GPIO1 output = jack/headset detection interrupt
1110: GPIO1 output = jack/headset detection interrupt OR button press interrupt
1111: GPIO1 output = jack/headset detection OR button press OR Short Circuit detection OR AGC
Noise detection interrupt
D3
D2
R/W
R/W
0
0
GPIO1 Clock Mux Output Control
0: GPIO1 clock mux output = PLL output
1: GPIO1 clock mux output = clock divider mux output
GPIO1 Interrupt Duration Control
0: GPIO1 Interrupt occurs as a single active-high pulse of typical duration 2ms.
1: GPIO1 Interrupt occurs as continuous pulses until the Interrupt Flags register (register 96) is read
by the host
D1
D0
R
0
0
GPIO1 General Purpose Input Value
0: A logic-low level is input to GPIO1
1: A logic-high level is input to GPIO1
R/W
GPIO1 General Purpose Output Value
0: GPIO1 outputs a logic-low level
1: GPIO1 outputs a logic-high level
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Page 0 / Register 99:
GPIO2 Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D4
R/W
0000
GPIO2 Output Control
0000: GPIO2 is disabled
0001: Reserved. Do not use.
0010: GPIO2 output = jack/headset detect interrupt (interrupt polarity: active high. Typical interrupt
duration: 1.75 ms.)
0011: GPIO2 = general purpose input
0100: GPIO2 = general purpose output
0101-0111: GPIO2 input = digital microphone input, data sampled on clock rising and falling edges
1000: GPIO2 = bit clock for audio serial data bus (programmable as input or output)
1001: GPIO2 output = Headset Detect OR Button Press Interrupt
1010: GPIO2 output = Headset Detect OR Button Press OR Short-Circuit Detect OR AGC Noise
Detect Interrupt
1011: GPIO2 output = Short Circuit Detect OR AGC Noise Detect Interrupt
1100: GPIO2 output = Headset Detect OR Button Press OR Short-Circuit Detect Interrupt
1101: GPIO2 output = Short Circuit Detect Interrupt
1110: GPIO2 output = AGC Noise Detect Interrupt
1111: GPIO2 output = Button Press / Hookswitch Interrupt
D3
D2
D1
R/W
R
0
0
0
GPIO2 General Purpose Output Value
0: GPIO1 outputs a logic-low level
1: GPIO1 outputs a logic-high level
GPIO2 General Purpose Input Value
0: A logic-low level is input to GPIO2
1: A logic-high level is input to GPIO2
R/W
GPIO2 Interrupt Duration Control
0: GPIO2 Interrupt occurs as a single active-high pulse of typical duration 2ms.
1: GPIO2 Interrupt occurs as continuous pulses until the Interrupt Flags register (register 96) is read
by the host
D0
R/W
0
Reserved. Write only zero to this register bit.
Page 0 / Register 100:
Additional GPIO Control Register A
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
(1)
D7-D6
R/W
00
SDA Pin Control
The SDA pin hardware includes pull-down capability only (open-drain NMOS), so an external pull-up
resistor is required when using this pin, even in GPIO mode.
00: SDA pin is not used as general purpose I/O
01: SDA pin used as general purpose input
10: SDA pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
(1)
D5
D4
R/W
R
0
0
SDA General Purpose Output Control
0: SDA driven to logic-low when used as general purpose output
1: SDA driven to logic-high when used as general purpose output (requires external pull-up resistor)
(1)
SDA General Purpose Input Value
0: SDA detects a logic-low when used as general purpose input
1: SDA is detects a logic-high when used as general purpose input
D3-D2
R/W
00
SCL Pin Control(1)
The SCL pin hardware includes pulldown capability only (open-drain NMOS), so an external pull-up
resistor is required when using this pin, even in GPIO mode.
00: SCL pin is not used as general purpose I/O
01: SCL pin used as general purpose input
10: SCL pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
(1)
D1
D0
R/W
R
0
0
SCL General Purpose Output Control
0: SCL driven to logic-low when used as general purpose output
1: SCL driven to logic-high when used as general purpose output (requires external pull-up resistor)
(1)
SCL General Purpose Input Value
0: SCL detects a logic-low when used as general purpose input
1: SCL detects a logic-high when used as general purpose input
(1) The control bits in Register 100 are only valid in SPI Mode, when SELECT=1.
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Page 0 / Register 101:
Additional GPIO Control Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
(1)
D7
R
0
I2C Address Pin #0 Status
0: MFP1 pin = I2C address pin #0 = 0 at reset
1: MFP1 pin = I2C address pin #0 = 1 at reset
(1)
D6
D5
D4
D3
D2
D1
D0
R
0
0
0
0
0
0
0
I2C Address Pin #1 Status
0: MFP0 pin = I2C address pin #1 = 0 at reset
1: MFP0 pin = I2C address pin #1 = 1 at reset
(1)
R/W
R/W
R
MFP3 Pin General Purpose Input Control
0: MFP3 pin usage as general purpose input is disabled
1: MFP3 pin usage as general purpose input is enabled
(1)
MFP3 Pin Serial Data Bus Input Control
0: MFP3 pin usage as audio serial data input pin is disabled
1: MFP3 pin usage as audio serial data input pin is enabled
(1)
MFP3 General Purpose Input Value
0: MFP3 detects a logic-low when used as general purpose input
1: MFP3 detects a logic-high when used as general purpose input
(1)
R/W
R/W
R/W
MFP2 General Purpose Output Control
0: MFP2 pin usage as general purpose output is disabled
1: MFP2 pin usage as general purpose output is enabled
(1)
MFP2 General Purpose Output Control
0: MFP2 pin drives a logic-low when used as a general purpose output
1: MFP2 pin drives a logic-high when used as a general purpose output
CODEC_CLKIN Source Selection
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
(1) Bits D7-D1 in Register 101 are only valid in I2C control Mode, when SELECT = 0.
Page 0 / Register 102:
Clock Generation Control Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D6
R/W
R/W
R/W
00
CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK
01: CLKDIV_IN uses GPIO2
10: CLKDIV_IN uses BCLK
11: Reserved. Do not use.
D5-D4
D3-D0
00
PLLCLK_IN Source Selection
00: PLLCLK_IN uses MCLK
01: PLLCLK_IN uses GPIO2
10: PLLCLK _IN uses BCLK
11: Reserved. Do not use.
0010
PLL Clock Divider N Value
0000: N=16
0001: N=17
0010: N=2
0011: N=3
…
1111: N=15
Page 0 / Register 103–127:
Reserved Registers
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R
00000000
Reserved. Do not write to these registers.
Page 1 / Register 0:
Page Select Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D1
X
0000000
Reserved, write only zeros to these register bits
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Page 1 / Register 0:
Page Select Register (continued)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D0
R/W
0
Page Select Bit
Writing zero to this bit sets Page-0 as the active page for following register accesses. Writing a one to
this bit sets Page-1 as the active page for following register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes. This register has the same functionality on page-0 and page-1.
Page 1 / Register 1:
Left Channel Audio Effects Filter N0 Coefficient MSB Register(1)
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x6B
Left Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
(1) Note that whenever any coefficient value is changed, the MSB register should be written first, immediately followed by theLSB register.
Even if only the MSB or LSB of the value changes, both registers should be written
Page 1 / Register 2:
Left Channel Audio Effects Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xE3
Left Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 3:
Left Channel Audio Effects Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x96
Left Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 4:
Left Channel Audio Effects Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x66
Left Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 5:
Left Channel Audio Effects Filter N2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x67
Left Channel Audio Effects Filter N2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 6:
Left Channel Audio Effects Filter N2 Coefficient LSB
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x5D
Left Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
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Page 1 / Register 7:
Left Channel Audio Effects Filter N3 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x6B
Left Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 8:
Left Channel Audio Effects Filter N3 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xE3
Left Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 9:
Left Channel Audio Effects Filter N4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x96
Left Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 10:
Left Channel Audio Effects Filter N4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x66
Left Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2’s
complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 11:
Left Channel Audio Effects Filter N5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x67
Left Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 12:
Left Channel Audio Effects Filter N5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x5D
Left Channel Audio Effects Filter N5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from -32768 to +32767.
Page 1 / Register 13:
Left Channel Audio Effects Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7D
Left Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 14:
Left Channel Audio Effects Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x83
Left Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
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Page 1 / Register 15:
Left Channel Audio Effects Filter D2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x84
Left Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 16:
Left Channel Audio Effects Filter D2 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xEE
Left Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 17:
Left Channel Audio Effects Filter D4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7D
Left Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 18:
Left Channel Audio Effects Filter D4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x83
Left Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 19:
Left Channel Audio Effects Filter D5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x84
Left Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 20:
Left Channel Audio Effects Filter D5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xEE
Left Channel Audio Effects Filter D5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 21:
Left Channel De-emphasis Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x39
Left Channel De-emphasis Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 22:
Left Channel De-emphasis Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x55
Left Channel De-emphasis Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
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Page 1 / Register 23:
Left Channel De-emphasis Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xF3
Left Channel De-emphasis Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 24:
Left Channel De-emphasis Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x2D
Left Channel De-emphasis Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 25:
Left Channel De-emphasis Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x53
Left Channel De-emphasis Filter A0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 26:
Left Channel De-emphasis Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7E
Left Channel De-emphasis Filter A0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 27:
Right Channel Audio Effects Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x6B
Right Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 28:
Right Channel Audio Effects Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xE3
Right Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 29:
Right Channel Audio Effects Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x96
Right Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 30:
Right Channel Audio Effects Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x66
Right Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
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Page 1 / Register 31:
Right Channel Audio Effects Filter N2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x67
Right Channel Audio Effects Filter N2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 32:
Right Channel Audio Effects Filter N2 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x5D
Right Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 33:
Right Channel Audio Effects Filter N3 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x6B
Right Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 34:
Right Channel Audio Effects Filter N3 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xE3
Right Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 35:
Right Channel Audio Effects Filter N4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x96
Right Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 36:
Right Channel Audio Effects Filter N4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x66
Right Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 37:
Right Channel Audio Effects Filter N5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x67
Right Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 38:
Right Channel Audio Effects Filter N5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x5D
Right Channel Audio Effects Filter N5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
80
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Page 1 / Register 39:
Right Channel Audio Effects Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7D
Right Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 40:
Right Channel Audio Effects Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x83
Right Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 41:
Right Channel Audio Effects Filter D2 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x84
Right Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 42:
Right Channel Audio Effects Filter D2 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xEE
Right Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 43:
Right Channel Audio Effects Filter D4 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7D
Right Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 44:
Right Channel Audio Effects Filter D4 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x83
Right Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 45:
Right Channel Audio Effects Filter D5 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x84
Right Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 46:
Right Channel Audio Effects Filter D5 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xEE
Right Channel Audio Effects Filter D5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
81
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Page 1 / Register 47:
Right Channel De-emphasis Filter N0 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x39
Right Channel De-emphasis Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 48:
Right Channel De-emphasis Filter N0 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x55
Right Channel De-emphasis Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 49:
Right Channel De-emphasis Filter N1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xF3
Right Channel De-emphasis Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 50:
Right Channel De-emphasis Filter N1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x2D
Right Channel De-emphasis Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 51:
Right Channel De-emphasis Filter D1 Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x53
Right Channel De-emphasis Filter A0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 52:
Right Channel De-emphasis Filter D1 Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7E
Right Channel De-emphasis Filter A0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 53:
3-D Attenuation Coefficient MSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0x7F
3-D Attenuation Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
Page 1 / Register 54:
3-D Attenuation Coefficient LSB Register
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R/W
0xFF
3-D Attenuation Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a
2’s complement integer, with possible values ranging from –32768 to +32767.
82
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Page 1 / Register 55–127:
Reserved Registers
BIT
READ/
WRITE
RESET
VALUE
DESCRIPTION
D7-D0
R
0x00
Reserved.
Do not write to these registers.
83
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PACKAGE OPTION ADDENDUM
www.ti.com
21-Nov-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TLV320AIC33IGQE
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GQE
80
360
TBD
SNPB
Level-2-220C-1 YEAR
TLV320AIC33IGQER
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GQE
80
2500
TBD
SNPB
Level-2-220C-1 YEAR
TLV320AIC33IRGZR
TLV320AIC33IRGZRG4
TLV320AIC33IRGZT
TLV320AIC33IRGZTG4
TLV320AIC33IZQE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
QFN
QFN
QFN
QFN
RGZ
RGZ
RGZ
RGZ
ZQE
48
48
48
48
80
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
360
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
TLV320AIC33IZQER
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZQE
80
2500
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Nov-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TLV320AIC33IGQER
BGA MI
CROSTA
R JUNI
OR
GQE
80
2500
330.0
12.4
5.3
5.3
1.5
8.0
12.0
Q1
TLV320AIC33IRGZR
TLV320AIC33IRGZT
TLV320AIC33IZQER
QFN
QFN
RGZ
RGZ
ZQE
48
48
80
2500
250
330.0
330.0
330.0
16.4
16.4
12.4
7.3
7.3
5.3
7.3
7.3
5.3
1.5
1.5
1.5
12.0
12.0
8.0
16.0
16.0
12.0
Q2
Q2
Q1
BGA MI
CROSTA
R JUNI
OR
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV320AIC33IGQER
BGA MICROSTAR
JUNIOR
GQE
80
2500
340.5
333.0
20.6
TLV320AIC33IRGZR
TLV320AIC33IRGZT
TLV320AIC33IZQER
QFN
QFN
RGZ
RGZ
ZQE
48
48
80
2500
250
333.2
333.2
340.5
345.9
345.9
333.0
28.6
28.6
20.6
BGA MICROSTAR
JUNIOR
2500
Pack Materials-Page 2
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