ZY7115-T3 [BEL]
DC-DC Regulated Power Supply Module, 1 Output, Hybrid;
| 型号： | ZY7115-T3 |
| 厂家： | 
BEL FUSE INC. |
| 描述： | DC-DC Regulated Power Supply Module, 1 Output, Hybrid |
| 文件： | 总30页 (文件大小：1446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
Member of the
Family
Features
•
•
•
•
Wide input voltage range: 3V – 13.2V
High continuous output current: 15A
Active digital current share
Single-wire serial communication bus for frequency
synchronization, programming, and monitoring
•
•
•
Wide programmable output voltage range: 0.5V to
5.5V
Optimal voltage positioning with programmable slope
of the VI line
Overcurrent, overvoltage, undervoltage, and
overtemperature protections with programmable
thresholds and types
Applications
•
•
•
Programmable fixed switching frequency 0.5-1.0MHz
Programmable turn-on and turn-off delays
•
Low voltage, high density systems with
Intermediate Bus Architectures (IBA)
Programmable turn-on and turn-off voltage slew rates
•
Point-of-load regulators for high performance DSP,
with tracking protection
FPGA, ASIC, and microprocessor applications
•
•
•
•
•
•
Programmable feedback loop compensation
Power Good signal with programmable limits
Programmable fault management
Start up into the load pre-biased up to 100%
Full rated current sink
•
•
Desktops, servers, and portable computing
Broadband, networking, optical, and
communications systems
•
Active memory bus terminators
Benefits
Real time voltage, current, and temperature
•
•
•
Integrates digital power conversion with intelligent
measurements, monitoring, and reporting
power management
•
•
•
Small footprint vertical SMT package: 8x32mm
Low profile of 14mm
Eliminates the need for external power
management components
Compatible with conventional pick-and-place
Completely programmable via industry standard
serial communication bus
equipment
•
•
Wide operating temperature range
•
•
One part that covers all applications
UL60950 recognized, CSA C22.2 No. 60950-00
certified, and TUV EN60950-1:2001 certified
(pending)
Reduces board space, system cost and
complexity, and time to market
Description
The ZY7115 is an intelligent, fully programmable step-down point-of-load DC-DC module integrating digital power
conversion and intelligent power management. When used with ZM7100 Series Digital Power Managers, the
ZY7115 completely eliminates the need for external components for sequencing, tracking, protection, monitoring,
and reporting. All parameters of the ZY7115 are programmable via the serial communication bus and can be
changed by a user at any time during product development and service.
REV. B2.1 AUG 17, 2004
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Page 1 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
1. Selection Chart
Model
Input Voltage
Output Voltage
Range (VDC)
Output Voltage Setpoint Accuracy
(%VOUT or mV, whichever is greater)
Output Current
(ADC)
Range (VDC)
3.0 – 13.2
3.0 – 13.2
3.0 – 13.2
ZY7115
ZY7115H
ZY7115L
0.5 – 5.5
0.5 – 5.5
0.5 – 5.5
1% or 15mV
1% or 10mV
1% or 20mV
15
15
15
2. Reference Documents:
•
•
•
ZM7100 Digital Power Manager. Data Sheet
Digital Power Manager. Programming Manual
ZIOSTM Graphical User Interface
3. Ordering Information
Part Number
ZY7115x–T1
ZY7115x–T2
ZY7115x-T3
Z-ONE-K1
Description
Quantity of ZY7115x
Tape and Reel
Tape and Reel
Tape and Reel
Evaluation Kit
500
100
50
4, mounted on evaluation board
4. Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long-
term reliability, and cause permanent damage to the converter.
Parameter
Operating Temperature
Input Voltage
Conditions/Description
Controller case temperature
250ms Transient
Min
Max
105
15
Units
°C
-40
VDC
ADC
Output Current
(See Output Current Derating Curves)
-15
15
5. Environmental and Mechanical Specifications
Parameter
Sinusoidal Vibration
Ambient Temperature Range
Storage Temperature (Ts)
Weight
Conditions/Description
Min
Nom
Max
20
Units
JESD-B103-B
g
°C
-40
-55
85
125
15
°C
grams
Hrs
MTBF
Per Telcordia TR-NWT-000332
TBD
REV. B2.1 AUG 17, 2004
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Page 2 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
6. Electrical Specifications
Specifications apply at the input voltage from 3V to 13.2V, output load from 0 to 15A, ambient temperature from -40°C to 85°C,
and default performance parameters settings unless otherwise noted.
6.1 Input Specifications
Parameter
Conditions/Description
At VIN<4.75V, VLDO pin needs to be
connected to an external voltage source
higher than 4.75V
Min
Nom
Max
Units
VDC
Input voltage (VIN)
3
13.2
Input Current (at no load)
50
mADC
VIN≥4.75V, VLDO pin connected to VIN
Undervoltage Lockout (VLDO
connected to VIN)
Ramping Up
4.2
VDC
VDC
Ramping Down
3.75
Undervoltage Lockout (VLDO
connected to VAUX=5V)
Ramping Up
3.0
2.5
VDC
VDC
Ramping Down
External Low Voltage Supply
VLDO Input Current
Connect to VLDO pin when VIN<4.75V
4.75
13.2
VDC
Current drawn from the external low
voltage supply at VLDO=5V
50
mADC
6.2 Output Specifications
Parameter
Conditions/Description
Min
0.5
Nom
Max
5.5
Units
Programmable1
VDC
Output Voltage Range (VOUT
)
Default (no programming)
0.5
VDC
Output Voltage Setpoint Accuracy
VIN=12V, IOUT=0.5*IOUT MAX, room temp
VIN MIN to VIN MAX
(See Selection Chart)
-152
15
Output Current (IOUT
Line Regulation
)
ADC
VIN MIN to VIN MAX
±0.3
±0.2
%VOUT
%VOUT
Load Regulation
0 to IOUT MAX
Dynamic Regulation
Peak Deviation
Settling Time
Slew rate 2.5A/µs
50 -100% load step change
to 10% of peak deviation
VIN=5.0V, VOUT=0.5V
VIN=13.2V, VOUT=0.5V
VIN=5.0V, VOUT=2.5V
VIN=13.2V, VOUT=2.5V
VIN=13.2V, VOUT=5.0V
mV
µs
mV
mV
mV
mV
mV
TBD
TBD
10
Output Voltage Peak-to-Peak
Ripple and Noise
15
10
BW=20MHz
25
With external capacitance
35
Temperature Coefficient
Switching Frequency
VIN=12V, IOUT=0.5*IOUT MAX
20
500
ppm/°C
Default
kHz
kHz
%
Programmable, 250kHz steps
Default
500
0
1,000
95
90.5
Duty Cycle Limit
Programmable, 1.56% steps
%
1
2
ZY7115 is a step-down converter, thus the output voltage is always lower than the input voltage
At the negative output current (bus terminator mode) efficiency of the ZY7115 degrades resulting in increased
internal power dissipation. Therefore maximum allowable negative current under specific conditions is 20% lower
than the current determined from the derating curves shown in paragraph 7.4
REV. B2.1 AUG 17, 2004
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Page 3 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
6.3 Protection Specifications
Parameter
Conditions/Description
Output Overcurrent Protection
Min
40
Nom
Max
Units
Default
Non-Latching, 130ms period
Latching/Non-Latching
Type
Programmable
Default
140
%IOUT
%IOUT
Threshold
Programmable in 10% steps
140
Output Overvoltage Protection
Default
Non-Latching, 130ms period
Latching/Non-Latching
Type
Threshold
Delay
Programmable
Default
130
%VO.SET
%VO.SET
Programmable in 10% steps
110
130
From instant when threshold is exceeded until
6
µs
the turn-off command is generated
Output Undervoltage Protection
Default
Non-Latching, 130ms period
Latching/Non-Latching
Type
Threshold
Delay
Programmable
Default
75
%VO.SET
%VO.SET
Programmable in 5% steps
75
85
From instant when threshold is exceeded until
6
µs
the turn-off command is generated
Overtemperature Protection
Default
Non-Latching, 130ms period
Latching/Non-Latching
Type
Programmable
Turn Off Threshold
Turn On Threshold
Temperature is increasing
130
°C
°C
Temperature is decreasing after module was
120
shut down by OTP
Tracking Protection (when Enabled)
Default
Disabled
Type
Threshold
Delay
Programmable
Latching/Non-Latching, 130ms period
Enabled during output voltage ramping up
From instant when threshold is exceeded until
the turn-off command is generated
mVDC
±250
6
µs
Overtemperature Warning
Threshold
Hysteresis
Always enabled, reported in Status register
120
3
°C
°C
From instant when threshold is exceeded until
the warning signal is generated
Delay
6
µs
Power Good Signal
VOUT is inside the PG window
High
Low
Logic
N/A
VOUT is outside the PG window
Default
90
%VO.SET
%VO.SET
%VO.SET
Lower Threshold
Upper Threshold
Delay
Programmable in 5% steps
90
95
110
12
From instant when threshold is exceeded until
status of PG signal changes
µs
REV. B2.1 AUG 17, 2004
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Page 4 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
6.4 Feature Specifications
Parameter
Conditions/Description
Current Share
Min
Nom
Max
Units
Type
Active, Single Line
10
Maximum Number of Modules
IOUT MIN≥20% IOUT NOM
Connected in Parallel
Maximum Number of Modules
Connected in Parallel
IOUT MIN=0
4
Current Share Accuracy
±10
%IOUT NOM
Interleave
Default
0
degree
degree
Interleave (Phase Shift)
0
348.75
Programmable in 11.25° steps
Sequencing
Default
0
ms
ms
Turn ON Delay
Turn OFF Delay
Programmable in 1ms steps
0
0
255
Default
0
ms
Programmable in 1ms steps
63
ms
Tracking
Default
0.1
V/ms
V/ms
Turn ON Slew Rate
Turn OFF Slew Rate
Programmable in 7 steps
0.1
8.33
Default
-0.1
V/ms
Programmable in 7 steps
-0.1
-8.33
V/ms
Optimal Voltage Positioning
Default
0
mV/A
mV/A
Load Regulation
Programmable in 8 steps
0
6.9
Feedback Loop Compensation
Zero1 (Effects phase lead and
increases gain in mid-band)
Default
4.8
50
kHz
kHz
Programmable
0.05
0.05
0.05
1
Zero 2 (Effects phase lead and
Default
49.3
kHz
increases gain in mid-band)
Programmable
50
kHz
Pole 1 (Integrator Pole, effects
loop gain)
Default
1.9
50
kHz
kHz
Programmable
Pole 2 (Effects phase lag and
Default
177
kHz
limits gain in mid-band)
Programmable
1000
kHz
Pole 3 (High frequency low-
pass filter to limit PWM noise)
Default
442
kHz
kHz
Programmable
1
1000
Monitoring
Output Voltage Monitoring
Accuracy
-2%VOUT
- 1LSB
2%VOUT
+ 1LSB
1 LSB=22mV
mV
%IOUT
°C
Output Current Monitoring
3A < IOUT < IOUT MAX
-20
-5
+20
+5
Accuracy
Temperature Monitoring
Accuracy
Junction temperature of POL controller
REV. B2.1 AUG 17, 2004
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Page 5 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
6.5 Signal Specifications
Parameter
Conditions/Description
Min
Nom
Max
Units
VDD
Internal supply voltage
3.15
3.3
3.45
V
SYNC/DATA Line
ViL_sd
ViH_sd
LOW level input voltage
HIGH level input voltage
-0.5
0.3 x VDD
VDD + 0.5
V
V
0.75 x
VDD
0.35 x
VDD
Vhyst_sd
Hysteresis of input Schmitt trigger
V
VoL
Tr_sd
LOW level sink current @ 0.5V
Maximum allowed rise time 10/90%VDD
Added node capacitance
14
mA
ns
300
10
Cnode_sd
Ipu_sd
5
pF
Pull-up current source at Vsd=0V
Clock frequency of external SD line
0.5
mA
Freq_sd
475
22
525
28
kHz
% of clock
cycle
Tsynq
T0
Sync pulse duration
% of clock
cycle
Data=0 pulse duration
72
78
Inputs: ADDR0…ADDR4, Enable, IM, VID0…VID4
Pull-up current source input forced low PG
Iup_PG
Iup_OK
ViL_x
60
µA
µA
V
Pull-up current source input forced low OK
400
LOW level input voltage
HIGH level input voltage
-0.5
0.3 x VDD
VDD+0.5
ViH_x
0.7 x VDD
V
Vhyst_x
Hysteresis of input Schmitt trigger
0.1 x VDD
400
V
Power Good and OK Inputs/Outputs
Iup_x
ViL_x
ViH_x
Vhyst_x
IoL
Pull-up current source input forced low
LOW level input voltage
µA
V
-0.5
0.3 x VDD
VDD+0.5
HIGH level input voltage
0.7 x VDD
V
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
Current Share Bus
0.1 x VDD
1.5
V
10
mA
Iup_CS
ViL_CS
Pull-up current source at VCS = 0V
LOW level input voltage
mA
V
-0.5
0.3 x VDD
VDD+0.5
0.75 x
ViH_CS
HIGH level input voltage
V
V
VDD
0.35 x
VDD
Vhyst_CS
Hysteresis of input Schmitt trigger
IoL
LOW level sink current at 0.5V
15
mA
ns
Tr_CS
Maximum allowed rise time 10/90% VDD
100
REV. B2.1 AUG 17, 2004
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Page 6 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
7. Typical Performance Characteristics
95
90
85
80
75
70
65
60
55
50
7.1 Efficiency Curves
95
90
85
80
Vout=0.5V
Vout=3.3V
Vout=1.2V
Vout=5.0V
Vout=2.5V
75
Vout=0.5V
Vout=1.2V
Vout=2.5V
0
1.5
3
4.5
6
7.5
9
10.5 12 13.5 15
Output Current, A
70
0
1.5
3
4.5
6
7.5
9
10.5 12 13.5 15
Figure 3. Efficiency vs. Load. Vin=12V, Fsw=500kHz
Output Current, A
Figure 1. Efficiency vs. Load. Vin=3.3V, Fsw=500kHz
95
100
90
85
80
75
70
65
95
90
85
80
75
70
Vin=3.3V
1.5
Vin=5V
Vin=12V
4.5
Vout=0.5V
Vout=2.5V
Vout=1.2V
Vout=3.3V
0.5
1
2
2.5
3
3.5
4
5
5.5
Output Voltage, V
0
1.5
3
4.5
6
7.5
9
10.5 12 13.5 15
Figure 4. Efficiency vs. Output Voltage, Iout=15A,
Fsw=500kHz
Output Current, A
Figure 2. Efficiency vs. Load. Vin=5V, Fsw=500kHz
REV. B2.1 AUG 17, 2004
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Page 7 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
90
88
86
84
82
80
95
90
85
80
75
70
65
78
Vout=0.5V
Vout=2.5V
Vout=1.2V
Vout=3.3V
500kHz
4.5
750kHz
9
1MHz
76
3
4
5
6
7
8
9
10
11
12
0
1.5
3
6
7.5
10.5 12 13.5 15
Input Voltage, V
Output Current, A
Figure 5. Efficiency vs. Input Voltage. Iout=15A, Fsw=500kHz
Figure 7. Efficiency vs. Load. Vin=5V, Vout=1.2V
95
93
91
89
87
85
83
95
94
93
92
91
90
89
500kHz
750kHz
1MHz
500kHz
4.5
750kHz
9
1MHz
88
0
1.5
3
6
7.5
10.5 12 13.5 15
0
1.5
3
4.5
6
7.5
9
10.5 12 13.5 15
Output Current, A
Output Current, A
Figure 6. Efficiency vs. Load. Vin=3.3V, Vout=2.5V
Figure 8. Efficiency vs. Load. Vin=12V, Vout=5V
REV. B2.1 AUG 17, 2004
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Page 8 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
94
92
90
88
86
84
82
80
3.3Vin/2.5Vout
5Vin/1.2Vout
750
12Vin/5Vout
1000
500
Figure 11. Turn-On with Different Rising Slew Rates.
Rising Slew Rates are Programmed as follows: V1-
1V/ms, V2-0.5V/ms, V3-0.2V/ms.
Switching Frequency, kHz
Figure 9. Efficiency vs. Switching Frequency. Iout=15A
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
7.2 Turn-On Characteristics
Figure 12. Sequenced Turn-On. Rising Slew Rate is
Programmed at 1V/ms. V2 Delay is 2ms, V3 delay
is 4ms. Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Figure 10. Tracking Turn-On. Rising Slew Rate is
Programmed at 0.5V/ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
REV. B2.1 AUG 17, 2004
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Page 9 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
7.3 Turn-Off Characteristics
Figure 13. Turn On with Sequencing and Tracking. Rising
Slew Rate Programmed at 0.2V/ms, V1 and V3
delays are programmed at 20ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Figure 15. Tracking Turn-Off. Falling Slew Rate is
Programmed at 0.5V/ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Figure 14. Turn On into Prebiased Load. Same as Figure 13,
with a Diode Between V2 and V3. V3 is Prebiased
by V2 via the Diode.
Figure 16. Turn-Off with Tracking and Sequencing. Falling
Slew Rate is Programmed at 0.5V/ms.
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
Vin=12V, Ch1 – V1, Ch2 – V2, Ch3 – V3
REV. B2.1 AUG 17, 2004
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Page 10 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
7.4 Thermal Derating Curves
15
14
13
12
11
10
9
8
7
6
NC
50
100 LFM
55
200 LFM
400 LFM
75
600 LFM
80
5
45
60
65
70
85
Temperature, 'C
Figure 17. Thermal Derating Curves. Vin=13.2V, Vout=2.5V, Fsw=500kHz
15
14
13
12
11
10
9
8
7
6
0 LFM
50
100 LFM
55
200 LFM
400 LFM
600 LFM
80
5
45
60
65
70
75
85
Temperature, 'C
Figure 18. Thermal Derating Curves. Vin=13.2V, Vout=5V, Fsw=500kHz
REV. B2.1 AUG 17, 2004
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
8. Typical Application
IC
Intermediate Voltage Bus
DPM
SD
OK_B
OK_A
CS
ZY7115
ZY7115
ZY7115
ZY7115
ADDR
ADDR
ADDR
ADDR
V1
V2
V3
Figure 19. Block Diagram of Typical Multiple Output Application with Digital Power Manager and I2C Interface
The block diagram of a typical application of ZY7115 point-of-load converters (POL) is shown in Figure 19. The
system includes multiple POLs and a ZM7100 Series Digital Power Manager (DPM). All POLs are connected to
the DPM and to each other via a single-wire SD (sync/data) communication bus. The bus provides
synchronization of all POLs to the master clock generated by the DPM and simultaneously performs bidirectional
data transfer between POLs and the DPM. Each POL has a unique 5-bit address programmed by grounding
respective address pins.
To enable the current share, CS pins of POLs connected in parallel are linked together.
There are two groups of POLs in the application, group A and group B. A group is defined as a number of POLs
interconnected via OK pins. Grouping of POLs is optional: it enables users to program advanced fault
management schemes and simplify POL parameters programming by applying settings to all POLs in a group.
The complete schematic of the application is shown in Figure 20.
REV. B2.1 AUG 17, 2004
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
Figure 20. Complete Schematic of Application Shown in Figure 19. Intermediate Bus Voltage is from 4.75V to 13.2V.
REV. B2.1 AUG 17, 2004
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
9. Pin Assignments and Description
Pin
Pin
No.
Pin
Buffer
Type
Pin Description
Notes
Name
Type
Connect to an external voltage source higher
than 4.75V, if VIN<4.75V. Connect to VIN, if
VIN≥4.75V
VLDO
1
P
Low Voltage Dropout
IM
2
3
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Leave floating
Leave floating
Leave floating
Leave floating
Leave floating
Leave floating
Leave floating
Leave floating
Connect to PGND
VID5
VID4
VID3
VID2
VID1
VID0
VREF
EN
4
5
6
7
8
9
10
Connect to OK pin of other Z-POL and/or
OK
11
I/O
PU
Fault/Status Condition
DPM. Leave floating, if not used
SD
12
13
14
I/O
I/O
PU
PU
Sync/Data Line
Power Good
Not Used
Connect to SD pin of DPM
Leave floating
PGOOD
TRIM
Connect to CS pin of other Z-POLs connected
CS
15
I/O
PU
Current Share
in parallel
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-VS
16
17
18
19
20
21
22
23
24
25
I
I
PU
PU
PU
PU
PU
PU
PU
POL Address Bit 4
POL Address Bit 3
POL Address Bit 2
POL Address Bit 1
POL Address Bit 0
Negative Voltage Sense
Positive Voltage Sense
Output Voltage
Tie to PGND for 0 or leave floating for 1
Tie to PGND for 0 or leave floating for 1
Tie to PGND for 0 or leave floating for 1
Tie to PGND for 0 or leave floating for 1
Tie to PGND for 0 or leave floating for 1
Connect to the negative point close to the load
Connect to the positive point close to the load
I
I
I
I
+VS
I
VOUT
PGND
VIN
P
P
P
Power Ground
Input Voltage
Legend: I=input, O=output, I/O=input/output, P=power, A=analog, PU=internal pull-up
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Page 14 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
Registers 00h through 14h are programmed at
10. Programmable Features
ZY7115 performance parameters
system startup.
can
be
programmed via the communication bus without
replacing any components or rewiring PCB traces.
Each parameter has a default value stored in the
registers of volatile memory detailed in Table 1.
When the user programs new performance
parameters, the default values are overwritten.
Upon removal of the input voltage, the default
settings are restored.
ZY7115 parameters can be reprogrammed at any
time during the system operation and service except
for the digital filter coefficients, the switching
frequency and the duty cycle limitation, that can only
be changed when the POL is turned off.
10.1 Output Voltage
The output voltage can be programmed in the GUI
Output Configuration window shown in the Figure 21
or directly via the I2C bus by writing into the VOS
register shown in Figure 22.
ZY7115 converters can be programmed using the
ZIOSTM Graphical User Interface or directly via the
I2C bus by using high and low level commands as
described in the ‘”DPM Programming Manual”.
Table 1. ZY7115 Memory Registers
Register
Content
Address
PC1
PC2
PC3
DON
DOF
TC
Protection Configuration 1
Protection Configuration 2
Protection Configuration 3
Turn-On Delay
00h
01h
02h
05h
06h
03h
04h
Turn-Off Delay
Tracking Configuration
Interleave Configuration and
Frequency Selection
INT
RUN
ST
VOS
CLS
DCL
B1
RUN Register
Status Register
15h
16h
07h
08h
09h
0Ah
Output Voltage Setpoint
Current Limit Setpoint
Duty Cycle Limit
Dig Controller Denominator z-1
Coefficient
B2
Dig Controller Denominator z-2
Coefficient
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
Figure 21. Output Configuration Window
B3
Dig Controller Denominator z-3
Coefficient
C0L
C0H
C1L
C1H
C2L
C2H
C3L
C3H
Dig Controller Numerator z0
Coefficient, Low Byte
Dig Controller Numerator z0
Coefficient, High Byte
Dig Controller Numerator z-1
Coefficient, Low Byte
Dig Controller Numerator z-1
Coefficient, High Byte
Dig Controller Numerator z-2
Coefficient, Low Byte
Dig Controller Numerator z-2
Coefficient, High Byte
Dig Controller Numerator z-3
Coefficient, High Byte
Dig Controller Numerator z-3
Coefficient, Low Byte
R/W-0
VOS7
Bit 7
R/W-0
VOS6
R/W-0
VOS5
R/W-0
VOS4
R/W-0
VOS3
R/W-0
VOS2
R/W-0
VOS1
R/W-0
VOS0
Bit 0
Bit 7:0 VOS[7:0], Output voltage setting
00h: corresponds to 0.5000V
01h: corresponds to 0.5125V
…
R
= Readable bit
= Writable bit
W
U
= Unimplemented bit,
read as ‘0’
77h: corresponds to 1.9875V
78h: corresponds to 2.0000V
79h: corresponds to 2.025V
…
- n = Value at POR reset
F9h: corresponds to 5.225V
FAh: corresponds to 5.250V
FBh: corresponds to 5.300V
…
FFh: corresponds to 5.500V
Figure 22. Output Voltage Setpoint Register VOS
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Page 15 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
10.1.1
Output Voltage Setpoint
VOUT
The output voltage programming range is from 0.5V
to 5.5V. Within this range, there are 256 predefined
voltage setpoints. To improve resolution of the
output voltage settings, the voltage range is divided
into three sub-ranges as shown in Table 2.
Upper Regulation
Limit
Operating
Point
VI Curve Without
Load Regulation
VI Curve With
Load Regulation
Headroom without
Load Regulation
Lower Regulation
Limit
Table 2. Output Voltage Adjustment Resolution
Headroom with
VOUT MIN, V
0.500
VOUT MAX, V
2.000
5.25
Resolution, mV
Load Regulation
Heavy
Load
Light
Load
IOUT
12.5
25
2.025
Figure 23. Optimal Voltage Positioning Concept
5.3
5.5
50
Increased headroom allows tolerating larger voltage
deviations. For example, the step load change from
light to heavy load will cause the output voltage to
drop. If the optimal voltage positioning is utilized, the
output voltage will stay within the regulation window.
Otherwise, the output voltage will drop below the
lower regulation limit. To compensate for the voltage
drop external output capacitance will need to be
added, thus increasing cost and complexity of the
system.
10.1.2
Output Voltage Margining
If the output voltage needs to be varied by a certain
percentage, the margining function can be utilized.
The margining can be programmed in the GUI
Output Configuration window or directly via the I2C
bus using high level commands as described in the
‘”DPM Programming Manual”.
In order to properly margin POLs that are connected
in parallel, the POLs must be members of one of the
The effect of optimal voltage positioning is shown in
Figure 24 and Figure 25. In this case, switching
output load causes large peak-to-peak deviation of
the output voltage. By programming load regulation,
the peak to peak deviation is dramatically reduced.
Parallel Buses.
Refer to the GUI System
Configuration Window shown in Figure 49.
10.1.3 Optimal Voltage Positioning
Optimal voltage positioning increases the voltage
regulation window by properly positioning the output
voltage setpoint. Positioning is determined by the
load regulation that can be programmed in the GUI
Output Configuration window shown in the Figure 21
or directly via the I2C bus by writing into the CLS
register shown in Figure 32.
Figure 23 illustrates optimal voltage positioning
concept. If no load regulation is programmed, the
headroom (voltage differential between the output
voltage setpoint and
a
regulation limit) is
approximately half of the voltage regulation window.
When load regulation is programmed, the output
voltage will decrease as the output current
increases, so the VI characteristic will have a
negative slope. Therefore, by properly selecting the
operating point, it is possible to increase the
headroom as shown in the picture.
Figure 24. Transient Response Without Optimal Voltage
Positioning
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Page 16 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
R/W-0
DON7
Bit 7
R/W-0
DON6
R/W-0
DON5
R/W-0
DON4
R/W-0
DON3
R/W-0
DON2
R/W-0
DON1
R/W-0
DON0
Bit 0
Bit 7:0 DON[7:0]: Turn-on delay time
00h: corresponds to 0ms delay after turn-on command has occurred
…
FFh: corresponds to 255ms delay after turn-on command has occurred
Figure 27. Turn-On Delay Register DON
10.2.2
Turn-Off Delay
U
---
U
R/W-0
DOF5
R/W-0
DOF4
R/W-0
DOF3
R/W-0
DOF2
R/W-0
DOF1
R/W-0
DOF0
Bit 0
---
Bit 7
Bit 7:6 Unimplemented, read as ‘0’
Bit 5:0 DOF[5:0]: Turn-off delay time
Figure 25. Transient Response With Optimal Voltage
Positioning
00h: corresponds to 0ms delay after turn-off command has occurred
…
3Fh: corresponds to 63ms delay after turn-off command has occurred
10.2 Sequencing and Tracking
Figure 28. Turn-Off Delay Register DOF
Turn-on delay, turn-off delay, and rising and falling
output voltage slew rates can be programmed in the
GUI Sequencing/Tracking window shown in Figure
26 or directly via the I2C bus by writing into the DON,
DOF, and TC registers, respectively. The registers
are shown in Figure 27, Figure 28, and Figure 30.
Turn-off delay is defined as an interval from the
application of the Turn-Off command until the output
voltage reaches zero (if the falling slew rate is
programmed) or until both high side and low side
switches are turned off (if the slew rate is not
programmed). Therefore, for the slew rate controlled
turn-off the ramp-down time is included in the turn-off
delay as shown in Figure 29.
User programmed turn-off delay, TDF
Turn-Off
Command
Calculated
Ramp-down time, TF
delay TD
Internal
ramp-down
command
Falling slew
rate dVF/dT
VOUT
Figure 26. Sequencing/Tracking Window
Time
10.2.1
Turn-On Delay
Figure 29. Relationship between Turn-Off Delay and Falling
Slew Rate
Turn-on delay is defined as an interval from the
application of the Turn-On command until the output
voltage starts ramping up.
As it can be seen from the figure, the internally
calculated delay TD is determined by the equation
below.
VOUT
TD = TDF
−
,
dVF
dT
For proper operation TD shall be greater than zero.
The appropriate value of the turn-off delay needs to
be programmed to satisfy the condition.
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Page 17 of 30
ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
U
---
R/W-0
R2
R/W-0
R1
R/W-0
R0
R/W-1
SC
R/W-0
F2
R/W-0
F1
R/W-0
F0
If the falling slew rate control is not utilized, the turn-
off delay only determines an interval from the
application of the Turn-Off command until both high
side and low side switches are turned off. In this
case, the output voltage ramp-down process is
determined by load parameters.
Bit 7
Bit 0
Bit 7
Unimplemented, read as ‘0’
R
= Readable bit
= Writable bit
W
U
Bit 7:4 R[2:0]: Value of Vo rising slope
0: corresponds to 0.1V/ms (default)
1: corresponds to 0.2V/ms
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
2: corresponds to 0.5V/ms
10.2.3
Rising and Falling Slew Rates
3: corresponds to 1.0V/ms
4: corresponds to 2.0V/ms
The output voltage tracking is accomplished by
programming the rising and falling slew rates of the
output voltage. To achieve programmed slew rates,
the output voltage is being changed in 12.5mV steps
where duration of each step determines the slew
rate. For example, ramping up a 1.0V output with a
slew rate of 0.5V/ms will require 80 steps duration of
25µs each.
5: corresponds to 5.0V/ms
6: corresponds to 8.33V/ms
7: corresponds to 8.33V/ms
Bit 3
SC, Slew rate control at turn-off
0: Slew rate control turned off
1: Slew rate control turned on
Bit 2:0 F[2:0]: Value of Vo falling slope
0: corresponds to -0.1V/ms (default)
1: corresponds to -0.2V/ms
2: corresponds to -0.5V/ms
3: corresponds to -1.0V/ms
4: corresponds to -2.0V/ms
5: corresponds to -5.0V/ms
6: corresponds to –8.33V/ms
7: corresponds to –8.33V/ms
Duration of each voltage step is calculated by
dividing the master clock frequency generated by the
Figure 30. Tracking Configuration Register TC
DPM.
Since all POLs in the system are
synchronized to the master clock, the matching of
voltage slew rates of different outputs is very
accurate as it can be seen in Figure 10 and Figure
15.
10.3 Protections
ZY7115 Series converters have a comprehensive set
of programmable protections. The set includes the
output over- and undervoltage protections,
overcurrent protection, overtemperature protection,
tracking protection, overtemperature warning, and
Power Good signal. Status of protections is stored in
the ST register shown in Figure 31.
During the turn on process, a POL not only delivers
current required by the load (ILOAD), but also charges
the load capacitance. The charging current can be
determined from the equation below:
dV
R dt
ICHG = CLOAD
×
Where, CLOAD is load capacitance, dVR/dt is rising
voltage slew rate, and ICHG is charging current.
R-1
PT
R-0
PG
R-1
TR
R-1
OT
R-1
OC
R-1
UV
R-1
OV
R-1
PV
Bit 7
Bit 0
When selecting the rising slew rate, a user needs to
Bit 7
PT: Temperature Warning
PG: Power Good Warning
TR: Tracking Fault
ensure that
R
= Readable bit
= Writable bit
W
U
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
ILOAD + ICHG < IOCP
= Unimplemented bit,
read as ‘0’
Where IOCP is the overcurrent protection threshold of
the ZY7115. If the condition is not met, then the
overcurrent protection will be triggered during the
turn-on process. To avoid this, dVR/dt and the
overcurrent protection threshold should be
programmed to meet the condition above.
OT: Temperature Fault
- n = Value at POR reset
OC: Over Current Fault
UV: Under Voltage Fault
OV: Over Voltage Error (Fatal)
PV: Phase Voltage Error (Fatal)
- A warning/fault/error shall be encoded as ‘0’
Figure 31. Protection Status Register ST
Thresholds of overcurrent, over- and undervoltage
protections, and Power Good limits can be
programmed in the GUI Output Configuration
window or directly via the I2C bus by writing into the
CLS and PC2 registers shown in Figure 32 and
Figure 33.
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
R/W-0
LR2
R/W-0
LR1
R/W-0
LR0
R/W-1
TCE
R/W-1
CLS3
R/W-0
CLS2
R/W-1
CLS1
R/W-1
CLS0
Bit 0
Bit 7
Bit 7:5 LR[2:0], Load regulation configuration
000: 0 V/A/Ohm
R
= Readable bit
= Writable bit
W
U
001: 0.39 V/A/Ohm
= Unimplemented bit,
read as ‘0’
010: 0.78 V/A/Ohm
011: 1.18 V/A/Ohm
- n = Value at POR reset
100: 1.57 V/A/Ohm
101: 1.96 V/A/Ohm
110: 2.35 V/A/Ohm
111: 2.75 V/A/Ohm
Bit 4
TCE, Temperature compensation enable
0: disabled
1: enabled
Bit 3:0 CLS[3:0], Current limit setting
0h: corresponds to 37%
1h: corresponds to 47%
…
Bh: corresponds to 140%
Figure 34. Fault Management Window
Values higher than Bh are translated to Bh (140%)
Figure 32. Current Limit Setpoint Register CLS
R/W-0
TRE
R/W-1
PVE
R/W-0
TRP
R/W-0
OTP
R/W-0
OCP
R/W-0
UVP
R/W-1
OVP
R/W-1
PVP
U
---
U
U
R/W-0
PGLL
R/W-1
R/W-0
R/W-0
R/W-0
Bit 7
Bit 0
---
---
OVPL1 OVPL0 UVPL1 UVPL0
Bit 0
Bit 7
Bit 7
TRE: Tracking fault enable
1 = enabled
R
= Readable bit
= Writable bit
W
U
0 = disabled
Bit 7:5 Unimplemented, read as ‘0’
= Unimplemented bit,
read as ‘0’
R
= Readable bit
= Writable bit
Bit 4
PGLL: Set Power Good Low Level
1 = 95% of Vo
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PVE: Phase voltage error enable
1 = enabled
W
U
- n = Value at POR reset
= Unimplemented bit,
read as ‘0’
0 = 90% of Vo (Default)
0 = disabled
- n = Value at POR reset
Bit 3:2 OVPL[1:0]: Set Over Voltage Protection
Level
TRP: Tracking fault protection
1 = latching
00 = 110% of Vo
0 = non latching
01 = 120% of Vo
OTP: Over temperature protection configuration
1 = latching
10 = 130% of Vo (Default)
11 = 130% of Vo
0 = non latching
Bit 1:0 UVPL[1:0]: Set Under Voltage Protection Level
00 = 75% of Vo (Default)
OCP: Over current protection configuration
1 = latching
01 = 80% of Vo
0 = non latching
10 = 85% of Vo
UVP: Under voltage protection configuration
1 = latching
Figure 33. Protection Configuration Register PC2
0 = non latching
OVP: Over voltage protection configuration
1 = latching
Note that the overvoltage and undervoltage
protection thresholds and Power Good limits are
defined as percentages of the output voltage.
Therefore, the absolute levels of the thresholds
change when the output voltage setpoint is changed
either by output voltage adjustment or by margining.
0 = non latching
PVP: Phase Voltage Protection
1 = latching
0 = non latching
Figure 35. Protection Configuration Register PC1
If the non-latching protection is selected, a POL will
attempt to restart every 130ms until the condition
that triggered the protection has been removed.
When restarting, the output voltages follow tracking
and sequencing settings.
In addition, a user can change type of protections
(latching or non-latching) or disable certain
protections. These settings are programmed in the
GUI Fault Management window shown in Figure 34
or directly via the I2C by writing into the PC1 register
shown in Figure 35.
If the latching type is selected, a POL will turn off and
stay off. The POL can be turned on after 130ms, if
the condition that caused the fault has been removed
and the respective bit in the ST register was cleared,
or the Turn On command was recycled, or the input
voltage was recycled.
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
All protections can be classified into three groups
based on their effect on system operation: warnings,
faults, and errors.
10.3.2
Faults
This group includes overcurrent, overtemperature,
undervoltage, and tracking protections. Triggering
any protection in this group will turn off a ZY7115.
10.3.1
Warnings
This group includes Overtemperature Warning and
Power Good Signal. The warnings do not turn off
POLs but rather generate signals that can be
transmitted to a host controller via the I2C bus.
10.3.2.1 Overcurrent Protection
Overcurrent protection is active whenever the output
voltage of the POL exceeds the prebias voltage (if
any). When the output current reaches the OC
threshold, the output voltage will start decreasing.
As soon as the output voltage decreases below the
undervoltage protection threshold, the OC fault
signal is generated, the POL turns off and the OC bit
in the register ST is changed to 0. Both high side
and low side switches of the POL are turned off
instantly (fast turn-off).
10.3.1.1 Overtemperature Warning
The Overtemperature Warning is generated when
temperature of the controller exceeds 120°C. The
Overtemperature Warning changes the PT bit of the
status register ST to 0 and sends a signal to the
DPM, if the reporting is enabled in the GUI Fault
Management window or directly via the I2C by writing
into the PC3 register shown in Figure 37. When
temperature falls below 117°C, the PT bit is cleared
and the Overtemperature Warning is removed.
The temperature compensation is added to keep the
OC
threshold
approximately
constant
at
temperatures above room temperature. Note that
the temperature compensation can be disabled in
the GUI Output Configuration window or directly via
the I2C by writing into the CLS register. However, it
is recommended to keep the temperature
compensation enabled.
10.3.1.2 Power Good
Power Good is an open collector output that is pulled
low, if the output voltage is outside of the Power
Good window. The window is formed by the Power
Good High threshold that is equal to 110% of the
output voltage and the Power Good Low threshold
that can be programmed from 90 to 95% of the
output voltage.
10.3.2.2 Undervoltage Protection
The undervoltage protection is only active during
steady state operation of the POL to prevent
nuisance tripping. If the output voltage decreases
below the UV threshold and there is no OC fault, the
UV fault signal is generated, the POL turns off, and
the UV bit in the register ST is changed to 0. The
output voltage is ramped down according to
sequencing and tracking settings (regular turn-off).
The Power Good protection is only enabled when the
output voltage is at its steady state level. It is
disabled during the transitions of the output voltage
from one level to other as shown in Figure 36.
The Power Good Warning pulls the Power Good pin
low, changes the PG bit of the status register ST to
0. It sends a signal to the DPM, if the reporting is
enabled in the GUI Fault Management window or
directly via the I2C by writing into the PC3 register
shown in Figure 37. When the output voltage returns
within the Power Good window, the PG pin is pulled
high, the PG bit is cleared and the Power Good
Warning is removed. The Power Good pin can also
be pulled low by an external circuit to initiate the
Power Good Warning.
10.3.2.3 Overtemperature Protection
Overtemperature protection is active whenever the
POL is powered up. If temperature of the controller
exceeds 130°C, the OT fault is generated, POL turns
off, and the OT bit in the register ST is changed to 0.
The output voltage is ramped down according to
sequencing and tracking settings (regular turn-off).
To clear the overtemperature fault, the temperature
of the controller must decrease below the
Overtemperature Warning threshold of 120°C.
Note: Current revision of the DPM does not support receiving
messages from POLs. To retrieve status information, Status
Monitoring in the GUI POL Group Configuration Window should
be enabled (refer to ZM7100 Digital Power Manager Data Sheet).
The DPM will retrieve the status information from each POL on a
continuous basis.
10.3.2.4 Tracking Protection
Tracking protection is active only when the output
voltage is ramped up. The purpose of the protection
is to ensure that the voltage differential between
multiple rails being tracked does not exceed 250mV.
This protection eliminates the need for external
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
clamping diodes between different voltage rails
side and low side switches of the POL are turned off
instantly (fast turn-off).
which are frequently recommended by ASIC
manufacturers.
The tracking protection can be disabled, if it
contradicts requirements of a particular system (for
example turning into high capacitive load where
rising slew rate is not important). It can be disabled
in the GUI Fault Management window or directly via
the I2C bus by writing into the PC1 register.
When the tracking protection is enabled, the POL
continuously compares actual value of the output
voltage to its programmed value as defined by the
output voltage and its rising slew rate. If absolute
value of the difference exceeds 250mV, the tracking
fault signal is generated, the POL turns off, and the
TR bit in the register ST is changed to 0. Both high
Vo
1
RUN
PT and OT
OC enabled
0
continuously enabled
1
0
Vo_Rise
Vo_Stable
Vo_Fall
Vo_Stable
Vo_Rise
Vo_Stable
Vo_Fall
OVP Limit
OVP Limit
PG High Limit
PG High Limit
OVP Limit
PG High Limit
Vo
PGLow Limit
UVP Limit
PGLow Limit
UVP Limit
PGLow Limit
UVP Limit
1.0V
pre-biased output
Time
Figure 36. Protections Enable Conditions
10.3.3
Errors
10.3.4
Faults and Errors Propagation
The group includes overvoltage protection and
phase voltage error. The phase voltage error is not
available in ZY7115.
The feature adds flexibility to the fault management
scheme by giving users control over propagation of
fault signals within and outside of the system. The
propagation means that a fault in one POL can be
programmed to turn off other POLs and devices in
the system, even if they are not directly affected by
the fault.
10.3.3.1 Overvoltage Protection
The overvoltage protection is active whenever the
output voltage of the POL exceeds the pre-bias
voltage (if any). If the output voltage exceeds the
overvoltage protection threshold, the overvoltage
error signal is generated, the POL turns off, and the
OV bit in the register ST is changed to 0. The high
side switch is turned off instantly, and simultaneously
the low side switch is turned on to ensure reliable
protection of sensitive loads. The low side switch
provides low impedance path to quickly dissipate
energy stored in the output filter and achieve
effective voltage limitation.
10.3.4.1 Grouping of POLs
Z-Series POLs can be arranged in several groups to
simplify fault management. A group of POLs is
defined as a number of POLs with interconnected
OK pins. A group can include from 1 to 32 POLs. If
fault propagation within a group is desired, the
propagation bit needs to be checked in the GUI Fault
Management Window. The parameters can also be
programmed directly via the I2C bus by writing into
the PC3 register shown in Figure 37.
The OV threshold can be programmed from 110% to
130% of the output voltage setpoint, but not lower
than 1.0V.
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
When propagation is enabled, the faulty POL pulls its
window. If an error is propagated, the DPM can also
generate commands to turn off a front end (a DC-DC
converter generating the intermediate bus voltage)
and trigger an optional crowbar protection to
accelerate removal of the IBV voltage.
OK pin low. A low OK line initiates turn-off of other
POLs in the group.
R/W-0
PTM
Bit 7
R/W-0
PGM
R/W-1
TRP
R/W-1
OTP
R/W-1
OCP
R/W-1
OVP
R/W-1
OVP
R/W-1
PVP
10.3.4.2 Propagation Process
Bit 0
Propagation of a fault (OCP, UVP, OTP, and TRP)
initiates regular turn-off of other POLs. The faulty
POL in this case performs either the regular or the
fast turn-off depending on a specific fault as
described in section 10.3.2.
Bit 7
PTM: Temperature warning Message
1 = enabled
R
= Readable bit
= Writable bit
W
U
0 = disabled
= Unimplemented bit,
read as ‘0’
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PGM: Power good message
1 = enabled
- n = Value at POR reset
0 = disabled
TRP: Tracking fault propagation
1 = enabled
Propagation of an error initiates fast turn-off of other
POLs. The faulty POL performs the fast turn-off and
turns on its low side switch.
0 = disabled
OTP: Over temperature fault propagation
1 = enabled
0 = disabled
OCP: Over current fault propagation
Example of the fault propagation is shown in Figure
39. In this three-output system (refer to block
diagram in Figure 19), the POL powering the output
V2 (Ch 1 in the picture) encounters a short circuit
during the turn-on. The POL immediately turns off
and generates the OC fault signal. Since the
propagation is enabled and V2 and V3 belong to one
group, the POL powering the output V2 pulls its OK
line low and causes turn off of the POL powering the
output V3 (Ch3 in the picture). The latter will enter
the regular turnoff programmed by the turn off delay
and the falling slew rate. The POL powering the
output V1 continues to ramp up until it reaches its
steady state level.
1 = enabled
0 = disabled
UVP: Under voltage fault propagation
1 = enabled
0 = disabled
OVP: Over voltage error propagation
1 = enabled
0 = disabled
PVP: Phase voltage error propagation
1 = enabled
0 = disabled
Figure 37. Protection Configuration Register PC3
In addition, the OK lines can be connected to the
DPM to facilitate propagation of faults and errors
between groups. One DPM can control up to 4
independent groups. To enable fault propagation
between groups, the respective bit needs to be
checked in the GUI Fault and Error Propagation
window shown in Figure 38.
Since the OC fault is programmed to be non-
latching, both V2 and V3 will attempt to restart every
130ms, repeating the process described above until
the condition causing the short circuit is removed. At
that time, both V2 and V3 will restart according to the
turn-on delay and rising slew rate settings as shown
in Figure 40.
Summary of protections, their parameters and
features is shown in Table 3.
Figure 38. Fault and Error Propagation Window
In this case low OK line will signal DPM to pull other
OK lines low to initiate shutdown of other POLs as
programmed in the GUI Fault and Error Propagation
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
Figure 39. Turn-On into Short Circuit On V2. The OC Fault Is
Figure 40. Output Auto Recovery Upon Removal of the Short
Circuit on V2.
Programmed To Be Non-Latching And Propagate.
Ch4 - Vin, Ch1 – V2, Ch2 – V1, Ch3 – V3
Ch4 - Vin, Ch1 – V2, Ch2 – V1, Ch3 – V3
Table 3. Summary of Protections Parameters and Features
Code
Name
Type
When Active
Turn
Low Side
Propagation
Disable
Off
Switch
PT
Pretemperature
Warning
Warning
Warning
Whenever VIN is applied
During steady state
No
No
N/A
N/A
Sends signal to
DPM
No
No
PG
Power Good
Sends signal to
DPM
TR
OT
OC
UV
OV
Tracking
Overtemperature
Overcurrent
Undervoltage
Overvoltage
Fault
Fault
Fault
Fault
Error
During ramp up
Fast
Regular
Fast
Regular
Fast
Off
Off
Off
Off
On
Regular turn off
Regular turn off
Regular turn off
Regular turn off
Fast turn off
Yes
No
No
No
No
Whenever VIN is applied
When VOUT exceeds prebias
During steady state
When VOUT exceeds prebias
as programmed by a user. ZY7115 converters can
operate at 500kHz, 750kHz, and 1MHz. Although
synchronized, switching frequencies of different
10.4 PWM Parameters
Z-Series POLs utilize digital PWM controller. It gives
users an ability to program most of the PWM
performance parameters, such as switching
frequency, interleave, duty cycle, and feedback loop
compensation.
POLs are independent of each other.
It is
permissible to mix POLs operating at different
frequencies in one system. It allows optimizing
efficiency and transient response of each POL in the
system individually.
10.4.1
Switching Frequency
The switching frequency can be programmed in the
GUI PWM Controller window shown in Figure 41 or
directly via the I2C bus by writing into the INT register
shown in Figure 42. Note that the content of the
register can be changed only when the POL is
turned off.
Switching actions of all POLs connected to the SD
line are synchronized to the master clock generated
by the DPM. Each POL is equipped with a PLL and
a frequency divider so they can operate at multiples
(including fractional) of the master clock frequency
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
input source is added together from all POLs as
shown in Figure 43.
Figure 43. Input Voltage Noise, No Interleave
Figure 41. PWM Controller Window
Figure 44 shows the input voltage noise of the three-
output system with programmed interleave. Instead
of all three POLs switching at the same time as in
the previous example, the POLs V1, V2, and V3
switch at 0°, 123.75°, and 247.5°, respectively.
Noise is spread evenly across the switching cycle
resulting in more than 1.5 times reduction. To
achieve similar noise reduction without interleave will
require the addition of an external LC filter.
R/W-0
FRQ2
Bit 7
R/W-0
FRQ1
R/W-0 R/W-01) R/W-01) R/W-01) R/W-01) R/W-01)
FRQ0
INT4
INT3
INT2
INT1
INT0
Bit 0
Bit 7:5 FRQ[2:0]: PWM Frequency Selection
000: 500kHz
R
= Readable bit
= Writable bit
W
U
001: 750kHz
= Unimplemented bit,
read as ‘0’
010: 1000lHz
011: 1250kHz
- n = Value at POR reset
100: 1250kHz
101: 1500kHz
110: 1750kHz
111: 2000kHz
Bit 4:0 INT[4:0]: Interleave position
00h: Ton starts with 0.0° Phase lag to SYNQ/DATA Line
01h: Ton starts with 11.25° Phase lag to SYNQ/DATA Line
02h: Ton starts with 22.50° Phase lag to SYNQ/DATA Line
…
1Fh: Ton starts with 348.75° Phase lag to SYNQ/DATA Line
1) Initial value depends on the state of the Interleave Mode (IM) Input:
IM=Open: At POR reset the 5 corresponding ADDRESS bits are loaded
IM=Low: At POR reset a 0 is loaded
Figure 42. Interleave Configuration Register INT
10.4.2
Interleave
Interleave is defined as a phase delay between the
synchronizing slope of the master clock on the SD
pin and PWM signal of a POL. The interleave can
be programmed in the GUI PWM Controller window
or directly via the I2C bus by writing into the INT
register.
Figure 44. Input Voltage Noise with Interleave
Similar noise reduction can be achieved on the
output of POLs connected in parallel. Figure 45 and
Figure 46 show the output noise of two ZY7115s
connected in parallel without and with 180°
interleave, respectively. Resulting noise reduction is
Every POL generates switching noise.
If no
interleave is programmed, all POLs in the system
switch simultaneously and noise reflected to the
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
more than 1/3 and is equivalent of adding extra
VOUT
VIN.MIN ×η
DC =
,
capacitance on the output of the POLs.
Where, DC is the duty cycle, VOUT is the required
maximum output voltage (including margining),
VIN.MIN is the minimum input voltage, and η is the
efficiency of the ZY7115 at VOUT, VIN.MIN, and
required IOUT
.
It is good practice to limit the maximum duty cycle of
the PWM controller to a slightly higher value
compared to the steady-state duty cycle as
expressed by the above equation. This will further
protect the output from excessive voltages. The duty
cycle limit can be programmed in the GUI PWM
Controller window or directly via the I2C bus by
writing into the DCL register shown in Figure 47.
R/W-1
DCL5
Bit 7
R/W-1
DCL4
R/W-1
DCL3
R/W-0
DCL2
R/W-1
DCL1
R/W-0
DCL0
R/W-0
HI
R/W-0
LO
Figure 45. Output Voltage Noise, No Interleave
Bit 0
R
= Readable bit
= Writable bit
Bit 7:2 DCL[5:0], Duty Cycle Limitation
W
U
00h: 0
= Unimplemented bit,
read as ‘0’
01h: 1/64
…
- n = Value at POR reset
3Fh: 63/64
Bit 1: HI, ADC high saturation feed-forward
0: disabled
1: enabled
Bit 0: LO, ADC low saturation feed-forward
0: disabled
1: enabled
Figure 47. Duty Cycle Limit Register
10.4.4
ADC Saturation Feedforward
To speed up the PWM response in case of heavy
dynamic loads, the duty cycle can be forced either to
0 or the duty cycle limit depending on the polarity of
the transient. This function is equivalent to having
two comparators defining a window around the
output voltage setpoint. When an error signal is
inside the window, it will produce gradual duty cycle
change proportional to the error signal. If the error
signal goes outside the window (usually due to large
output current steps) the duty cycle will change to its
limit in one switching cycle. In most cases this will
significantly improve transient response of the
controller, reducing amount of required external
capacitance.
Figure 46. Output Voltage Noise, 180° Interleave
The ZY7115 interleave feature is similar to that of
multiphase converters, however, unlike in the case of
multiphase converters, interleave does not have to
be equal to 360/N, where N is the number of POLs in
a system. ZY7115 interleave is independent of the
number of POLs in
a
system and is fully
programmable in 11.25° steps. It allows maximum
output noise reduction by intelligently spreading
switching energy.
10.4.3
Duty Cycle Limit
Under certain circumstances, usually when the
maximum duty cycle limit significantly exceeds its
nominal value, the ADC saturation can lead to the
The ZY7115 is a step-down converter therefore VOUT
is always less than VIN. The relationship between
the two parameters is characterized by duty cycle
and expressed by the following equation:
overcompensation of the output error.
The
phenomenon manifests itself as low frequency
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
oscillations on the output of the POL. It can usually
coefficients are stored in the C0H, C0L, C1H, C1L,
C2H, C2L, C3H, C3L, B1, B2, and B3 registers.
be reduced or eliminated by disabling the ADC
saturation or limiting the maximum duty cycle to 120-
140% of the calculated value. It is not recommended
to use ADC saturation for output voltages higher
than 2.0V
Note: The GUI automatically transforms zero and pole
frequencies into the digital filter coefficients. It is strongly
recommended to use the GUI to determine filter
coefficients.
The ADC saturation feedforward can be
programmed in the GUI PWM Controller window or
directly via the I2C bus by writing into the DCL
register.
Programming feedback loop compensation allows
optimizing POL performance for various application
conditions. For example, increase in bandwidth can
significantly improve dynamic response.
10.4.5
Feedback Loop Compensation
10.5 Current Share
Feedback loop compensation can be programmed in
the GUI PWM Controller window by setting
frequency of poles and zeros of the transfer function.
Z-Series converters are equipped with the digital
current share function. To activate the current share,
interconnect the CS pins of the POLs connected in
parallel. The digital signal transmitted over the CS
line sets output currents of all POLs to the same
level.
The transfer function of the ZY7115 is shown in
Figure 48. It is a third order function with two zeros
and three poles. Pole 1 is the integrator pole, Pole 2
is used in conjunction with Zero 1 and Zero 2 to
adjust the phase lead and limit the gain increase in
mid band. Pole 3 is used as a high frequency low-
pass filter to limit PWM noise.
When POLs are connected in parallel, they must be
included in the same parallel bus in the GUI System
Configuration window shown in Figure 49. In this
case, the GUI automatically copies parameters of
one POL onto all POLs connected to the parallel
bus. It makes it impossible to configure different
performance parameters for POLs connected in
parallel except for interleave and load regulation
settings that are independent. The interleave allows
to reduce and move the output noise of the
converters connected in parallel to higher
frequencies. The load regulation allows controlling
the current share loop gain in case of small signal
oscillations. Always add small amount of load
regulation to one of the converters connected in
parallel to reduce loop gain and therefore improve
stability.
Magnitude[dB]
50
40
30
20
10
Z1 P1 Z2 P2
P3
P1: Pole 1
P2: Pole 3
P3: Pole 3
Z1: Zero 1
Z2: Zero 2
Freq
[kHz]
0.1
0.1
1
1
10
10
100
1000
1000
Phase
[°]
+45
Freq
0
-45
[kHz]
100
10.6 Performance Parameters Monitoring
Z-Series converters can monitor their own
performance parameters such as output voltage,
output current, and temperature.
-90
-135
-180
Figure 48. Transfer Function of PWM
The output voltage is measured at the output sense
pins, output current is measured using the ESR of
the output inductor and temperature is measured by
the thermal sensor built into the controller IC. Output
current readings are adjusted based on temperature
readings to compensate for the change of ESR of
the inductor with temperature.
Positions of poles and zeroes are determined by
coefficients of the digital filter.
The filter is
characterized by four numerator coefficients (C0, C1,
C2, C3) and three denominator coefficients (B1, B2,
B3). The coefficients are automatically calculated
when desired frequency of poles and zeros is
entered in the GUI PWM Controller window. The
An 8-Bit Analog to Digital Converter (ADC) converts
the output voltage, output current, and temperature
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
into a digital signal to be transmitted via the serial
Configuration window shown in Figure 50 are
checked, these registers are being copied into the
ring buffer located in the DPM. Contents of the ring
buffer can be displayed in the GUI IBS Monitoring
Window shown in Figure 51 or it can be read directly
via the I2C bus using high and low level commands
as described in the ‘”DPM Programming Manual”.
interface. The ADC allows a minimum sampling
frequency of 1kHz for all three values.
Monitored parameters are stored in registers (VOM,
IOM, and TMON) that are continuously updated. If
Retrieve Monitoring bits in the GUI Group
Figure 49. GUI System Configuration Window
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
Figure 50. POL Group Configuration Window
Figure 51. IBS Monitoring Window
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
11. Mechanical Drawings
All Dimensions are in mm
Tolerances:
0.5-10
±0.1
10-100 ±0.2
Tilt Specifications 5° From Vertical After Assembly
Figure 52. Mechanical Drawing
Figure 53. Pinout Diagram (Bottom View)
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ZY7115 15A DC-DC Intelligent POL Preliminary Data Sheet
3V to 13.2V Input • 0.5V to 5.5V Output
8.60
4.00
1.20
32.00
10.00
10.00
(x 3)
Un-Exposed Thermal Copper Area
associated with each pad
must be free from other copper/traces
9.00
6.00
1.80
Pin 1
1.27
(x 10)
2.54
1.27
(x 10)
0.80
2.00
(x 22)
Figure 54. Recommended Pad Sizes
Vi+
Vo+
0.45mm Ø Thermal Via x 42
0.45mm Ø Thermal Via x 42
V-
0.45mm Ø Thermal Via x 56
Figure 55. Recommended PCB Layout for Multilayer PCBs
Notes:
1. NUCLEAR AND MEDICAL APPLICATIONS - Power-One products are not authorized for use as critical components in life support systems,
equipment used in hazardous environments or nuclear control systems without the express written consent of the respective divisional
President of Power-One, Inc.
2. TECHNICAL REVISIONS - Specifications are subject to change without notice
2
I C is a trademark of Philips Corporation.
REV. B2.1 AUG 17, 2004
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Page 30 of 30
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