AMMC-6120-W50 [BOARDCOM]
8 â 24 GHz Output à 2 Active Frequency Multiplier;
| 型号： | AMMC-6120-W50 |
| 厂家： | 
Broadcom Corporation. |
| 描述： | 8 â 24 GHz Output à 2 Active Frequency Multiplier |
| 文件： | 总8页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AMMC-6120
8 – 24 GHz Output × 2
Active Frequency Multiplier
Data Sheet
Chip Size: 1600 x 1000 µm (64 x 40 mils)
Chip Size Tolerance: 10 µm ( 0.4 mils)
Chip Thickness: 100 10 µm (4 0.4 mils)
Pad Dimensions: 120 x 80 µm (5x3 0.4 mils)
Description
Features
• Input frequency range: 4-10 GHz
• Broad input power range: -11 to +5dBm
• Output power: +14 dBm (Pin=+3dBm)
• Fundamental Suppression of 25 dBc
• 50 Ω input and output match
Avago Technologies' AMMC-6120 is an easy-to-use x2
active frequency multiplier MMIC designed for com-
mercial communication systems. Though capable of
doubling to 24 GHz with reduced fundamental suppres-
sion, the MMIC is designed to take a 4 to 10 GHz input
and double it to 8 to 24 GHz. It has integrated output
amplifier, matching harmonic suppression, and bias
networks. The input/output are matched to 50 Ω
and fully DC blocked. The MMIC is fabricated using
PHEMT technology. The backside of this die is both RF
and DC ground. This helps simplify the assembly process
and reduces assembly related performance variations
and costs. For improved reliability and moisture protec-
tion, the die is passivated at the active areas. This MMIC is
a cost effective alternative to bulky hybrid FET and diode
doublers that require high input drive power, have high
C.L. and poor fundamental suppression.
• Supply bias of -1.4V, 5V and 85mA
Applications
• Microwave radio systems
• Satellite VSAT, DBS Up/Down Link
• LMDS & Pt-Pt mmW Long Haul
• Broadband Wireless Access
(including 802.16 and 802.20 WiMax)
• WLL and MMDS loops
[1]
AMMC-6120 Absolute Maximum Ratings
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model (Class A)
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
Symbol Parameters/Conditions
Units Min. Max.
Vd
Positive Drain Voltage
Gate Supply Voltage
Drain Current
V
7
Vg
V
-3.0
0.5
Id
mA
dBm
°C
120
15
Pin
Tch
Tstg
Tmax
CW Input Power
Operating Channel Temp.
Storage Case Temp.
+150
+150
+300
°C
-65
Maximum Assembly Temp. °C
(60 sec. max.)
Note:
1. Operation in excess of any one of these conditions may result in
permanent damage to this device.
[1]
AMMC-6120 DC Specifications/Physical Properties
Symbol
Idq
Parameters and Test Conditions
Units
mA
V
Min.
80
Typ.
85
Max.
105
-1.0
Drain Supply Current
Vg
Gate Supply Operating Voltage
-1.5
-1.4
qch-b
Thermal Resistance[2]
(Backside Temperature, Tb = 25°C)
°C/W
25
Notes:
1. Ambient operational temperature T = 25°C unless otherwise noted.
A
2. Channel-to-backside Thermal Resistance (q
) = 26°C/W at T (T ) = 34°C as measured using infrared microscopy. Thermal Resistance at
ch-b channel c
backside temperature (T ) = 25°C calculated from measured data.
b
[3,4,5]
AMMC-6120 RF Specifications
T = 25°C, V = 5 V, V =-1.4V, I
= 85 mA, Z = 50 Ω
o
A
dd
g
d(Q)
Symbol Parameters and Test Conditions
Units
GHz
GHz
dBm
dBc
Minimum
Typical
4 to 10
8 to 24
14
Maximum
Sigma
Fin
Fout
Po
Input Frequency
Output Frequency
Output Power[4]
10.5
18
0.6
1.8
Fo
Fundamental Isolation
(referenced to Po)
25
3Fo
3rd Harmonic Isolation
(referenced to Po)
dBc
25
2.5
P-1dB
RLin
RLout
SSB
Input Power at 1dB Gain Compression
Input Return Loss[6]
Output Return Loss[6]
dBm
dB
+1
-15
-9
dB
Single Sideband Phase Noise
(100 KHz offset)
DBc/Hz
-135
Notes:
3. Small/Large -signal data measured in wafer form T = 25°C.
A
4. 100% on-wafer RF test is done at Pin = +3 dBm, output frequency = 10, 16, and 20 GHz.
5. Specifications are derived from measurements in a 50-W test environment. Aspects of the multiplier performance may be improved over a
more narrow bandwidth by application of additional matching.
2
AMMC-6120 Typical Performances
(T = 25°C, V = 5 V, I = 85 mA, V = -1.4 V, Z = Z = 50 W unless otherwise stated)
A
dd
dq
g
in
out
Note: These measurements are in 50 W test environment. Aspects of the amplifier performance may be improved over a narrower bandwidth by
application of additional conjugate, linearity or low noise (Gopt) matching.
20
15
10
5
20
15
10
5
-40˚C [2H]
+25˚C [2H]
+85˚C [2H]
-40˚C [1H]
+25˚C [1H]
+85˚C [1H]
2H
1H
3H
4H
0
0
-5
-5
-10
-15
-20
-25
-30
-10
-15
-20
-25
-30
8
10 12 14 16 18 20 22 24 26
Output Frequency (GHz)
8
10
12
14
16
18
20
22
24
26
Output Frequency (GHz)
Figure 1. Output Power vs. Output Freq. @ Pin=+3dBm
Figure 2. Output Power vs. Output Freq. over temp @ Pin=+3dBm
19
18
17
16
15
14
13
10
15
20
25
30
Pin=-2dBm
Pin= 0dBm
Pin=+2dBm
Pin=+4dBm
20 22
Pin=-2dBm
Pin= 0dBm
Pin=+2dBm
Pin=+4dBm
12
11
10
35
40
8
10
12
14
16
18
20
22
24
26
8
10
12
14
16
18
24
26
Output Frequency (GHz)
Output Frequency [GHz]
Figure 3. Output Power [2H] vs. Output Freq. at variable Pin
Figure 4. Fundamental Suppression at variable Pin
160
0
-5
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
150
140
Vg=-1.4V, Vd=5.0V
-10
-15
-20
-25
-30
130
120
110
100
90
S11
S22
80
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
4
6
8
10 12 14 16 18 20 22 24 26
Frequncy (GHz)
Input Power [1H] (dBm)
Figure 5. Input and Output Return Loss
Figure 6. Variation of total drain current with input power
3
20
18
16
14
12
10
8
20
25
30
35
40
45
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
Fout=8GHz
6
Fout=8GHz
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
4
2
0
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
Input Power [1H] (dBm)
Input Power [1H] (dBm)
Figure 7. 2H Output Power Vs Input Power @ Fout=8GHz
Figure 8. Fundamental Supp. Vs Input Power @ Fout=8GHz
20
20
Fout=10GHz
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
18
16
14
12
10
8
25
30
35
40
45
6
Fout=10GHz
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
4
2
0
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
Input Power [1H] (dBm)
Input Power [1H] (dBm)
Figure 9. 2H Output Power Vs Input Power @ Fout=10GHz
Figure 10. Fundamental Supp. Vs Input Power @ Fout=10GHz
20
18
10
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
16
15
Fout=14GHz
14
12
10
8
20
25
6
Vg=-1.2V, Vd=4.5V
4
30
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
Fout=14GHz
2
0
35
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
Input Power [1H] (dBm)
Input Power [1H] (dBm)
Figure 11. 2H Output Power Vs Input Power @ Fout=14GHz
Figure 12. Fundamental Supp. Vs Input Power @ Fout=14GHz
4
20
18
16
14
12
10
8
10
15
20
25
30
35
Fout=16GH
Fout=16GHz
6
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
4
2
0
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
Input Power [1H] (dBm)
Input Power [1H] (dBm)
Figure 14. Fundamental Supp. Vs Input Power @ Fout=16GHz
Figure 13. 2H Output Power Vs Input Power @ Fout=16GHz
20
18
16
14
12
5
Fout=20GHz
10
15
10
8
20
Fout=20GHz
25
6
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.2V, Vd=4.5V
4
Vg=-1.2V, Vd=5.0V
30
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
2
Vg=-1.4V, Vd=5.0V
0
35
-11 -9 -7 -5 -3 -1
Input Power [1H] (dBm)
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
1
3
5
7
9
11
Input Power [1H] (dBm)
Figure 15. 2H Output Power Vs Input Power @ Fout=20GHz
Figure 16. Fundamental Supp. Vs Input Power @ Fout=20GHz
5
20
18
16
14
12
Vg=-1.2V, Vd=4.5V
10
15
20
25
30
35
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
10
8
Fout=22GHz
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
6
4
2
0
Fout=22GHz
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
Input Power [1H] (dBm)
Input Power [1H] (dBm)
Figure 17. 2H Output Power Vs Input Power @ Fout=22GHz
Figure 18. Fundamental Supp. Vs Input Power @ Fout=22GHz
5
5
20
18
16
14
12
10
8
Fout=26GHz
Vd=4.5V, Vg=-1.2V
Fout=26GHz
10
15
20
25
30
35
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=4.5V
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
6
Vg=-1.2V, Vd=5.0V
Vg=-1.4V, Vd=4.5V
Vg=-1.4V, Vd=5.0V
4
2
0
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
-11 -9 -7 -5 -3 -1
1
3
5
7
9
11
Input Power [1H] (dBm)
Input Power [1H] (dBm)
Figure. 19 2H Output Power Vs Input Power @ Fout=26GHz
Figure. 20 Fundamental Supp. Vs Input Power @ Fout=26GHz
-50
-60
-70
-80
-90
Fout=15.6GHz
-100
-110
-120
-130
-140
-150
-160
-170
M/N
@ fo
M/N
@ 2fo
S
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
A. DIFF. AMP
ACTIVE BALUN
Offset Frequency [Hz]
Figure.21 SSB Phase Noise of frequency doubler
(Pin=+2dBm, fout=15.6GHz)
Figure 22.
Biasing and Operation
The frequency doubler MMIC consists of a differen- The AMMC-6120 performance changes very slightly with
tial amplifier circuit that acts as an active balun. The
outputs of this balun feed the gates of balanced FETs
Drain (Vd) and Gate bias (Vg) as shown in Figure 8 and 9.
Minor improve-ments in performance are possible for
and the drains are connected to form the single-ended output power or fundamental suppression by optimizing
output. This results in the fundamental frequency and
odd harmonics canceling and the even harmonic drain
currents (in phase) adding in superposition. Node‘S’acts
as a virtual ground. An input matching network (M/N)
is designed to provide good match at fundamental fre-
quencies and produces high impedance mismatch at
higher harmonics.
the Vg from –1.0 V to –1.4 V and/or Vd from 4.0 to 5.0 V.
The RF input and output port are AC coupled thus no
DC voltage is present at either ports. However, the RF
output port has a internal output-matching circuit that
presents a DC short. Proper care should be taken while
biasing sequential circuit to AMMC-6120 as it might cause
DC short (use a DC block if sub sequential circuit is not
AMMC-6120 is biased with a single positive drain supply AC coupled). No ground wires are needed since ground
and single negative gate supply using separate bypass connections are made with plated through-holes to the
capacitors. It is normally biased with the drain supply
connected to both the VdAB and the Vdd bond pads
and the gate supply connected to the VgD bond pad. It
is important to bypass both VdAB and Vdd with 100 pF
capacitors placed as close to the die as possible. Typical
bias connections are shown in Figure 22. For most of the
application it is recommended to use a Vg = –1.2 V and
Vd = 4.5 V.
backside of the device.
Refer the Absolute Maximum Ratings table for allowed
DC and thermal conditions.
6
Assembly Techniques
Thermosonic wedge bonding is the preferred method
for wire attachment to the bond pads. Gold mesh can
be attached using a 2 mil round tracking tool and a tool
force of approximately 22 grams and a ultrasonic power
of roughly 55 dB for a duration of 76 8 mS. The guided
wedge at an ultrasonic power level of 64 dB can be used
for 0.7 mil wire. The recommended wire bond stage tem-
perature is 150 2°C.
The backside of the MMIC chip is RF ground. For mi-
crostrip applications the chip should be attached directly
to the ground plane (e.g. circuit carrier or heatsink) using
[1,2]
electrically conductive epoxy
.
For best performance, the topside of the MMIC should be
brought up to the same height as the circuit surrounding
it. This can be accomplished by mounting a gold plate
metal shim (same length and width as the MMIC) under
the chip which is of correct thickness to make the chip
and adjacent circuit the same height. The amount of
epoxy used for the chip and/or shim attachment should
be just enough to provide a thin fillet around the bottom
perimeter of the chip or shim. The ground plan should
be free of any residue that may jeopardize electrical or
mechanical attachment.
Caution should be taken to not exceed the Absolute
Maximum Rating for assembly temperature and time.
The chip is 100 µm thick and should be handled with care.
This MMIC has exposed air bridges on the top surface and
should be handled by the edges or with a custom collet
(do not pick up the die with a vacuum on die center).
This MMIC is also static sensitive and ESD precautions
should be taken.
Notes:
1. Ablebond 84-1 LM1 silver epoxy is recommended.
2. Eutectic attach is not recommended and may jeopardize reliability
of the device.
The location of the RF bond pads is shown in Figure
24. Note that all the RF input and output ports are in a
Ground-Signal-Ground configuration.
RF connections should be kept as short as reasonable to
minimize performance degradation due to undesirable
series inductance. A single bond wire is normally suf-
ficient for signal connections, however double bonding
with 0.7 mil gold wire or use of gold mesh is recom-
mended for best performance, especially near the high
end of the frequency band.
VdAB
VgD
Vdd
RFin
RFout
Figure 23. AMMC-6120 simplified schematic.
7
1000
715
VdAB
1310
VgD
1478
Vdd
0
660
660
RFI
RFin
472
RFout
0
0
1600
Figure 24. AMMC-6120 bonding pad locations.
Vd
Vg
/100 pF
VdAB
/100 pF
VgD
Vdd
50 OHM LINE
RFin
RFout
50 OHM LINE
Figure 25. AMMC-6120 assembly diagram.
Ordering Information:
AMMC-6120-W10 = 10 devices per tray
AMMC-6120-W50 = 50 devices per tray
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes 5989-3944EN
AV02-0743EN - April 30, 2013
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