BH616UV1611TIG70 [BSI]
Ultra Low Power/High Speed CMOS SRAM 1M X 16 bit / 2M x 8-bit; 超低功耗/高速CMOS SRAM 1M X 16位/ 2M ×8位型号: | BH616UV1611TIG70 |
厂家: | BRILLIANCE SEMICONDUCTOR |
描述: | Ultra Low Power/High Speed CMOS SRAM 1M X 16 bit / 2M x 8-bit |
文件: | 总12页 (文件大小:149K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ultra Low Power/High Speed CMOS SRAM
1M X 16 bit / 2M x 8-bit
BH616UV1611
Pb-Free and Green package materials are compliant to RoHS
n FEATURES
n DESCRIPTION
Ÿ Wide VCC low operation voltage : 1.65V ~ 3.6V
The BH616UV1611 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 1,048,576 by 16 bits
and operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with typical operating current of
1.5mA at 1MHz at 3.0V/25OC and maximum access time of 55ns at
1.65V/85OC.
Ÿ Ultra low power consumption :
VCC = 3.6V
Operation current :10mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 5.0uA (Typ.) at 3.0V/25OC
Data retention current : 1.5uA(Typ.) at 25OC
VCC = 1.2V
Ÿ High speed access time :
-55
-70
55ns (Max.) at VCC=1.65~3.6V
70ns (Max.) at VCC=1.65~3.6V
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
Ÿ Automatic power down when chip is deselected
Ÿ Easy expansion with CE1, CE2 and OE options
Ÿ I/O Configuration x8/x16 selectable by LB and UB pin.
Ÿ Three state outputs and TTL compatible
The BH616UV1611 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BH616UV1611 is available in DICE form, JEDEC standard
48-pin TSOP-I and 48-ball BGA package.
Ÿ Fully static operation, no clock, no refresh
Ÿ Data retention supply voltage as low as 1.0V
n POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
VCC=3.6V
10MHz
VCC=1.8V
10MHz
VCC=3.6V VCC=1.8V
1MHz
2mA
fMax.
1MHz
fMax.
BH616UV1611DI
BH616UV1611BI
BH616UV1611TI
DICE
Industrial
30uA
25uA
6mA
10mA
1.5mA
5mA
8mA
BGA-48-0810
TSOP I-48
-40OC to +85OC
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
A15
A14
A13
DQ15/A20
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
A12
A11
A10
A9
Address
Input
1024
Memory Array
1024 x 16384
10
A8
Row
Decoder
A19
NC
WE
CE2
NC
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Buffer
A8
BH616UV1611TI
A19
A18
16384
DQ0
Column I/O
16
16
Data
Input
Buffer
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
.
VSS
CE1
A0
16
16
.
Data
Output
Buffer
.
.
1024
1
2
3
4
5
6
Column Decoder
DQ15
CE2
A
B
C
D
E
F
LB
OE
A0
A1
A2
10
CE2, CE1
WE
DQ8
UB
A3
A5
A4
A6
CE1
DQ1
DQ3
DQ4
DQ5
WE
DQ0
DQ2
VCC
VSS
DQ6
DQ7
NC
Address Input Buffer
OE
Control
UB
DQ9 DQ10
VSS DQ11
VCC DQ12
LB
A 16 A 0 A 17 A 7 A 6 A 5 A 4 A 3 A 2 A 1
A17
NC
A7
VCC
VSS
A16
A15
A13
A10
DQ14 DQ13 A14
G
H
DQ15 A19
A12
A9
A18
A8
A11
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV1611
Revision 1.3
Otc. 2006
1
BH616UV1611
n PIN DESCRIPTIONS
Name
Function
These 20 address inputs select one of the 1,024K x 16 bit in the RAM, if BYTE is HIGH
A0 to A19 Address Input (word mode)
These 21 address inputs select one of the 2,048K x 8 bit in the RAM, If BYTE is LOW
A0 to A20 Address Input (byte mode)
(TSOP only)
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
BYTE Byte Enable Input (TSOP only)
This input selects the organization of the SRAM. 1,024K x 16-bit configuration is
selected if BYTE is HIGH. 2,048K x 8-bit configuration is selected if BYTE is LOW
16 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ15 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
Revision 1.3
R0201-BH616UV1611
2
Otc.
2006
BH616UV1611
n TRUTH TABLE
Byte Mode (TSOP only)
VCC
CURRENT
MODE
CE2
DQ0~DQ7 DQ8~DQ14 DQ15
UB BYTE
CE1
WE
OE
LB
Chip
De-selected
(Power Down)
H
X
L
X
L
X
X
H
X
X
H
X
X
X
X
X
X
L
L
L
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
ICCSB, ICCSB1
ICCSB, ICCSB1
Output
Disabled
Read
(byte mode)
Write
(byte mode)
H
ICC
ICC
ICC
L
L
H
H
H
L
L
X
X
X
X
L
L
DOUT
DIN
High Z
X
A20
A20
X
Word Mode
MODE
VCC
CURRENT
CE2
DQ0~DQ7 DQ8~DQ14 DQ15
UB BYTE
CE1
WE
OE
LB
H
X
X
L
X
L
X
X
X
H
X
X
X
H
X
X
H
X
L
X
X
H
X
L
H
H
H
H
H
H
H
H
H
H
High Z
High Z
High Z
High Z
DOUT
High Z
DOUT
DIN
High Z
High Z
High Z
High Z
DOUT
DOUT
High Z
DIN
High Z
High Z
High Z
High Z
DOUT
DOUT
High Z
DIN
ICCSB, ICCSB1
Chip
De-selected
(Power Down)
ICCSB, ICCSB1
X
H
ICCSB, ICCSB1
Output
Disabled
ICC
ICC
ICC
ICC
ICC
ICC
ICC
Read
(word mode)
L
L
H
H
H
L
L
H
L
L
H
L
L
Write
(word mode)
X
H
L
L
X
DIN
DIN
H
DIN
X
X
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
48BGA ignore BYTE condition.
Revision 1.3
R0201-BH616UV1611
3
Otc.
2006
BH616UV1611
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
-40OC to + 85OC
SYMBOL
PARAMETER
RATING
UNITS
RANG
VCC
Terminal Voltage with
Respect to GND
VTERM
-0.5(2) to 4.6V
V
Industrial
1.65V ~ 3.6V
Temperature Under
Bias
TBIAS
TSTG
PT
-40 to +125
-60 to +150
1.0
OC
OC
W
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
Storage Temperature
Power Dissipation
DC Output Current
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
IOUT
20
mA
Input
Capacitance
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
NAME
1.65
--
3.6
V
VCC
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
0.4
0.8
Input Low Voltage
Input High Voltage
Input Leakage Current
-0.3(2)
--
--
--
V
V
VIL
VIH
IIL
1.4
2.2
VCC+0.3(3)
VIN = 0V to VCC
,
--
--
--
1
uA
CE1 = VIH or CE2 = VIL
VI/O = 0V to VCC,
Output Leakage Current
--
1
uA
ILO
CE1 = VIH or CE2 = VIL or OE = VIH or
UB = LB = VIH
VCC=1.8V
VCC = Max, IOL = 0.2mA
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -0.1mA
VCC = Min, IOH = -1.0mA
0.2
0.4
Output Low Voltage
Output High Voltage
--
--
V
VOL
VOH
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC=1.8V
VCC=3.6V
VCC-0.2
2.4
--
V
6
8
CE1 = VIL and CE2 = VIH,
Operating Power Supply
Current
--
--
--
--
mA
mA
mA
uA
ICC
(4)
8
10
IDQ = 0mA, f = FMAX
1.0
1.5
1.5
2.0
0.5
1.0
25
CE1 = VIL and CE2 = VIH,
IDQ = 0mA, f = 1MHz
Operating Power Supply
Current
ICC1
CE1 = VIH, or CE2 = VIL,
IDQ = 0mA
Standby Current – TTL
--
ICCSB
4.0
5.0(5)
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
Standby Current – CMOS
ICCSB1
30
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. VCC=3.0V
Revision 1.3
Otc. 2006
R0201-BH616UV1611
4
BH616UV1611
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VCC for Data Retention
1.0
--
--
V
VCC=1.2V
Data Retention Current
--
0
1.5
--
15
--
uA
ns
ns
ICCDR
tCDR
tR
Chip Deselect to Data
Retention Time
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
--
1. Typical characteristics are at TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE1≧VCC - 0.2V
VIH
VIH
CE1
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
V
DR≧1.0V
VCC
VCC
VCC
tCDR
tR
CE2≦0.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
Input Pulse Levels
VCC / 0V
1V/ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
MUST BE
STEADY
MUST BE
STEADY
Input and Output Timing
Reference Level
0.5Vcc
tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1
tCHZ2, tBDO, tOHZ, tWHZ, tOW
,
MAY CHANGE
FROM “H” TO “L”
WILL BE CHANGE
FROM “H” TO “L”
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
VCC
GND
CHANGE :
STATE UNKNOW
1 TTL
90%
90%
Output
10%
10%
(1)
®
¬
®
¬
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL
DOES NOT
APPLY
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
Revision 1.3
R0201-BH616UV1611
5
Otc.
2006
BH616UV1611
n BYTE FUNCTION
PARAMETER
NAME
MIN.
MAX.
UNITS
PARAMETER
BYTE Setup Time
BYTE Recovery Time
tBS
tBR
5
5
--
--
ms
ms
CE2
CE1
tBS
tBR
BYTE
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns CYCLE TIME : 70ns
MIN. TYP. MAX. MIN. TYP. MAX.
PARANETER
DESCRIPTION
Read Cycle Time
UNITS
NAME
tAVAX
tAVQX
tE1LQV
tE2LQV
tBLQV
tGLQV
tE1LQX
tE2LQX
tBLQX
tGLQX
tE1HQZ
tE2HQZ
tBHQZ
tGHQZ
tAVQX
tRC
tAA
55
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
55
25
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
70
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
(CE1)
tACS1
tACS2
tBA
--
--
Chip Select Access Time
(CE2)
--
--
Data Byte Control Access Time
(LB, UB)
--
--
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
--
--
(CE1)
tCLZ1
tCLZ2
tBE
10
10
10
10
5
Chip Select to Output Low Z
(CE2) 10
--
--
Data Byte Control to Output Low Z (LB, UB)
Output Enable to Output Low Z
10
5
--
--
tOLZ
tCHZ1
tCHZ2
tBDO
tOHZ
tOH
--
--
Chip Deselect to Output High Z
Chip Deselect to Output High Z
(CE1)
(CE2)
--
25
25
25
25
--
--
35
35
35
30
--
--
--
Data Byte Control to Output High Z (LB, UB)
Output Disable to Output High Z
--
--
--
--
Data Hold from Address Change
10
10
Revision 1.3
Otc. 2006
R0201-BH616UV1611
6
BH616UV1611
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
(6)
tACS2
(5, 6)
tCHZ
(5,6)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
tACS1
tO(H1Z,5)
(5)
tCLZ1
tCHZ
CE2
tACS2
(5)
(2,5)
tCLZ2
tCHZ2
tBA
tBE
LB, UB
DOUT
tBDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision 1.3
R0201-BH616UV1611
7
Otc.
2006
BH616UV1611
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns CYCLE TIME : 70ns
MIN. TYP. MAX. MIN. TYP. MAX.
PARANETER
DESCRIPTION
UNITS
NAME
tAVAX
tAVWL
tAVWH
tELWH
tBLWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAS
Write Cycle Time
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set up Time
tAW
tCW
tBW
tWP
tWR1
tWR2
tWHZ
tDW
tDH
Address Valid to End of Write
Chip Select to End of Write
Data Byte Control to End of Write
40
40
40
30
0
--
60
60
60
35
0
--
--
--
(LB, UB)
--
--
Write Pulse Width
--
--
Write Recovery Time
(CE1, WE)
(CE2)
--
--
Write Recovery Time
0
--
0
--
Write to Output High Z
--
20
--
--
30
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
25
0
30
0
--
--
tOHZ
tOW
--
25
--
--
30
--
5
5
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
(5)
CE1
CE2
(11)
tCW
(3)
tWR2
tBW
LB, UB
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 1.3
Otc. 2006
R0201-BH616UV1611
8
BH616UV1611
WRITE CYCLE 2 (1,6)
ADDRESS
tWC
(11)
tCW
(5)
CE1
CE2
(5)
(11)
tCW
tBW
(3)
tWR
(12)
LB, UB
WE
tAW
(2)
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE
low. All signals must be active to initiate a write and any one signal can terminate a write by
going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data
input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision 1.3
R0201-BH616UV1611
9
Otc.
2006
BH616UV1611
n ORDERING INFORMATION
BH616UV1611 X
X
Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
I: -40oC ~ +85oC
PACKAGE
D: Dice
B: BGA-48-0810
T: TSOP I-48
Note:
Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
D
E
D1
E1
e
48
10.0
8.0
5.25
3.75
0.75
SOLDER BALL
0.35 ± 0.05
VIEW A
48 mini-BGA (8 x 10mm)
Revision 1.3
R0201-BH616UV1611
10
Otc.
2006
BH616UV1611
n PACKAGE DIMENSIONS
TSOP I-48 Pin (12mm x 20mm)
Revision 1.3
R0201-BH616UV1611
11
Otc.
2006
BH616UV1611
n Revision History
Revision No.
History
Draft Date
Remark
Initial
1.0
1.1
Initial Production Version
May 10,2006
May 25, 2006
Change I-grade operation temperature range
- from –25OC to –40OC
1.2
1.3
Add Part Number for 70ns
July 21, 2006
Otc 22, 2006
Add DICE form and 48 TSOP-I package type
Change BGA package dimension for single chip solution
- form 6x8 mm to 8x10mm
Improve Spec.
- ICC(MAX.) from 12mA to 10mA for VCC=3.6V
- ICCsb1(TYP.) from 5.0uA to 4.0uA for VCC=1.8V
- ICCDR(TYP.) from 2.5uA to 1.5uA for VCC=1.2V
- tOE(MIN.) from 30ns to 25ns
- tAW(MIN.) from 45ns to 40ns
- tCW(MIN.) from 45ns to 40ns
- tBW(MIN.) from 45ns to 40ns
Revision 1.3
R0201-BH616UV1611
12
Otc.
2006
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